15161a55cSBen Widawsky /* SPDX-License-Identifier: GPL-2.0-only */ 25161a55cSBen Widawsky /* Copyright(c) 2020-2021 Intel Corporation. */ 35161a55cSBen Widawsky #ifndef __CXL_MEM_H__ 45161a55cSBen Widawsky #define __CXL_MEM_H__ 54faf31b4SDan Williams #include <uapi/linux/cxl_mem.h> 65161a55cSBen Widawsky #include <linux/cdev.h> 75161a55cSBen Widawsky #include "cxl.h" 85161a55cSBen Widawsky 95161a55cSBen Widawsky /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */ 105161a55cSBen Widawsky #define CXLMDEV_STATUS_OFFSET 0x0 115161a55cSBen Widawsky #define CXLMDEV_DEV_FATAL BIT(0) 125161a55cSBen Widawsky #define CXLMDEV_FW_HALT BIT(1) 135161a55cSBen Widawsky #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2) 145161a55cSBen Widawsky #define CXLMDEV_MS_NOT_READY 0 155161a55cSBen Widawsky #define CXLMDEV_MS_READY 1 165161a55cSBen Widawsky #define CXLMDEV_MS_ERROR 2 175161a55cSBen Widawsky #define CXLMDEV_MS_DISABLED 3 185161a55cSBen Widawsky #define CXLMDEV_READY(status) \ 195161a55cSBen Widawsky (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \ 205161a55cSBen Widawsky CXLMDEV_MS_READY) 215161a55cSBen Widawsky #define CXLMDEV_MBOX_IF_READY BIT(4) 225161a55cSBen Widawsky #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5) 235161a55cSBen Widawsky #define CXLMDEV_RESET_NEEDED_NOT 0 245161a55cSBen Widawsky #define CXLMDEV_RESET_NEEDED_COLD 1 255161a55cSBen Widawsky #define CXLMDEV_RESET_NEEDED_WARM 2 265161a55cSBen Widawsky #define CXLMDEV_RESET_NEEDED_HOT 3 275161a55cSBen Widawsky #define CXLMDEV_RESET_NEEDED_CXL 4 285161a55cSBen Widawsky #define CXLMDEV_RESET_NEEDED(status) \ 295161a55cSBen Widawsky (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \ 305161a55cSBen Widawsky CXLMDEV_RESET_NEEDED_NOT) 315161a55cSBen Widawsky 325161a55cSBen Widawsky /** 335161a55cSBen Widawsky * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device 345161a55cSBen Widawsky * @dev: driver core device object 355161a55cSBen Widawsky * @cdev: char dev core object for ioctl operations 365e2411aeSIra Weiny * @cxlds: The device state backing this device 378dd2bc0fSBen Widawsky * @detach_work: active memdev lost a port in its ancestry 38f17b558dSDan Williams * @cxl_nvb: coordinate removal of @cxl_nvd if present 39f17b558dSDan Williams * @cxl_nvd: optional bridge to an nvdimm if the device supports pmem 405161a55cSBen Widawsky * @id: id number of this memdev instance. 415161a55cSBen Widawsky */ 425161a55cSBen Widawsky struct cxl_memdev { 435161a55cSBen Widawsky struct device dev; 445161a55cSBen Widawsky struct cdev cdev; 455e2411aeSIra Weiny struct cxl_dev_state *cxlds; 468dd2bc0fSBen Widawsky struct work_struct detach_work; 47f17b558dSDan Williams struct cxl_nvdimm_bridge *cxl_nvb; 48f17b558dSDan Williams struct cxl_nvdimm *cxl_nvd; 495161a55cSBen Widawsky int id; 505161a55cSBen Widawsky }; 515161a55cSBen Widawsky 523d135db5SBen Widawsky static inline struct cxl_memdev *to_cxl_memdev(struct device *dev) 533d135db5SBen Widawsky { 543d135db5SBen Widawsky return container_of(dev, struct cxl_memdev, dev); 553d135db5SBen Widawsky } 563d135db5SBen Widawsky 579c57cde0SDan Williams static inline struct cxl_port *cxled_to_port(struct cxl_endpoint_decoder *cxled) 589c57cde0SDan Williams { 599c57cde0SDan Williams return to_cxl_port(cxled->cxld.dev.parent); 609c57cde0SDan Williams } 619c57cde0SDan Williams 62384e624bSDan Williams static inline struct cxl_port *cxlrd_to_port(struct cxl_root_decoder *cxlrd) 63384e624bSDan Williams { 64384e624bSDan Williams return to_cxl_port(cxlrd->cxlsd.cxld.dev.parent); 65384e624bSDan Williams } 66384e624bSDan Williams 679c57cde0SDan Williams static inline struct cxl_memdev * 689c57cde0SDan Williams cxled_to_memdev(struct cxl_endpoint_decoder *cxled) 699c57cde0SDan Williams { 709c57cde0SDan Williams struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent); 719c57cde0SDan Williams 729c57cde0SDan Williams return to_cxl_memdev(port->uport); 739c57cde0SDan Williams } 749c57cde0SDan Williams 758dd2bc0fSBen Widawsky bool is_cxl_memdev(struct device *dev); 768dd2bc0fSBen Widawsky static inline bool is_cxl_endpoint(struct cxl_port *port) 778dd2bc0fSBen Widawsky { 788dd2bc0fSBen Widawsky return is_cxl_memdev(port->uport); 798dd2bc0fSBen Widawsky } 808dd2bc0fSBen Widawsky 815e2411aeSIra Weiny struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds); 823d135db5SBen Widawsky 83*7592d935SDan Williams static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port, 84*7592d935SDan Williams struct cxl_memdev *cxlmd) 85*7592d935SDan Williams { 86*7592d935SDan Williams if (!port) 87*7592d935SDan Williams return NULL; 88*7592d935SDan Williams 89*7592d935SDan Williams return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev); 90*7592d935SDan Williams } 91*7592d935SDan Williams 925161a55cSBen Widawsky /** 93b64955a9SDan Williams * struct cxl_mbox_cmd - A command to be submitted to hardware. 94b64955a9SDan Williams * @opcode: (input) The command set and command submitted to hardware. 95b64955a9SDan Williams * @payload_in: (input) Pointer to the input payload. 96b64955a9SDan Williams * @payload_out: (output) Pointer to the output payload. Must be allocated by 97b64955a9SDan Williams * the caller. 98b64955a9SDan Williams * @size_in: (input) Number of bytes to load from @payload_in. 99b64955a9SDan Williams * @size_out: (input) Max number of bytes loaded into @payload_out. 100b64955a9SDan Williams * (output) Number of bytes generated by the device. For fixed size 101b64955a9SDan Williams * outputs commands this is always expected to be deterministic. For 102b64955a9SDan Williams * variable sized output commands, it tells the exact number of bytes 103b64955a9SDan Williams * written. 104b64955a9SDan Williams * @return_code: (output) Error code returned from hardware. 105b64955a9SDan Williams * 106b64955a9SDan Williams * This is the primary mechanism used to send commands to the hardware. 107b64955a9SDan Williams * All the fields except @payload_* correspond exactly to the fields described in 108b64955a9SDan Williams * Command Register section of the CXL 2.0 8.2.8.4.5. @payload_in and 109b64955a9SDan Williams * @payload_out are written to, and read from the Command Payload Registers 110b64955a9SDan Williams * defined in CXL 2.0 8.2.8.4.8. 111b64955a9SDan Williams */ 112b64955a9SDan Williams struct cxl_mbox_cmd { 113b64955a9SDan Williams u16 opcode; 114b64955a9SDan Williams void *payload_in; 115b64955a9SDan Williams void *payload_out; 116b64955a9SDan Williams size_t size_in; 117b64955a9SDan Williams size_t size_out; 118b64955a9SDan Williams u16 return_code; 119b64955a9SDan Williams }; 120b64955a9SDan Williams 121b64955a9SDan Williams /* 12292fcc1abSDavidlohr Bueso * Per CXL 2.0 Section 8.2.8.4.5.1 12392fcc1abSDavidlohr Bueso */ 12492fcc1abSDavidlohr Bueso #define CMD_CMD_RC_TABLE \ 12592fcc1abSDavidlohr Bueso C(SUCCESS, 0, NULL), \ 12692fcc1abSDavidlohr Bueso C(BACKGROUND, -ENXIO, "background cmd started successfully"), \ 12792fcc1abSDavidlohr Bueso C(INPUT, -ENXIO, "cmd input was invalid"), \ 12892fcc1abSDavidlohr Bueso C(UNSUPPORTED, -ENXIO, "cmd is not supported"), \ 12992fcc1abSDavidlohr Bueso C(INTERNAL, -ENXIO, "internal device error"), \ 13092fcc1abSDavidlohr Bueso C(RETRY, -ENXIO, "temporary error, retry once"), \ 13192fcc1abSDavidlohr Bueso C(BUSY, -ENXIO, "ongoing background operation"), \ 13292fcc1abSDavidlohr Bueso C(MEDIADISABLED, -ENXIO, "media access is disabled"), \ 13392fcc1abSDavidlohr Bueso C(FWINPROGRESS, -ENXIO, "one FW package can be transferred at a time"), \ 13492fcc1abSDavidlohr Bueso C(FWOOO, -ENXIO, "FW package content was transferred out of order"), \ 13592fcc1abSDavidlohr Bueso C(FWAUTH, -ENXIO, "FW package authentication failed"), \ 13692fcc1abSDavidlohr Bueso C(FWSLOT, -ENXIO, "FW slot is not supported for requested operation"), \ 13792fcc1abSDavidlohr Bueso C(FWROLLBACK, -ENXIO, "rolled back to the previous active FW"), \ 13892fcc1abSDavidlohr Bueso C(FWRESET, -ENXIO, "FW failed to activate, needs cold reset"), \ 13992fcc1abSDavidlohr Bueso C(HANDLE, -ENXIO, "one or more Event Record Handles were invalid"), \ 14092fcc1abSDavidlohr Bueso C(PADDR, -ENXIO, "physical address specified is invalid"), \ 14192fcc1abSDavidlohr Bueso C(POISONLMT, -ENXIO, "poison injection limit has been reached"), \ 14292fcc1abSDavidlohr Bueso C(MEDIAFAILURE, -ENXIO, "permanent issue with the media"), \ 14392fcc1abSDavidlohr Bueso C(ABORT, -ENXIO, "background cmd was aborted by device"), \ 14492fcc1abSDavidlohr Bueso C(SECURITY, -ENXIO, "not valid in the current security state"), \ 14592fcc1abSDavidlohr Bueso C(PASSPHRASE, -ENXIO, "phrase doesn't match current set passphrase"), \ 14692fcc1abSDavidlohr Bueso C(MBUNSUPPORTED, -ENXIO, "unsupported on the mailbox it was issued on"),\ 14792fcc1abSDavidlohr Bueso C(PAYLOADLEN, -ENXIO, "invalid payload length") 14892fcc1abSDavidlohr Bueso 14992fcc1abSDavidlohr Bueso #undef C 15092fcc1abSDavidlohr Bueso #define C(a, b, c) CXL_MBOX_CMD_RC_##a 15192fcc1abSDavidlohr Bueso enum { CMD_CMD_RC_TABLE }; 15292fcc1abSDavidlohr Bueso #undef C 15392fcc1abSDavidlohr Bueso #define C(a, b, c) { b, c } 15492fcc1abSDavidlohr Bueso struct cxl_mbox_cmd_rc { 15592fcc1abSDavidlohr Bueso int err; 15692fcc1abSDavidlohr Bueso const char *desc; 15792fcc1abSDavidlohr Bueso }; 15892fcc1abSDavidlohr Bueso 15992fcc1abSDavidlohr Bueso static const 16092fcc1abSDavidlohr Bueso struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE }; 16192fcc1abSDavidlohr Bueso #undef C 16292fcc1abSDavidlohr Bueso 16392fcc1abSDavidlohr Bueso static inline const char *cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd *mbox_cmd) 16492fcc1abSDavidlohr Bueso { 16592fcc1abSDavidlohr Bueso return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc; 16692fcc1abSDavidlohr Bueso } 16792fcc1abSDavidlohr Bueso 16892fcc1abSDavidlohr Bueso static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd) 16992fcc1abSDavidlohr Bueso { 17092fcc1abSDavidlohr Bueso return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err; 17192fcc1abSDavidlohr Bueso } 17292fcc1abSDavidlohr Bueso 17392fcc1abSDavidlohr Bueso /* 174b64955a9SDan Williams * CXL 2.0 - Memory capacity multiplier 175b64955a9SDan Williams * See Section 8.2.9.5 176b64955a9SDan Williams * 177b64955a9SDan Williams * Volatile, Persistent, and Partition capacities are specified to be in 178b64955a9SDan Williams * multiples of 256MB - define a multiplier to convert to/from bytes. 179b64955a9SDan Williams */ 180b64955a9SDan Williams #define CXL_CAPACITY_MULTIPLIER SZ_256M 181b64955a9SDan Williams 182b64955a9SDan Williams /** 183560f7855SBen Widawsky * struct cxl_endpoint_dvsec_info - Cached DVSEC info 184560f7855SBen Widawsky * @mem_enabled: cached value of mem_enabled in the DVSEC, PCIE_DEVICE 185560f7855SBen Widawsky * @ranges: Number of active HDM ranges this device uses. 186560f7855SBen Widawsky * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE 187560f7855SBen Widawsky */ 188560f7855SBen Widawsky struct cxl_endpoint_dvsec_info { 189560f7855SBen Widawsky bool mem_enabled; 190560f7855SBen Widawsky int ranges; 191560f7855SBen Widawsky struct range dvsec_range[2]; 192560f7855SBen Widawsky }; 193560f7855SBen Widawsky 194560f7855SBen Widawsky /** 1955e2411aeSIra Weiny * struct cxl_dev_state - The driver device state 1965e2411aeSIra Weiny * 1975e2411aeSIra Weiny * cxl_dev_state represents the CXL driver/device state. It provides an 1985e2411aeSIra Weiny * interface to mailbox commands as well as some cached data about the device. 1995e2411aeSIra Weiny * Currently only memory devices are represented. 2005e2411aeSIra Weiny * 2015e2411aeSIra Weiny * @dev: The device associated with this CXL state 2025161a55cSBen Widawsky * @regs: Parsed register blocks 20306e279e5SBen Widawsky * @cxl_dvsec: Offset to the PCIe device DVSEC 2045161a55cSBen Widawsky * @payload_size: Size of space for payload 2055161a55cSBen Widawsky * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register) 2065161a55cSBen Widawsky * @lsa_size: Size of Label Storage Area 2075161a55cSBen Widawsky * (CXL 2.0 8.2.9.5.1.1 Identify Memory Device) 2085161a55cSBen Widawsky * @mbox_mutex: Mutex to synchronize mailbox access. 2095161a55cSBen Widawsky * @firmware_version: Firmware version for the memory device. 2105161a55cSBen Widawsky * @enabled_cmds: Hardware commands found enabled in CEL. 21112f3856aSDan Williams * @exclusive_cmds: Commands that are kernel-internal only 212d3b75029SDan Williams * @dpa_res: Overall DPA resource tree for the device 213d3b75029SDan Williams * @pmem_res: Active Persistent memory capacity configuration 214d3b75029SDan Williams * @ram_res: Active Volatile memory capacity configuration 21513e7749dSDan Williams * @total_bytes: sum of all possible capacities 21613e7749dSDan Williams * @volatile_only_bytes: hard volatile capacity 21713e7749dSDan Williams * @persistent_only_bytes: hard persistent capacity 21813e7749dSDan Williams * @partition_align_bytes: alignment size for partition-able capacity 21913e7749dSDan Williams * @active_volatile_bytes: sum of hard + soft volatile 22013e7749dSDan Williams * @active_persistent_bytes: sum of hard + soft persistent 22113e7749dSDan Williams * @next_volatile_bytes: volatile capacity change pending device reset 22213e7749dSDan Williams * @next_persistent_bytes: persistent capacity change pending device reset 2234112a08dSBen Widawsky * @component_reg_phys: register base of component registers 224560f7855SBen Widawsky * @info: Cached DVSEC information about the device. 225bcc79ea3SDan Williams * @serial: PCIe Device Serial Number 2263eddcc93SIra Weiny * @doe_mbs: PCI DOE mailbox array 227b64955a9SDan Williams * @mbox_send: @dev specific transport for transmitting mailbox commands 22813e7749dSDan Williams * 22913e7749dSDan Williams * See section 8.2.9.5.2 Capacity Configuration and Label Storage for 23013e7749dSDan Williams * details on capacity parameters. 2315161a55cSBen Widawsky */ 2325e2411aeSIra Weiny struct cxl_dev_state { 23399e222a5SDan Williams struct device *dev; 2345161a55cSBen Widawsky 2355161a55cSBen Widawsky struct cxl_regs regs; 23606e279e5SBen Widawsky int cxl_dvsec; 2375161a55cSBen Widawsky 2385161a55cSBen Widawsky size_t payload_size; 2395161a55cSBen Widawsky size_t lsa_size; 2405161a55cSBen Widawsky struct mutex mbox_mutex; /* Protects device mailbox and firmware */ 2415161a55cSBen Widawsky char firmware_version[0x10]; 242ff56ab9eSDan Williams DECLARE_BITMAP(enabled_cmds, CXL_MEM_COMMAND_ID_MAX); 24312f3856aSDan Williams DECLARE_BITMAP(exclusive_cmds, CXL_MEM_COMMAND_ID_MAX); 2445161a55cSBen Widawsky 245d3b75029SDan Williams struct resource dpa_res; 246d3b75029SDan Williams struct resource pmem_res; 247d3b75029SDan Williams struct resource ram_res; 2480b9159d0SIra Weiny u64 total_bytes; 2490b9159d0SIra Weiny u64 volatile_only_bytes; 2500b9159d0SIra Weiny u64 persistent_only_bytes; 2510b9159d0SIra Weiny u64 partition_align_bytes; 252f847502aSIra Weiny 253f847502aSIra Weiny u64 active_volatile_bytes; 254f847502aSIra Weiny u64 active_persistent_bytes; 255f847502aSIra Weiny u64 next_volatile_bytes; 256f847502aSIra Weiny u64 next_persistent_bytes; 257b64955a9SDan Williams 2584112a08dSBen Widawsky resource_size_t component_reg_phys; 259bcc79ea3SDan Williams u64 serial; 2604112a08dSBen Widawsky 2613eddcc93SIra Weiny struct xarray doe_mbs; 2623eddcc93SIra Weiny 2635e2411aeSIra Weiny int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd); 2645161a55cSBen Widawsky }; 2654faf31b4SDan Williams 2664faf31b4SDan Williams enum cxl_opcode { 2674faf31b4SDan Williams CXL_MBOX_OP_INVALID = 0x0000, 2684faf31b4SDan Williams CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID, 2694faf31b4SDan Williams CXL_MBOX_OP_GET_FW_INFO = 0x0200, 2704faf31b4SDan Williams CXL_MBOX_OP_ACTIVATE_FW = 0x0202, 2714faf31b4SDan Williams CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400, 2724faf31b4SDan Williams CXL_MBOX_OP_GET_LOG = 0x0401, 2734faf31b4SDan Williams CXL_MBOX_OP_IDENTIFY = 0x4000, 2744faf31b4SDan Williams CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100, 2754faf31b4SDan Williams CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101, 2764faf31b4SDan Williams CXL_MBOX_OP_GET_LSA = 0x4102, 2774faf31b4SDan Williams CXL_MBOX_OP_SET_LSA = 0x4103, 2784faf31b4SDan Williams CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200, 2794faf31b4SDan Williams CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201, 2804faf31b4SDan Williams CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202, 2814faf31b4SDan Williams CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203, 2824faf31b4SDan Williams CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204, 2834faf31b4SDan Williams CXL_MBOX_OP_GET_POISON = 0x4300, 2844faf31b4SDan Williams CXL_MBOX_OP_INJECT_POISON = 0x4301, 2854faf31b4SDan Williams CXL_MBOX_OP_CLEAR_POISON = 0x4302, 2864faf31b4SDan Williams CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303, 2874faf31b4SDan Williams CXL_MBOX_OP_SCAN_MEDIA = 0x4304, 2884faf31b4SDan Williams CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305, 2894faf31b4SDan Williams CXL_MBOX_OP_MAX = 0x10000 2904faf31b4SDan Williams }; 2914faf31b4SDan Williams 29249be6dd8SDan Williams #define DEFINE_CXL_CEL_UUID \ 29349be6dd8SDan Williams UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62, \ 29449be6dd8SDan Williams 0x3b, 0x3f, 0x17) 29549be6dd8SDan Williams 29649be6dd8SDan Williams #define DEFINE_CXL_VENDOR_DEBUG_UUID \ 29749be6dd8SDan Williams UUID_INIT(0xe1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \ 29849be6dd8SDan Williams 0x40, 0x3d, 0x86) 29949be6dd8SDan Williams 30049be6dd8SDan Williams struct cxl_mbox_get_supported_logs { 30149be6dd8SDan Williams __le16 entries; 30249be6dd8SDan Williams u8 rsvd[6]; 30349be6dd8SDan Williams struct cxl_gsl_entry { 30449be6dd8SDan Williams uuid_t uuid; 30549be6dd8SDan Williams __le32 size; 30649be6dd8SDan Williams } __packed entry[]; 30749be6dd8SDan Williams } __packed; 30849be6dd8SDan Williams 30949be6dd8SDan Williams struct cxl_cel_entry { 31049be6dd8SDan Williams __le16 opcode; 31149be6dd8SDan Williams __le16 effect; 31249be6dd8SDan Williams } __packed; 31349be6dd8SDan Williams 31449be6dd8SDan Williams struct cxl_mbox_get_log { 31549be6dd8SDan Williams uuid_t uuid; 31649be6dd8SDan Williams __le32 offset; 31749be6dd8SDan Williams __le32 length; 31849be6dd8SDan Williams } __packed; 31949be6dd8SDan Williams 32049be6dd8SDan Williams /* See CXL 2.0 Table 175 Identify Memory Device Output Payload */ 32149be6dd8SDan Williams struct cxl_mbox_identify { 32249be6dd8SDan Williams char fw_revision[0x10]; 32349be6dd8SDan Williams __le64 total_capacity; 32449be6dd8SDan Williams __le64 volatile_capacity; 32549be6dd8SDan Williams __le64 persistent_capacity; 32649be6dd8SDan Williams __le64 partition_align; 32749be6dd8SDan Williams __le16 info_event_log_size; 32849be6dd8SDan Williams __le16 warning_event_log_size; 32949be6dd8SDan Williams __le16 failure_event_log_size; 33049be6dd8SDan Williams __le16 fatal_event_log_size; 33149be6dd8SDan Williams __le32 lsa_size; 33249be6dd8SDan Williams u8 poison_list_max_mer[3]; 33349be6dd8SDan Williams __le16 inject_poison_limit; 33449be6dd8SDan Williams u8 poison_caps; 33549be6dd8SDan Williams u8 qos_telemetry_caps; 33649be6dd8SDan Williams } __packed; 33749be6dd8SDan Williams 338e7ad1bf6SDan Williams struct cxl_mbox_get_partition_info { 339e7ad1bf6SDan Williams __le64 active_volatile_cap; 340e7ad1bf6SDan Williams __le64 active_persistent_cap; 341e7ad1bf6SDan Williams __le64 next_volatile_cap; 342e7ad1bf6SDan Williams __le64 next_persistent_cap; 343e7ad1bf6SDan Williams } __packed; 344e7ad1bf6SDan Williams 34549be6dd8SDan Williams struct cxl_mbox_get_lsa { 3468a664875SAlison Schofield __le32 offset; 3478a664875SAlison Schofield __le32 length; 34849be6dd8SDan Williams } __packed; 34949be6dd8SDan Williams 35049be6dd8SDan Williams struct cxl_mbox_set_lsa { 3518a664875SAlison Schofield __le32 offset; 3528a664875SAlison Schofield __le32 reserved; 35349be6dd8SDan Williams u8 data[]; 35449be6dd8SDan Williams } __packed; 35549be6dd8SDan Williams 3566179045cSAlison Schofield struct cxl_mbox_set_partition_info { 3576179045cSAlison Schofield __le64 volatile_capacity; 3586179045cSAlison Schofield u8 flags; 3596179045cSAlison Schofield } __packed; 3606179045cSAlison Schofield 3616179045cSAlison Schofield #define CXL_SET_PARTITION_IMMEDIATE_FLAG BIT(0) 3626179045cSAlison Schofield 3634faf31b4SDan Williams /** 3644faf31b4SDan Williams * struct cxl_mem_command - Driver representation of a memory device command 3654faf31b4SDan Williams * @info: Command information as it exists for the UAPI 3664faf31b4SDan Williams * @opcode: The actual bits used for the mailbox protocol 3674faf31b4SDan Williams * @flags: Set of flags effecting driver behavior. 3684faf31b4SDan Williams * 3694faf31b4SDan Williams * * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag 3704faf31b4SDan Williams * will be enabled by the driver regardless of what hardware may have 3714faf31b4SDan Williams * advertised. 3724faf31b4SDan Williams * 3734faf31b4SDan Williams * The cxl_mem_command is the driver's internal representation of commands that 3744faf31b4SDan Williams * are supported by the driver. Some of these commands may not be supported by 3754faf31b4SDan Williams * the hardware. The driver will use @info to validate the fields passed in by 3764faf31b4SDan Williams * the user then submit the @opcode to the hardware. 3774faf31b4SDan Williams * 3784faf31b4SDan Williams * See struct cxl_command_info. 3794faf31b4SDan Williams */ 3804faf31b4SDan Williams struct cxl_mem_command { 3814faf31b4SDan Williams struct cxl_command_info info; 3824faf31b4SDan Williams enum cxl_opcode opcode; 3834faf31b4SDan Williams u32 flags; 3844faf31b4SDan Williams #define CXL_CMD_FLAG_NONE 0 3854faf31b4SDan Williams #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0) 3864faf31b4SDan Williams }; 3874faf31b4SDan Williams 3885e2411aeSIra Weiny int cxl_mbox_send_cmd(struct cxl_dev_state *cxlds, u16 opcode, void *in, 3894faf31b4SDan Williams size_t in_size, void *out, size_t out_size); 3905e2411aeSIra Weiny int cxl_dev_state_identify(struct cxl_dev_state *cxlds); 3912e4ba0ecSDan Williams int cxl_await_media_ready(struct cxl_dev_state *cxlds); 3925e2411aeSIra Weiny int cxl_enumerate_cmds(struct cxl_dev_state *cxlds); 3935e2411aeSIra Weiny int cxl_mem_create_range_info(struct cxl_dev_state *cxlds); 3945e2411aeSIra Weiny struct cxl_dev_state *cxl_dev_state_create(struct device *dev); 3955e2411aeSIra Weiny void set_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds); 3965e2411aeSIra Weiny void clear_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds); 3979ea4dcf4SDan Williams #ifdef CONFIG_CXL_SUSPEND 3989ea4dcf4SDan Williams void cxl_mem_active_inc(void); 3999ea4dcf4SDan Williams void cxl_mem_active_dec(void); 4009ea4dcf4SDan Williams #else 4019ea4dcf4SDan Williams static inline void cxl_mem_active_inc(void) 4029ea4dcf4SDan Williams { 4039ea4dcf4SDan Williams } 4049ea4dcf4SDan Williams static inline void cxl_mem_active_dec(void) 4059ea4dcf4SDan Williams { 4069ea4dcf4SDan Williams } 4079ea4dcf4SDan Williams #endif 408d17d0540SDan Williams 409d17d0540SDan Williams struct cxl_hdm { 410d17d0540SDan Williams struct cxl_component_regs regs; 411d17d0540SDan Williams unsigned int decoder_count; 412d17d0540SDan Williams unsigned int target_count; 413d17d0540SDan Williams unsigned int interleave_mask; 414d17d0540SDan Williams struct cxl_port *port; 415d17d0540SDan Williams }; 416cc2a4878SDan Williams 417cc2a4878SDan Williams struct seq_file; 418cc2a4878SDan Williams struct dentry *cxl_debugfs_create_dir(const char *dir); 419cc2a4878SDan Williams void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds); 4205161a55cSBen Widawsky #endif /* __CXL_MEM_H__ */ 421