1*5161a55cSBen Widawsky /* SPDX-License-Identifier: GPL-2.0-only */ 2*5161a55cSBen Widawsky /* Copyright(c) 2020-2021 Intel Corporation. */ 3*5161a55cSBen Widawsky #ifndef __CXL_MEM_H__ 4*5161a55cSBen Widawsky #define __CXL_MEM_H__ 5*5161a55cSBen Widawsky #include <linux/cdev.h> 6*5161a55cSBen Widawsky #include "cxl.h" 7*5161a55cSBen Widawsky 8*5161a55cSBen Widawsky /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */ 9*5161a55cSBen Widawsky #define CXLMDEV_STATUS_OFFSET 0x0 10*5161a55cSBen Widawsky #define CXLMDEV_DEV_FATAL BIT(0) 11*5161a55cSBen Widawsky #define CXLMDEV_FW_HALT BIT(1) 12*5161a55cSBen Widawsky #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2) 13*5161a55cSBen Widawsky #define CXLMDEV_MS_NOT_READY 0 14*5161a55cSBen Widawsky #define CXLMDEV_MS_READY 1 15*5161a55cSBen Widawsky #define CXLMDEV_MS_ERROR 2 16*5161a55cSBen Widawsky #define CXLMDEV_MS_DISABLED 3 17*5161a55cSBen Widawsky #define CXLMDEV_READY(status) \ 18*5161a55cSBen Widawsky (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \ 19*5161a55cSBen Widawsky CXLMDEV_MS_READY) 20*5161a55cSBen Widawsky #define CXLMDEV_MBOX_IF_READY BIT(4) 21*5161a55cSBen Widawsky #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5) 22*5161a55cSBen Widawsky #define CXLMDEV_RESET_NEEDED_NOT 0 23*5161a55cSBen Widawsky #define CXLMDEV_RESET_NEEDED_COLD 1 24*5161a55cSBen Widawsky #define CXLMDEV_RESET_NEEDED_WARM 2 25*5161a55cSBen Widawsky #define CXLMDEV_RESET_NEEDED_HOT 3 26*5161a55cSBen Widawsky #define CXLMDEV_RESET_NEEDED_CXL 4 27*5161a55cSBen Widawsky #define CXLMDEV_RESET_NEEDED(status) \ 28*5161a55cSBen Widawsky (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \ 29*5161a55cSBen Widawsky CXLMDEV_RESET_NEEDED_NOT) 30*5161a55cSBen Widawsky 31*5161a55cSBen Widawsky /* 32*5161a55cSBen Widawsky * An entire PCI topology full of devices should be enough for any 33*5161a55cSBen Widawsky * config 34*5161a55cSBen Widawsky */ 35*5161a55cSBen Widawsky #define CXL_MEM_MAX_DEVS 65536 36*5161a55cSBen Widawsky 37*5161a55cSBen Widawsky /** 38*5161a55cSBen Widawsky * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device 39*5161a55cSBen Widawsky * @dev: driver core device object 40*5161a55cSBen Widawsky * @cdev: char dev core object for ioctl operations 41*5161a55cSBen Widawsky * @cxlm: pointer to the parent device driver data 42*5161a55cSBen Widawsky * @id: id number of this memdev instance. 43*5161a55cSBen Widawsky */ 44*5161a55cSBen Widawsky struct cxl_memdev { 45*5161a55cSBen Widawsky struct device dev; 46*5161a55cSBen Widawsky struct cdev cdev; 47*5161a55cSBen Widawsky struct cxl_mem *cxlm; 48*5161a55cSBen Widawsky int id; 49*5161a55cSBen Widawsky }; 50*5161a55cSBen Widawsky 51*5161a55cSBen Widawsky /** 52*5161a55cSBen Widawsky * struct cxl_mem - A CXL memory device 53*5161a55cSBen Widawsky * @pdev: The PCI device associated with this CXL device. 54*5161a55cSBen Widawsky * @cxlmd: Logical memory device chardev / interface 55*5161a55cSBen Widawsky * @regs: Parsed register blocks 56*5161a55cSBen Widawsky * @payload_size: Size of space for payload 57*5161a55cSBen Widawsky * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register) 58*5161a55cSBen Widawsky * @lsa_size: Size of Label Storage Area 59*5161a55cSBen Widawsky * (CXL 2.0 8.2.9.5.1.1 Identify Memory Device) 60*5161a55cSBen Widawsky * @mbox_mutex: Mutex to synchronize mailbox access. 61*5161a55cSBen Widawsky * @firmware_version: Firmware version for the memory device. 62*5161a55cSBen Widawsky * @enabled_cmds: Hardware commands found enabled in CEL. 63*5161a55cSBen Widawsky * @pmem_range: Persistent memory capacity information. 64*5161a55cSBen Widawsky * @ram_range: Volatile memory capacity information. 65*5161a55cSBen Widawsky */ 66*5161a55cSBen Widawsky struct cxl_mem { 67*5161a55cSBen Widawsky struct pci_dev *pdev; 68*5161a55cSBen Widawsky struct cxl_memdev *cxlmd; 69*5161a55cSBen Widawsky 70*5161a55cSBen Widawsky struct cxl_regs regs; 71*5161a55cSBen Widawsky 72*5161a55cSBen Widawsky size_t payload_size; 73*5161a55cSBen Widawsky size_t lsa_size; 74*5161a55cSBen Widawsky struct mutex mbox_mutex; /* Protects device mailbox and firmware */ 75*5161a55cSBen Widawsky char firmware_version[0x10]; 76*5161a55cSBen Widawsky unsigned long *enabled_cmds; 77*5161a55cSBen Widawsky 78*5161a55cSBen Widawsky struct range pmem_range; 79*5161a55cSBen Widawsky struct range ram_range; 80*5161a55cSBen Widawsky }; 81*5161a55cSBen Widawsky #endif /* __CXL_MEM_H__ */ 82