15161a55cSBen Widawsky /* SPDX-License-Identifier: GPL-2.0-only */
25161a55cSBen Widawsky /* Copyright(c) 2020-2021 Intel Corporation. */
35161a55cSBen Widawsky #ifndef __CXL_MEM_H__
45161a55cSBen Widawsky #define __CXL_MEM_H__
54faf31b4SDan Williams #include <uapi/linux/cxl_mem.h>
65161a55cSBen Widawsky #include <linux/cdev.h>
76ebe28f9SIra Weiny #include <linux/uuid.h>
8ccadf131SDavidlohr Bueso #include <linux/rcuwait.h>
926a1a86dSIra Weiny #include <linux/cxl-event.h>
1086557b7eSDave Jiang #include <linux/node.h>
115161a55cSBen Widawsky #include "cxl.h"
125161a55cSBen Widawsky
135161a55cSBen Widawsky /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */
145161a55cSBen Widawsky #define CXLMDEV_STATUS_OFFSET 0x0
155161a55cSBen Widawsky #define CXLMDEV_DEV_FATAL BIT(0)
165161a55cSBen Widawsky #define CXLMDEV_FW_HALT BIT(1)
175161a55cSBen Widawsky #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2)
185161a55cSBen Widawsky #define CXLMDEV_MS_NOT_READY 0
195161a55cSBen Widawsky #define CXLMDEV_MS_READY 1
205161a55cSBen Widawsky #define CXLMDEV_MS_ERROR 2
215161a55cSBen Widawsky #define CXLMDEV_MS_DISABLED 3
225161a55cSBen Widawsky #define CXLMDEV_READY(status) \
235161a55cSBen Widawsky (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \
245161a55cSBen Widawsky CXLMDEV_MS_READY)
255161a55cSBen Widawsky #define CXLMDEV_MBOX_IF_READY BIT(4)
265161a55cSBen Widawsky #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5)
275161a55cSBen Widawsky #define CXLMDEV_RESET_NEEDED_NOT 0
285161a55cSBen Widawsky #define CXLMDEV_RESET_NEEDED_COLD 1
295161a55cSBen Widawsky #define CXLMDEV_RESET_NEEDED_WARM 2
305161a55cSBen Widawsky #define CXLMDEV_RESET_NEEDED_HOT 3
315161a55cSBen Widawsky #define CXLMDEV_RESET_NEEDED_CXL 4
325161a55cSBen Widawsky #define CXLMDEV_RESET_NEEDED(status) \
335161a55cSBen Widawsky (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \
345161a55cSBen Widawsky CXLMDEV_RESET_NEEDED_NOT)
355161a55cSBen Widawsky
365161a55cSBen Widawsky /**
375161a55cSBen Widawsky * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device
385161a55cSBen Widawsky * @dev: driver core device object
395161a55cSBen Widawsky * @cdev: char dev core object for ioctl operations
405e2411aeSIra Weiny * @cxlds: The device state backing this device
418dd2bc0fSBen Widawsky * @detach_work: active memdev lost a port in its ancestry
42f17b558dSDan Williams * @cxl_nvb: coordinate removal of @cxl_nvd if present
43f17b558dSDan Williams * @cxl_nvd: optional bridge to an nvdimm if the device supports pmem
44516b300cSDan Williams * @endpoint: connection to the CXL port topology for this memory device
455161a55cSBen Widawsky * @id: id number of this memdev instance.
462345df54SDan Williams * @depth: endpoint port depth
475161a55cSBen Widawsky */
485161a55cSBen Widawsky struct cxl_memdev {
495161a55cSBen Widawsky struct device dev;
505161a55cSBen Widawsky struct cdev cdev;
515e2411aeSIra Weiny struct cxl_dev_state *cxlds;
528dd2bc0fSBen Widawsky struct work_struct detach_work;
53f17b558dSDan Williams struct cxl_nvdimm_bridge *cxl_nvb;
54f17b558dSDan Williams struct cxl_nvdimm *cxl_nvd;
55516b300cSDan Williams struct cxl_port *endpoint;
565161a55cSBen Widawsky int id;
572345df54SDan Williams int depth;
585161a55cSBen Widawsky };
595161a55cSBen Widawsky
to_cxl_memdev(struct device * dev)603d135db5SBen Widawsky static inline struct cxl_memdev *to_cxl_memdev(struct device *dev)
613d135db5SBen Widawsky {
623d135db5SBen Widawsky return container_of(dev, struct cxl_memdev, dev);
633d135db5SBen Widawsky }
643d135db5SBen Widawsky
cxled_to_port(struct cxl_endpoint_decoder * cxled)659c57cde0SDan Williams static inline struct cxl_port *cxled_to_port(struct cxl_endpoint_decoder *cxled)
669c57cde0SDan Williams {
679c57cde0SDan Williams return to_cxl_port(cxled->cxld.dev.parent);
689c57cde0SDan Williams }
699c57cde0SDan Williams
cxlrd_to_port(struct cxl_root_decoder * cxlrd)70384e624bSDan Williams static inline struct cxl_port *cxlrd_to_port(struct cxl_root_decoder *cxlrd)
71384e624bSDan Williams {
72384e624bSDan Williams return to_cxl_port(cxlrd->cxlsd.cxld.dev.parent);
73384e624bSDan Williams }
74384e624bSDan Williams
759c57cde0SDan Williams static inline struct cxl_memdev *
cxled_to_memdev(struct cxl_endpoint_decoder * cxled)769c57cde0SDan Williams cxled_to_memdev(struct cxl_endpoint_decoder *cxled)
779c57cde0SDan Williams {
789c57cde0SDan Williams struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent);
799c57cde0SDan Williams
807481653dSDan Williams return to_cxl_memdev(port->uport_dev);
819c57cde0SDan Williams }
829c57cde0SDan Williams
832a81ada3SGreg Kroah-Hartman bool is_cxl_memdev(const struct device *dev);
is_cxl_endpoint(struct cxl_port * port)848dd2bc0fSBen Widawsky static inline bool is_cxl_endpoint(struct cxl_port *port)
858dd2bc0fSBen Widawsky {
867481653dSDan Williams return is_cxl_memdev(port->uport_dev);
878dd2bc0fSBen Widawsky }
888dd2bc0fSBen Widawsky
89f29a824bSDan Williams struct cxl_memdev *devm_cxl_add_memdev(struct device *host,
90f29a824bSDan Williams struct cxl_dev_state *cxlds);
915f2da197SDan Williams int devm_cxl_sanitize_setup_notifier(struct device *host,
925f2da197SDan Williams struct cxl_memdev *cxlmd);
93aeaefabcSDan Williams struct cxl_memdev_state;
94f29a824bSDan Williams int devm_cxl_setup_fw_upload(struct device *host, struct cxl_memdev_state *mds);
953d8f7ccaSDan Williams int devm_cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled,
963d8f7ccaSDan Williams resource_size_t base, resource_size_t len,
973d8f7ccaSDan Williams resource_size_t skipped);
983d135db5SBen Widawsky
cxl_ep_load(struct cxl_port * port,struct cxl_memdev * cxlmd)997592d935SDan Williams static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port,
1007592d935SDan Williams struct cxl_memdev *cxlmd)
1017592d935SDan Williams {
1027592d935SDan Williams if (!port)
1037592d935SDan Williams return NULL;
1047592d935SDan Williams
1057592d935SDan Williams return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev);
1067592d935SDan Williams }
1077592d935SDan Williams
1085161a55cSBen Widawsky /**
109b64955a9SDan Williams * struct cxl_mbox_cmd - A command to be submitted to hardware.
110b64955a9SDan Williams * @opcode: (input) The command set and command submitted to hardware.
111b64955a9SDan Williams * @payload_in: (input) Pointer to the input payload.
112b64955a9SDan Williams * @payload_out: (output) Pointer to the output payload. Must be allocated by
113b64955a9SDan Williams * the caller.
114b64955a9SDan Williams * @size_in: (input) Number of bytes to load from @payload_in.
115b64955a9SDan Williams * @size_out: (input) Max number of bytes loaded into @payload_out.
116b64955a9SDan Williams * (output) Number of bytes generated by the device. For fixed size
117b64955a9SDan Williams * outputs commands this is always expected to be deterministic. For
118b64955a9SDan Williams * variable sized output commands, it tells the exact number of bytes
119b64955a9SDan Williams * written.
1202aeaf663SDan Williams * @min_out: (input) internal command output payload size validation
121ccadf131SDavidlohr Bueso * @poll_count: (input) Number of timeouts to attempt.
122ccadf131SDavidlohr Bueso * @poll_interval_ms: (input) Time between mailbox background command polling
123ccadf131SDavidlohr Bueso * interval timeouts.
124b64955a9SDan Williams * @return_code: (output) Error code returned from hardware.
125b64955a9SDan Williams *
126b64955a9SDan Williams * This is the primary mechanism used to send commands to the hardware.
127b64955a9SDan Williams * All the fields except @payload_* correspond exactly to the fields described in
128b64955a9SDan Williams * Command Register section of the CXL 2.0 8.2.8.4.5. @payload_in and
129b64955a9SDan Williams * @payload_out are written to, and read from the Command Payload Registers
130b64955a9SDan Williams * defined in CXL 2.0 8.2.8.4.8.
131b64955a9SDan Williams */
132b64955a9SDan Williams struct cxl_mbox_cmd {
133b64955a9SDan Williams u16 opcode;
134b64955a9SDan Williams void *payload_in;
135b64955a9SDan Williams void *payload_out;
136b64955a9SDan Williams size_t size_in;
137b64955a9SDan Williams size_t size_out;
1382aeaf663SDan Williams size_t min_out;
139ccadf131SDavidlohr Bueso int poll_count;
140ccadf131SDavidlohr Bueso int poll_interval_ms;
141b64955a9SDan Williams u16 return_code;
142b64955a9SDan Williams };
143b64955a9SDan Williams
144b64955a9SDan Williams /*
145bfe58458SDavidlohr Bueso * Per CXL 3.0 Section 8.2.8.4.5.1
14692fcc1abSDavidlohr Bueso */
14792fcc1abSDavidlohr Bueso #define CMD_CMD_RC_TABLE \
14892fcc1abSDavidlohr Bueso C(SUCCESS, 0, NULL), \
14992fcc1abSDavidlohr Bueso C(BACKGROUND, -ENXIO, "background cmd started successfully"), \
15092fcc1abSDavidlohr Bueso C(INPUT, -ENXIO, "cmd input was invalid"), \
15192fcc1abSDavidlohr Bueso C(UNSUPPORTED, -ENXIO, "cmd is not supported"), \
15292fcc1abSDavidlohr Bueso C(INTERNAL, -ENXIO, "internal device error"), \
15392fcc1abSDavidlohr Bueso C(RETRY, -ENXIO, "temporary error, retry once"), \
15492fcc1abSDavidlohr Bueso C(BUSY, -ENXIO, "ongoing background operation"), \
15592fcc1abSDavidlohr Bueso C(MEDIADISABLED, -ENXIO, "media access is disabled"), \
15692fcc1abSDavidlohr Bueso C(FWINPROGRESS, -ENXIO, "one FW package can be transferred at a time"), \
15792fcc1abSDavidlohr Bueso C(FWOOO, -ENXIO, "FW package content was transferred out of order"), \
15892fcc1abSDavidlohr Bueso C(FWAUTH, -ENXIO, "FW package authentication failed"), \
15992fcc1abSDavidlohr Bueso C(FWSLOT, -ENXIO, "FW slot is not supported for requested operation"), \
16092fcc1abSDavidlohr Bueso C(FWROLLBACK, -ENXIO, "rolled back to the previous active FW"), \
16192fcc1abSDavidlohr Bueso C(FWRESET, -ENXIO, "FW failed to activate, needs cold reset"), \
16292fcc1abSDavidlohr Bueso C(HANDLE, -ENXIO, "one or more Event Record Handles were invalid"), \
1637ff6ad10SAlison Schofield C(PADDR, -EFAULT, "physical address specified is invalid"), \
164*591209c7SAlison Schofield C(POISONLMT, -EBUSY, "poison injection limit has been reached"), \
16592fcc1abSDavidlohr Bueso C(MEDIAFAILURE, -ENXIO, "permanent issue with the media"), \
16692fcc1abSDavidlohr Bueso C(ABORT, -ENXIO, "background cmd was aborted by device"), \
16792fcc1abSDavidlohr Bueso C(SECURITY, -ENXIO, "not valid in the current security state"), \
16892fcc1abSDavidlohr Bueso C(PASSPHRASE, -ENXIO, "phrase doesn't match current set passphrase"), \
16992fcc1abSDavidlohr Bueso C(MBUNSUPPORTED, -ENXIO, "unsupported on the mailbox it was issued on"),\
170bfe58458SDavidlohr Bueso C(PAYLOADLEN, -ENXIO, "invalid payload length"), \
171bfe58458SDavidlohr Bueso C(LOG, -ENXIO, "invalid or unsupported log page"), \
172bfe58458SDavidlohr Bueso C(INTERRUPTED, -ENXIO, "asynchronous event occured"), \
173bfe58458SDavidlohr Bueso C(FEATUREVERSION, -ENXIO, "unsupported feature version"), \
174bfe58458SDavidlohr Bueso C(FEATURESELVALUE, -ENXIO, "unsupported feature selection value"), \
175bfe58458SDavidlohr Bueso C(FEATURETRANSFERIP, -ENXIO, "feature transfer in progress"), \
176bfe58458SDavidlohr Bueso C(FEATURETRANSFEROOO, -ENXIO, "feature transfer out of order"), \
177bfe58458SDavidlohr Bueso C(RESOURCEEXHAUSTED, -ENXIO, "resources are exhausted"), \
178bfe58458SDavidlohr Bueso C(EXTLIST, -ENXIO, "invalid Extent List"), \
17992fcc1abSDavidlohr Bueso
18092fcc1abSDavidlohr Bueso #undef C
18192fcc1abSDavidlohr Bueso #define C(a, b, c) CXL_MBOX_CMD_RC_##a
18292fcc1abSDavidlohr Bueso enum { CMD_CMD_RC_TABLE };
18392fcc1abSDavidlohr Bueso #undef C
18492fcc1abSDavidlohr Bueso #define C(a, b, c) { b, c }
18592fcc1abSDavidlohr Bueso struct cxl_mbox_cmd_rc {
18692fcc1abSDavidlohr Bueso int err;
18792fcc1abSDavidlohr Bueso const char *desc;
18892fcc1abSDavidlohr Bueso };
18992fcc1abSDavidlohr Bueso
19092fcc1abSDavidlohr Bueso static const
19192fcc1abSDavidlohr Bueso struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE };
19292fcc1abSDavidlohr Bueso #undef C
19392fcc1abSDavidlohr Bueso
cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd * mbox_cmd)19492fcc1abSDavidlohr Bueso static inline const char *cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd *mbox_cmd)
19592fcc1abSDavidlohr Bueso {
19692fcc1abSDavidlohr Bueso return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc;
19792fcc1abSDavidlohr Bueso }
19892fcc1abSDavidlohr Bueso
cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd * mbox_cmd)19992fcc1abSDavidlohr Bueso static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd)
20092fcc1abSDavidlohr Bueso {
20192fcc1abSDavidlohr Bueso return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err;
20292fcc1abSDavidlohr Bueso }
20392fcc1abSDavidlohr Bueso
20492fcc1abSDavidlohr Bueso /*
205b64955a9SDan Williams * CXL 2.0 - Memory capacity multiplier
206b64955a9SDan Williams * See Section 8.2.9.5
207b64955a9SDan Williams *
208b64955a9SDan Williams * Volatile, Persistent, and Partition capacities are specified to be in
209b64955a9SDan Williams * multiples of 256MB - define a multiplier to convert to/from bytes.
210b64955a9SDan Williams */
211b64955a9SDan Williams #define CXL_CAPACITY_MULTIPLIER SZ_256M
212b64955a9SDan Williams
213c192e543SDan Williams /*
214a49aa814SDavidlohr Bueso * Event Interrupt Policy
215a49aa814SDavidlohr Bueso *
216a49aa814SDavidlohr Bueso * CXL rev 3.0 section 8.2.9.2.4; Table 8-52
217560f7855SBen Widawsky */
218a49aa814SDavidlohr Bueso enum cxl_event_int_mode {
219a49aa814SDavidlohr Bueso CXL_INT_NONE = 0x00,
220a49aa814SDavidlohr Bueso CXL_INT_MSI_MSIX = 0x01,
221a49aa814SDavidlohr Bueso CXL_INT_FW = 0x02
222a49aa814SDavidlohr Bueso };
223a49aa814SDavidlohr Bueso struct cxl_event_interrupt_policy {
224a49aa814SDavidlohr Bueso u8 info_settings;
225a49aa814SDavidlohr Bueso u8 warn_settings;
226a49aa814SDavidlohr Bueso u8 failure_settings;
227a49aa814SDavidlohr Bueso u8 fatal_settings;
228a49aa814SDavidlohr Bueso } __packed;
229a49aa814SDavidlohr Bueso
230a49aa814SDavidlohr Bueso /**
2316ebe28f9SIra Weiny * struct cxl_event_state - Event log driver state
2326ebe28f9SIra Weiny *
233c192e543SDan Williams * @buf: Buffer to receive event data
234c192e543SDan Williams * @log_lock: Serialize event_buf and log use
2356ebe28f9SIra Weiny */
2366ebe28f9SIra Weiny struct cxl_event_state {
2376ebe28f9SIra Weiny struct cxl_get_event_payload *buf;
2386ebe28f9SIra Weiny struct mutex log_lock;
239560f7855SBen Widawsky };
240560f7855SBen Widawsky
241d0abf578SAlison Schofield /* Device enabled poison commands */
242d0abf578SAlison Schofield enum poison_cmd_enabled_bits {
243d0abf578SAlison Schofield CXL_POISON_ENABLED_LIST,
244d0abf578SAlison Schofield CXL_POISON_ENABLED_INJECT,
245d0abf578SAlison Schofield CXL_POISON_ENABLED_CLEAR,
246d0abf578SAlison Schofield CXL_POISON_ENABLED_SCAN_CAPS,
247d0abf578SAlison Schofield CXL_POISON_ENABLED_SCAN_MEDIA,
248d0abf578SAlison Schofield CXL_POISON_ENABLED_SCAN_RESULTS,
249d0abf578SAlison Schofield CXL_POISON_ENABLED_MAX
250d0abf578SAlison Schofield };
251d0abf578SAlison Schofield
252ad64f595SDavidlohr Bueso /* Device enabled security commands */
253ad64f595SDavidlohr Bueso enum security_cmd_enabled_bits {
254ad64f595SDavidlohr Bueso CXL_SEC_ENABLED_SANITIZE,
255ad64f595SDavidlohr Bueso CXL_SEC_ENABLED_SECURE_ERASE,
256ad64f595SDavidlohr Bueso CXL_SEC_ENABLED_GET_SECURITY_STATE,
257ad64f595SDavidlohr Bueso CXL_SEC_ENABLED_SET_PASSPHRASE,
258ad64f595SDavidlohr Bueso CXL_SEC_ENABLED_DISABLE_PASSPHRASE,
259ad64f595SDavidlohr Bueso CXL_SEC_ENABLED_UNLOCK,
260ad64f595SDavidlohr Bueso CXL_SEC_ENABLED_FREEZE_SECURITY,
261ad64f595SDavidlohr Bueso CXL_SEC_ENABLED_PASSPHRASE_SECURE_ERASE,
262ad64f595SDavidlohr Bueso CXL_SEC_ENABLED_MAX
263ad64f595SDavidlohr Bueso };
264ad64f595SDavidlohr Bueso
265d0abf578SAlison Schofield /**
266d0abf578SAlison Schofield * struct cxl_poison_state - Driver poison state info
267d0abf578SAlison Schofield *
268d0abf578SAlison Schofield * @max_errors: Maximum media error records held in device cache
269d0abf578SAlison Schofield * @enabled_cmds: All poison commands enabled in the CEL
270d0abf578SAlison Schofield * @list_out: The poison list payload returned by device
271d0abf578SAlison Schofield * @lock: Protect reads of the poison list
272d0abf578SAlison Schofield *
273d0abf578SAlison Schofield * Reads of the poison list are synchronized to ensure that a reader
274d0abf578SAlison Schofield * does not get an incomplete list because their request overlapped
275d0abf578SAlison Schofield * (was interrupted or preceded by) another read request of the same
276d0abf578SAlison Schofield * DPA range. CXL Spec 3.0 Section 8.2.9.8.4.1
277d0abf578SAlison Schofield */
278d0abf578SAlison Schofield struct cxl_poison_state {
279d0abf578SAlison Schofield u32 max_errors;
280d0abf578SAlison Schofield DECLARE_BITMAP(enabled_cmds, CXL_POISON_ENABLED_MAX);
281d0abf578SAlison Schofield struct cxl_mbox_poison_out *list_out;
282d0abf578SAlison Schofield struct mutex lock; /* Protect reads of poison list */
283d0abf578SAlison Schofield };
284d0abf578SAlison Schofield
2859521875bSVishal Verma /*
2869521875bSVishal Verma * Get FW Info
2879521875bSVishal Verma * CXL rev 3.0 section 8.2.9.3.1; Table 8-56
2889521875bSVishal Verma */
2899521875bSVishal Verma struct cxl_mbox_get_fw_info {
2909521875bSVishal Verma u8 num_slots;
2919521875bSVishal Verma u8 slot_info;
2929521875bSVishal Verma u8 activation_cap;
2939521875bSVishal Verma u8 reserved[13];
2949521875bSVishal Verma char slot_1_revision[16];
2959521875bSVishal Verma char slot_2_revision[16];
2969521875bSVishal Verma char slot_3_revision[16];
2979521875bSVishal Verma char slot_4_revision[16];
2989521875bSVishal Verma } __packed;
2999521875bSVishal Verma
3009521875bSVishal Verma #define CXL_FW_INFO_SLOT_INFO_CUR_MASK GENMASK(2, 0)
3019521875bSVishal Verma #define CXL_FW_INFO_SLOT_INFO_NEXT_MASK GENMASK(5, 3)
3029521875bSVishal Verma #define CXL_FW_INFO_SLOT_INFO_NEXT_SHIFT 3
3039521875bSVishal Verma #define CXL_FW_INFO_ACTIVATION_CAP_HAS_LIVE_ACTIVATE BIT(0)
3049521875bSVishal Verma
3059521875bSVishal Verma /*
3069521875bSVishal Verma * Transfer FW Input Payload
3079521875bSVishal Verma * CXL rev 3.0 section 8.2.9.3.2; Table 8-57
3089521875bSVishal Verma */
3099521875bSVishal Verma struct cxl_mbox_transfer_fw {
3109521875bSVishal Verma u8 action;
3119521875bSVishal Verma u8 slot;
3129521875bSVishal Verma u8 reserved[2];
3139521875bSVishal Verma __le32 offset;
3149521875bSVishal Verma u8 reserved2[0x78];
3159521875bSVishal Verma u8 data[];
3169521875bSVishal Verma } __packed;
3179521875bSVishal Verma
3189521875bSVishal Verma #define CXL_FW_TRANSFER_ACTION_FULL 0x0
3199521875bSVishal Verma #define CXL_FW_TRANSFER_ACTION_INITIATE 0x1
3209521875bSVishal Verma #define CXL_FW_TRANSFER_ACTION_CONTINUE 0x2
3219521875bSVishal Verma #define CXL_FW_TRANSFER_ACTION_END 0x3
3229521875bSVishal Verma #define CXL_FW_TRANSFER_ACTION_ABORT 0x4
3239521875bSVishal Verma
3249521875bSVishal Verma /*
3259521875bSVishal Verma * CXL rev 3.0 section 8.2.9.3.2 mandates 128-byte alignment for FW packages
3269521875bSVishal Verma * and for each part transferred in a Transfer FW command.
3279521875bSVishal Verma */
3289521875bSVishal Verma #define CXL_FW_TRANSFER_ALIGNMENT 128
3299521875bSVishal Verma
3309521875bSVishal Verma /*
3319521875bSVishal Verma * Activate FW Input Payload
3329521875bSVishal Verma * CXL rev 3.0 section 8.2.9.3.3; Table 8-58
3339521875bSVishal Verma */
3349521875bSVishal Verma struct cxl_mbox_activate_fw {
3359521875bSVishal Verma u8 action;
3369521875bSVishal Verma u8 slot;
3379521875bSVishal Verma } __packed;
3389521875bSVishal Verma
3399521875bSVishal Verma #define CXL_FW_ACTIVATE_ONLINE 0x0
3409521875bSVishal Verma #define CXL_FW_ACTIVATE_OFFLINE 0x1
3419521875bSVishal Verma
3429521875bSVishal Verma /* FW state bits */
3439521875bSVishal Verma #define CXL_FW_STATE_BITS 32
34495c6bff7SDan Carpenter #define CXL_FW_CANCEL 0
3459521875bSVishal Verma
3469521875bSVishal Verma /**
3479521875bSVishal Verma * struct cxl_fw_state - Firmware upload / activation state
3489521875bSVishal Verma *
3499521875bSVishal Verma * @state: fw_uploader state bitmask
3509521875bSVishal Verma * @oneshot: whether the fw upload fits in a single transfer
3519521875bSVishal Verma * @num_slots: Number of FW slots available
3529521875bSVishal Verma * @cur_slot: Slot number currently active
3539521875bSVishal Verma * @next_slot: Slot number for the new firmware
3549521875bSVishal Verma */
3559521875bSVishal Verma struct cxl_fw_state {
3569521875bSVishal Verma DECLARE_BITMAP(state, CXL_FW_STATE_BITS);
3579521875bSVishal Verma bool oneshot;
3589521875bSVishal Verma int num_slots;
3599521875bSVishal Verma int cur_slot;
3609521875bSVishal Verma int next_slot;
3619521875bSVishal Verma };
3629521875bSVishal Verma
363560f7855SBen Widawsky /**
3649968c9ddSDavidlohr Bueso * struct cxl_security_state - Device security state
3659968c9ddSDavidlohr Bueso *
3669968c9ddSDavidlohr Bueso * @state: state of last security operation
367ad64f595SDavidlohr Bueso * @enabled_cmds: All security commands enabled in the CEL
3680c36b6adSDavidlohr Bueso * @poll_tmo_secs: polling timeout
36933981838SDan Williams * @sanitize_active: sanitize completion pending
3700c36b6adSDavidlohr Bueso * @poll_dwork: polling work item
37148dcdbb1SDavidlohr Bueso * @sanitize_node: sanitation sysfs file to notify
3729968c9ddSDavidlohr Bueso */
3739968c9ddSDavidlohr Bueso struct cxl_security_state {
3749968c9ddSDavidlohr Bueso unsigned long state;
375ad64f595SDavidlohr Bueso DECLARE_BITMAP(enabled_cmds, CXL_SEC_ENABLED_MAX);
3760c36b6adSDavidlohr Bueso int poll_tmo_secs;
37733981838SDan Williams bool sanitize_active;
3780c36b6adSDavidlohr Bueso struct delayed_work poll_dwork;
37948dcdbb1SDavidlohr Bueso struct kernfs_node *sanitize_node;
3809968c9ddSDavidlohr Bueso };
3819968c9ddSDavidlohr Bueso
382aeaefabcSDan Williams /*
383f6b8ab32SDan Williams * enum cxl_devtype - delineate type-2 from a generic type-3 device
384f6b8ab32SDan Williams * @CXL_DEVTYPE_DEVMEM - Vendor specific CXL Type-2 device implementing HDM-D or
385f6b8ab32SDan Williams * HDM-DB, no requirement that this device implements a
386f6b8ab32SDan Williams * mailbox, or other memory-device-standard manageability
387f6b8ab32SDan Williams * flows.
388f6b8ab32SDan Williams * @CXL_DEVTYPE_CLASSMEM - Common class definition of a CXL Type-3 device with
389f6b8ab32SDan Williams * HDM-H and class-mandatory memory device registers
390f6b8ab32SDan Williams */
391f6b8ab32SDan Williams enum cxl_devtype {
392f6b8ab32SDan Williams CXL_DEVTYPE_DEVMEM,
393f6b8ab32SDan Williams CXL_DEVTYPE_CLASSMEM,
394f6b8ab32SDan Williams };
395f6b8ab32SDan Williams
3969968c9ddSDavidlohr Bueso /**
39786557b7eSDave Jiang * struct cxl_dpa_perf - DPA performance property entry
398a0f39d51SYao Xingtao * @dpa_range: range for DPA address
399a0f39d51SYao Xingtao * @coord: QoS performance data (i.e. latency, bandwidth)
400a0f39d51SYao Xingtao * @qos_class: QoS Class cookies
40186557b7eSDave Jiang */
40286557b7eSDave Jiang struct cxl_dpa_perf {
40386557b7eSDave Jiang struct range dpa_range;
404001c5d19SDave Jiang struct access_coordinate coord[ACCESS_COORDINATE_MAX];
40586557b7eSDave Jiang int qos_class;
40686557b7eSDave Jiang };
40786557b7eSDave Jiang
40886557b7eSDave Jiang /**
4095e2411aeSIra Weiny * struct cxl_dev_state - The driver device state
4105e2411aeSIra Weiny *
4115e2411aeSIra Weiny * cxl_dev_state represents the CXL driver/device state. It provides an
4125e2411aeSIra Weiny * interface to mailbox commands as well as some cached data about the device.
4135e2411aeSIra Weiny * Currently only memory devices are represented.
4145e2411aeSIra Weiny *
4155e2411aeSIra Weiny * @dev: The device associated with this CXL state
4162905cb52SDan Williams * @cxlmd: The device representing the CXL.mem capabilities of @dev
4172dd18279SRobert Richter * @reg_map: component and ras register mapping parameters
4185161a55cSBen Widawsky * @regs: Parsed register blocks
41906e279e5SBen Widawsky * @cxl_dvsec: Offset to the PCIe device DVSEC
4200a19bfc8SDan Williams * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH)
421e764f122SDave Jiang * @media_ready: Indicate whether the device media is usable
42259f8d151SDan Williams * @dpa_res: Overall DPA resource tree for the device
42359f8d151SDan Williams * @pmem_res: Active Persistent memory capacity configuration
42459f8d151SDan Williams * @ram_res: Active Volatile memory capacity configuration
42559f8d151SDan Williams * @serial: PCIe Device Serial Number
426f6b8ab32SDan Williams * @type: Generic Memory Class device or Vendor Specific Memory device
42759f8d151SDan Williams */
42859f8d151SDan Williams struct cxl_dev_state {
42959f8d151SDan Williams struct device *dev;
43059f8d151SDan Williams struct cxl_memdev *cxlmd;
4312dd18279SRobert Richter struct cxl_register_map reg_map;
43259f8d151SDan Williams struct cxl_regs regs;
43359f8d151SDan Williams int cxl_dvsec;
43459f8d151SDan Williams bool rcd;
43559f8d151SDan Williams bool media_ready;
43659f8d151SDan Williams struct resource dpa_res;
43759f8d151SDan Williams struct resource pmem_res;
43859f8d151SDan Williams struct resource ram_res;
43959f8d151SDan Williams u64 serial;
440f6b8ab32SDan Williams enum cxl_devtype type;
44159f8d151SDan Williams };
44259f8d151SDan Williams
44359f8d151SDan Williams /**
44459f8d151SDan Williams * struct cxl_memdev_state - Generic Type-3 Memory Device Class driver data
44559f8d151SDan Williams *
44659f8d151SDan Williams * CXL 8.1.12.1 PCI Header - Class Code Register Memory Device defines
44759f8d151SDan Williams * common memory device functionality like the presence of a mailbox and
44859f8d151SDan Williams * the functionality related to that like Identify Memory Device and Get
44959f8d151SDan Williams * Partition Info
45059f8d151SDan Williams * @cxlds: Core driver state common across Type-2 and Type-3 devices
4515161a55cSBen Widawsky * @payload_size: Size of space for payload
4525161a55cSBen Widawsky * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register)
4535161a55cSBen Widawsky * @lsa_size: Size of Label Storage Area
4545161a55cSBen Widawsky * (CXL 2.0 8.2.9.5.1.1 Identify Memory Device)
4555161a55cSBen Widawsky * @mbox_mutex: Mutex to synchronize mailbox access.
4565161a55cSBen Widawsky * @firmware_version: Firmware version for the memory device.
4575161a55cSBen Widawsky * @enabled_cmds: Hardware commands found enabled in CEL.
45812f3856aSDan Williams * @exclusive_cmds: Commands that are kernel-internal only
45913e7749dSDan Williams * @total_bytes: sum of all possible capacities
46013e7749dSDan Williams * @volatile_only_bytes: hard volatile capacity
46113e7749dSDan Williams * @persistent_only_bytes: hard persistent capacity
46213e7749dSDan Williams * @partition_align_bytes: alignment size for partition-able capacity
46313e7749dSDan Williams * @active_volatile_bytes: sum of hard + soft volatile
46413e7749dSDan Williams * @active_persistent_bytes: sum of hard + soft persistent
46513e7749dSDan Williams * @next_volatile_bytes: volatile capacity change pending device reset
46613e7749dSDan Williams * @next_persistent_bytes: persistent capacity change pending device reset
467a0f39d51SYao Xingtao * @ram_perf: performance data entry matched to RAM partition
468a0f39d51SYao Xingtao * @pmem_perf: performance data entry matched to PMEM partition
4691bb31131SAlison Schofield * @event: event log driver state
470d0abf578SAlison Schofield * @poison: poison driver state info
4713de8cd22SDavidlohr Bueso * @security: security driver state info
4729521875bSVishal Verma * @fw: firmware upload / activation state
473a0f39d51SYao Xingtao * @mbox_wait: RCU wait for mbox send completely
474b64955a9SDan Williams * @mbox_send: @dev specific transport for transmitting mailbox commands
47513e7749dSDan Williams *
47659f8d151SDan Williams * See CXL 3.0 8.2.9.8.2 Capacity Configuration and Label Storage for
47713e7749dSDan Williams * details on capacity parameters.
4785161a55cSBen Widawsky */
47959f8d151SDan Williams struct cxl_memdev_state {
48059f8d151SDan Williams struct cxl_dev_state cxlds;
4815161a55cSBen Widawsky size_t payload_size;
4825161a55cSBen Widawsky size_t lsa_size;
4835161a55cSBen Widawsky struct mutex mbox_mutex; /* Protects device mailbox and firmware */
4845161a55cSBen Widawsky char firmware_version[0x10];
485ff56ab9eSDan Williams DECLARE_BITMAP(enabled_cmds, CXL_MEM_COMMAND_ID_MAX);
48612f3856aSDan Williams DECLARE_BITMAP(exclusive_cmds, CXL_MEM_COMMAND_ID_MAX);
4870b9159d0SIra Weiny u64 total_bytes;
4880b9159d0SIra Weiny u64 volatile_only_bytes;
4890b9159d0SIra Weiny u64 persistent_only_bytes;
4900b9159d0SIra Weiny u64 partition_align_bytes;
491f847502aSIra Weiny u64 active_volatile_bytes;
492f847502aSIra Weiny u64 active_persistent_bytes;
493f847502aSIra Weiny u64 next_volatile_bytes;
494f847502aSIra Weiny u64 next_persistent_bytes;
49586557b7eSDave Jiang
49600413c15SDave Jiang struct cxl_dpa_perf ram_perf;
49700413c15SDave Jiang struct cxl_dpa_perf pmem_perf;
49886557b7eSDave Jiang
4996ebe28f9SIra Weiny struct cxl_event_state event;
500d0abf578SAlison Schofield struct cxl_poison_state poison;
5019968c9ddSDavidlohr Bueso struct cxl_security_state security;
5029521875bSVishal Verma struct cxl_fw_state fw;
5036ebe28f9SIra Weiny
504ccadf131SDavidlohr Bueso struct rcuwait mbox_wait;
50559f8d151SDan Williams int (*mbox_send)(struct cxl_memdev_state *mds,
50659f8d151SDan Williams struct cxl_mbox_cmd *cmd);
5075161a55cSBen Widawsky };
5084faf31b4SDan Williams
50959f8d151SDan Williams static inline struct cxl_memdev_state *
to_cxl_memdev_state(struct cxl_dev_state * cxlds)51059f8d151SDan Williams to_cxl_memdev_state(struct cxl_dev_state *cxlds)
51159f8d151SDan Williams {
512f6b8ab32SDan Williams if (cxlds->type != CXL_DEVTYPE_CLASSMEM)
513f6b8ab32SDan Williams return NULL;
51459f8d151SDan Williams return container_of(cxlds, struct cxl_memdev_state, cxlds);
51559f8d151SDan Williams }
51659f8d151SDan Williams
5174faf31b4SDan Williams enum cxl_opcode {
5184faf31b4SDan Williams CXL_MBOX_OP_INVALID = 0x0000,
5194faf31b4SDan Williams CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID,
5206ebe28f9SIra Weiny CXL_MBOX_OP_GET_EVENT_RECORD = 0x0100,
5216ebe28f9SIra Weiny CXL_MBOX_OP_CLEAR_EVENT_RECORD = 0x0101,
522a49aa814SDavidlohr Bueso CXL_MBOX_OP_GET_EVT_INT_POLICY = 0x0102,
523a49aa814SDavidlohr Bueso CXL_MBOX_OP_SET_EVT_INT_POLICY = 0x0103,
5244faf31b4SDan Williams CXL_MBOX_OP_GET_FW_INFO = 0x0200,
5259521875bSVishal Verma CXL_MBOX_OP_TRANSFER_FW = 0x0201,
5264faf31b4SDan Williams CXL_MBOX_OP_ACTIVATE_FW = 0x0202,
527cb46fca8SDavidlohr Bueso CXL_MBOX_OP_GET_TIMESTAMP = 0x0300,
528fa884345SJonathan Cameron CXL_MBOX_OP_SET_TIMESTAMP = 0x0301,
5294faf31b4SDan Williams CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400,
5304faf31b4SDan Williams CXL_MBOX_OP_GET_LOG = 0x0401,
531940325adSSrinivasulu Thanneeru CXL_MBOX_OP_GET_LOG_CAPS = 0x0402,
532206f9fa9SSrinivasulu Thanneeru CXL_MBOX_OP_CLEAR_LOG = 0x0403,
533940325adSSrinivasulu Thanneeru CXL_MBOX_OP_GET_SUP_LOG_SUBLIST = 0x0405,
5344faf31b4SDan Williams CXL_MBOX_OP_IDENTIFY = 0x4000,
5354faf31b4SDan Williams CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100,
5364faf31b4SDan Williams CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101,
5374faf31b4SDan Williams CXL_MBOX_OP_GET_LSA = 0x4102,
5384faf31b4SDan Williams CXL_MBOX_OP_SET_LSA = 0x4103,
5394faf31b4SDan Williams CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200,
5404faf31b4SDan Williams CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201,
5414faf31b4SDan Williams CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202,
5424faf31b4SDan Williams CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203,
5434faf31b4SDan Williams CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204,
5444faf31b4SDan Williams CXL_MBOX_OP_GET_POISON = 0x4300,
5454faf31b4SDan Williams CXL_MBOX_OP_INJECT_POISON = 0x4301,
5464faf31b4SDan Williams CXL_MBOX_OP_CLEAR_POISON = 0x4302,
5474faf31b4SDan Williams CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303,
5484faf31b4SDan Williams CXL_MBOX_OP_SCAN_MEDIA = 0x4304,
5494faf31b4SDan Williams CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305,
5500c36b6adSDavidlohr Bueso CXL_MBOX_OP_SANITIZE = 0x4400,
551180ffd33SDavidlohr Bueso CXL_MBOX_OP_SECURE_ERASE = 0x4401,
55232828115SDave Jiang CXL_MBOX_OP_GET_SECURITY_STATE = 0x4500,
55399746940SDave Jiang CXL_MBOX_OP_SET_PASSPHRASE = 0x4501,
554c4ef680dSDave Jiang CXL_MBOX_OP_DISABLE_PASSPHRASE = 0x4502,
5552bb692f7SDave Jiang CXL_MBOX_OP_UNLOCK = 0x4503,
556a072f7b7SDave Jiang CXL_MBOX_OP_FREEZE_SECURITY = 0x4504,
5573b502e88SDave Jiang CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE = 0x4505,
5584faf31b4SDan Williams CXL_MBOX_OP_MAX = 0x10000
5594faf31b4SDan Williams };
5604faf31b4SDan Williams
56149be6dd8SDan Williams #define DEFINE_CXL_CEL_UUID \
56249be6dd8SDan Williams UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62, \
56349be6dd8SDan Williams 0x3b, 0x3f, 0x17)
56449be6dd8SDan Williams
56549be6dd8SDan Williams #define DEFINE_CXL_VENDOR_DEBUG_UUID \
5668ecef8e0Speng guo UUID_INIT(0x5e1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \
56749be6dd8SDan Williams 0x40, 0x3d, 0x86)
56849be6dd8SDan Williams
56949be6dd8SDan Williams struct cxl_mbox_get_supported_logs {
57049be6dd8SDan Williams __le16 entries;
57149be6dd8SDan Williams u8 rsvd[6];
57249be6dd8SDan Williams struct cxl_gsl_entry {
57349be6dd8SDan Williams uuid_t uuid;
57449be6dd8SDan Williams __le32 size;
57549be6dd8SDan Williams } __packed entry[];
57649be6dd8SDan Williams } __packed;
57749be6dd8SDan Williams
57849be6dd8SDan Williams struct cxl_cel_entry {
57949be6dd8SDan Williams __le16 opcode;
58049be6dd8SDan Williams __le16 effect;
58149be6dd8SDan Williams } __packed;
58249be6dd8SDan Williams
58349be6dd8SDan Williams struct cxl_mbox_get_log {
58449be6dd8SDan Williams uuid_t uuid;
58549be6dd8SDan Williams __le32 offset;
58649be6dd8SDan Williams __le32 length;
58749be6dd8SDan Williams } __packed;
58849be6dd8SDan Williams
58949be6dd8SDan Williams /* See CXL 2.0 Table 175 Identify Memory Device Output Payload */
59049be6dd8SDan Williams struct cxl_mbox_identify {
59149be6dd8SDan Williams char fw_revision[0x10];
59249be6dd8SDan Williams __le64 total_capacity;
59349be6dd8SDan Williams __le64 volatile_capacity;
59449be6dd8SDan Williams __le64 persistent_capacity;
59549be6dd8SDan Williams __le64 partition_align;
59649be6dd8SDan Williams __le16 info_event_log_size;
59749be6dd8SDan Williams __le16 warning_event_log_size;
59849be6dd8SDan Williams __le16 failure_event_log_size;
59949be6dd8SDan Williams __le16 fatal_event_log_size;
60049be6dd8SDan Williams __le32 lsa_size;
60149be6dd8SDan Williams u8 poison_list_max_mer[3];
60249be6dd8SDan Williams __le16 inject_poison_limit;
60349be6dd8SDan Williams u8 poison_caps;
60449be6dd8SDan Williams u8 qos_telemetry_caps;
60549be6dd8SDan Williams } __packed;
60649be6dd8SDan Williams
6076ebe28f9SIra Weiny /*
6084c115c9cSIra Weiny * General Media Event Record UUID
6094c115c9cSIra Weiny * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43
6106ebe28f9SIra Weiny */
6114c115c9cSIra Weiny #define CXL_EVENT_GEN_MEDIA_UUID \
6124c115c9cSIra Weiny UUID_INIT(0xfbcd0a77, 0xc260, 0x417f, 0x85, 0xa9, 0x08, 0x8b, 0x16, \
6134c115c9cSIra Weiny 0x21, 0xeb, 0xa6)
6146ebe28f9SIra Weiny
6154c115c9cSIra Weiny /*
6164c115c9cSIra Weiny * DRAM Event Record UUID
6174c115c9cSIra Weiny * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44
6184c115c9cSIra Weiny */
6194c115c9cSIra Weiny #define CXL_EVENT_DRAM_UUID \
6204c115c9cSIra Weiny UUID_INIT(0x601dcbb3, 0x9c06, 0x4eab, 0xb8, 0xaf, 0x4e, 0x9b, 0xfb, \
6214c115c9cSIra Weiny 0x5c, 0x96, 0x24)
6224c115c9cSIra Weiny
6234c115c9cSIra Weiny /*
6244c115c9cSIra Weiny * Memory Module Event Record UUID
6254c115c9cSIra Weiny * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45
6264c115c9cSIra Weiny */
6274c115c9cSIra Weiny #define CXL_EVENT_MEM_MODULE_UUID \
6284c115c9cSIra Weiny UUID_INIT(0xfe927475, 0xdd59, 0x4339, 0xa5, 0x86, 0x79, 0xba, 0xb1, \
6294c115c9cSIra Weiny 0x13, 0xb7, 0x74)
6306ebe28f9SIra Weiny
6316ebe28f9SIra Weiny /*
6326ebe28f9SIra Weiny * Get Event Records output payload
6336ebe28f9SIra Weiny * CXL rev 3.0 section 8.2.9.2.2; Table 8-50
6346ebe28f9SIra Weiny */
6356ebe28f9SIra Weiny #define CXL_GET_EVENT_FLAG_OVERFLOW BIT(0)
6366ebe28f9SIra Weiny #define CXL_GET_EVENT_FLAG_MORE_RECORDS BIT(1)
6376ebe28f9SIra Weiny struct cxl_get_event_payload {
6386ebe28f9SIra Weiny u8 flags;
6396ebe28f9SIra Weiny u8 reserved1;
6406ebe28f9SIra Weiny __le16 overflow_err_count;
6416ebe28f9SIra Weiny __le64 first_overflow_timestamp;
6426ebe28f9SIra Weiny __le64 last_overflow_timestamp;
6436ebe28f9SIra Weiny __le16 record_count;
6446ebe28f9SIra Weiny u8 reserved2[10];
6456ebe28f9SIra Weiny struct cxl_event_record_raw records[];
6466ebe28f9SIra Weiny } __packed;
6476ebe28f9SIra Weiny
6486ebe28f9SIra Weiny /*
6496ebe28f9SIra Weiny * CXL rev 3.0 section 8.2.9.2.2; Table 8-49
6506ebe28f9SIra Weiny */
6516ebe28f9SIra Weiny enum cxl_event_log_type {
6526ebe28f9SIra Weiny CXL_EVENT_TYPE_INFO = 0x00,
6536ebe28f9SIra Weiny CXL_EVENT_TYPE_WARN,
6546ebe28f9SIra Weiny CXL_EVENT_TYPE_FAIL,
6556ebe28f9SIra Weiny CXL_EVENT_TYPE_FATAL,
6566ebe28f9SIra Weiny CXL_EVENT_TYPE_MAX
6576ebe28f9SIra Weiny };
6586ebe28f9SIra Weiny
6596ebe28f9SIra Weiny /*
6606ebe28f9SIra Weiny * Clear Event Records input payload
6616ebe28f9SIra Weiny * CXL rev 3.0 section 8.2.9.2.3; Table 8-51
6626ebe28f9SIra Weiny */
6636ebe28f9SIra Weiny struct cxl_mbox_clear_event_payload {
6646ebe28f9SIra Weiny u8 event_log; /* enum cxl_event_log_type */
6656ebe28f9SIra Weiny u8 clear_flags;
6666ebe28f9SIra Weiny u8 nr_recs;
6676ebe28f9SIra Weiny u8 reserved[3];
6686ebe28f9SIra Weiny __le16 handles[];
6696ebe28f9SIra Weiny } __packed;
6706ebe28f9SIra Weiny #define CXL_CLEAR_EVENT_MAX_HANDLES U8_MAX
6716ebe28f9SIra Weiny
672e7ad1bf6SDan Williams struct cxl_mbox_get_partition_info {
673e7ad1bf6SDan Williams __le64 active_volatile_cap;
674e7ad1bf6SDan Williams __le64 active_persistent_cap;
675e7ad1bf6SDan Williams __le64 next_volatile_cap;
676e7ad1bf6SDan Williams __le64 next_persistent_cap;
677e7ad1bf6SDan Williams } __packed;
678e7ad1bf6SDan Williams
67949be6dd8SDan Williams struct cxl_mbox_get_lsa {
6808a664875SAlison Schofield __le32 offset;
6818a664875SAlison Schofield __le32 length;
68249be6dd8SDan Williams } __packed;
68349be6dd8SDan Williams
68449be6dd8SDan Williams struct cxl_mbox_set_lsa {
6858a664875SAlison Schofield __le32 offset;
6868a664875SAlison Schofield __le32 reserved;
68749be6dd8SDan Williams u8 data[];
68849be6dd8SDan Williams } __packed;
68949be6dd8SDan Williams
6906179045cSAlison Schofield struct cxl_mbox_set_partition_info {
6916179045cSAlison Schofield __le64 volatile_capacity;
6926179045cSAlison Schofield u8 flags;
6936179045cSAlison Schofield } __packed;
6946179045cSAlison Schofield
6956179045cSAlison Schofield #define CXL_SET_PARTITION_IMMEDIATE_FLAG BIT(0)
6966179045cSAlison Schofield
697fa884345SJonathan Cameron /* Set Timestamp CXL 3.0 Spec 8.2.9.4.2 */
698fa884345SJonathan Cameron struct cxl_mbox_set_timestamp_in {
699fa884345SJonathan Cameron __le64 timestamp;
700fa884345SJonathan Cameron
701fa884345SJonathan Cameron } __packed;
702fa884345SJonathan Cameron
703ed83f7caSAlison Schofield /* Get Poison List CXL 3.0 Spec 8.2.9.8.4.1 */
704ed83f7caSAlison Schofield struct cxl_mbox_poison_in {
705ed83f7caSAlison Schofield __le64 offset;
706ed83f7caSAlison Schofield __le64 length;
707ed83f7caSAlison Schofield } __packed;
708ed83f7caSAlison Schofield
709ed83f7caSAlison Schofield struct cxl_mbox_poison_out {
710ed83f7caSAlison Schofield u8 flags;
711ed83f7caSAlison Schofield u8 rsvd1;
712ed83f7caSAlison Schofield __le64 overflow_ts;
713ed83f7caSAlison Schofield __le16 count;
714ed83f7caSAlison Schofield u8 rsvd2[20];
715ed83f7caSAlison Schofield struct cxl_poison_record {
716ed83f7caSAlison Schofield __le64 address;
717ed83f7caSAlison Schofield __le32 length;
718ed83f7caSAlison Schofield __le32 rsvd;
719ed83f7caSAlison Schofield } __packed record[];
720ed83f7caSAlison Schofield } __packed;
721ed83f7caSAlison Schofield
722ed83f7caSAlison Schofield /*
723ed83f7caSAlison Schofield * Get Poison List address field encodes the starting
724ed83f7caSAlison Schofield * address of poison, and the source of the poison.
725ed83f7caSAlison Schofield */
726ed83f7caSAlison Schofield #define CXL_POISON_START_MASK GENMASK_ULL(63, 6)
727ed83f7caSAlison Schofield #define CXL_POISON_SOURCE_MASK GENMASK(2, 0)
728ed83f7caSAlison Schofield
729ed83f7caSAlison Schofield /* Get Poison List record length is in units of 64 bytes */
730ed83f7caSAlison Schofield #define CXL_POISON_LEN_MULT 64
731ed83f7caSAlison Schofield
732ed83f7caSAlison Schofield /* Kernel defined maximum for a list of poison errors */
733ed83f7caSAlison Schofield #define CXL_POISON_LIST_MAX 1024
734ed83f7caSAlison Schofield
735ed83f7caSAlison Schofield /* Get Poison List: Payload out flags */
736ed83f7caSAlison Schofield #define CXL_POISON_FLAG_MORE BIT(0)
737ed83f7caSAlison Schofield #define CXL_POISON_FLAG_OVERFLOW BIT(1)
738ed83f7caSAlison Schofield #define CXL_POISON_FLAG_SCANNING BIT(2)
739ed83f7caSAlison Schofield
740ed83f7caSAlison Schofield /* Get Poison List: Poison Source */
741ed83f7caSAlison Schofield #define CXL_POISON_SOURCE_UNKNOWN 0
742ed83f7caSAlison Schofield #define CXL_POISON_SOURCE_EXTERNAL 1
743ed83f7caSAlison Schofield #define CXL_POISON_SOURCE_INTERNAL 2
744ed83f7caSAlison Schofield #define CXL_POISON_SOURCE_INJECTED 3
745ed83f7caSAlison Schofield #define CXL_POISON_SOURCE_VENDOR 7
746ed83f7caSAlison Schofield
747d2fbc486SAlison Schofield /* Inject & Clear Poison CXL 3.0 Spec 8.2.9.8.4.2/3 */
748d2fbc486SAlison Schofield struct cxl_mbox_inject_poison {
749d2fbc486SAlison Schofield __le64 address;
750d2fbc486SAlison Schofield };
751d2fbc486SAlison Schofield
7529690b077SAlison Schofield /* Clear Poison CXL 3.0 Spec 8.2.9.8.4.3 */
7539690b077SAlison Schofield struct cxl_mbox_clear_poison {
7549690b077SAlison Schofield __le64 address;
7559690b077SAlison Schofield u8 write_data[CXL_POISON_LEN_MULT];
7569690b077SAlison Schofield } __packed;
7579690b077SAlison Schofield
7584faf31b4SDan Williams /**
7594faf31b4SDan Williams * struct cxl_mem_command - Driver representation of a memory device command
7604faf31b4SDan Williams * @info: Command information as it exists for the UAPI
7614faf31b4SDan Williams * @opcode: The actual bits used for the mailbox protocol
7624faf31b4SDan Williams * @flags: Set of flags effecting driver behavior.
7634faf31b4SDan Williams *
7644faf31b4SDan Williams * * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag
7654faf31b4SDan Williams * will be enabled by the driver regardless of what hardware may have
7664faf31b4SDan Williams * advertised.
7674faf31b4SDan Williams *
7684faf31b4SDan Williams * The cxl_mem_command is the driver's internal representation of commands that
7694faf31b4SDan Williams * are supported by the driver. Some of these commands may not be supported by
7704faf31b4SDan Williams * the hardware. The driver will use @info to validate the fields passed in by
7714faf31b4SDan Williams * the user then submit the @opcode to the hardware.
7724faf31b4SDan Williams *
7734faf31b4SDan Williams * See struct cxl_command_info.
7744faf31b4SDan Williams */
7754faf31b4SDan Williams struct cxl_mem_command {
7764faf31b4SDan Williams struct cxl_command_info info;
7774faf31b4SDan Williams enum cxl_opcode opcode;
7784faf31b4SDan Williams u32 flags;
7794faf31b4SDan Williams #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0)
7804faf31b4SDan Williams };
7814faf31b4SDan Williams
78232828115SDave Jiang #define CXL_PMEM_SEC_STATE_USER_PASS_SET 0x01
78332828115SDave Jiang #define CXL_PMEM_SEC_STATE_MASTER_PASS_SET 0x02
78432828115SDave Jiang #define CXL_PMEM_SEC_STATE_LOCKED 0x04
78532828115SDave Jiang #define CXL_PMEM_SEC_STATE_FROZEN 0x08
78632828115SDave Jiang #define CXL_PMEM_SEC_STATE_USER_PLIMIT 0x10
78732828115SDave Jiang #define CXL_PMEM_SEC_STATE_MASTER_PLIMIT 0x20
78832828115SDave Jiang
78999746940SDave Jiang /* set passphrase input payload */
79099746940SDave Jiang struct cxl_set_pass {
79199746940SDave Jiang u8 type;
79299746940SDave Jiang u8 reserved[31];
79399746940SDave Jiang /* CXL field using NVDIMM define, same length */
79499746940SDave Jiang u8 old_pass[NVDIMM_PASSPHRASE_LEN];
79599746940SDave Jiang u8 new_pass[NVDIMM_PASSPHRASE_LEN];
79699746940SDave Jiang } __packed;
79799746940SDave Jiang
798c4ef680dSDave Jiang /* disable passphrase input payload */
799c4ef680dSDave Jiang struct cxl_disable_pass {
800c4ef680dSDave Jiang u8 type;
801c4ef680dSDave Jiang u8 reserved[31];
802c4ef680dSDave Jiang u8 pass[NVDIMM_PASSPHRASE_LEN];
803c4ef680dSDave Jiang } __packed;
804c4ef680dSDave Jiang
8053b502e88SDave Jiang /* passphrase secure erase payload */
8063b502e88SDave Jiang struct cxl_pass_erase {
8073b502e88SDave Jiang u8 type;
8083b502e88SDave Jiang u8 reserved[31];
8093b502e88SDave Jiang u8 pass[NVDIMM_PASSPHRASE_LEN];
8103b502e88SDave Jiang } __packed;
8113b502e88SDave Jiang
81299746940SDave Jiang enum {
81399746940SDave Jiang CXL_PMEM_SEC_PASS_MASTER = 0,
81499746940SDave Jiang CXL_PMEM_SEC_PASS_USER,
81599746940SDave Jiang };
81699746940SDave Jiang
81759f8d151SDan Williams int cxl_internal_send_cmd(struct cxl_memdev_state *mds,
8185331cdf4SDan Williams struct cxl_mbox_cmd *cmd);
81959f8d151SDan Williams int cxl_dev_state_identify(struct cxl_memdev_state *mds);
8202e4ba0ecSDan Williams int cxl_await_media_ready(struct cxl_dev_state *cxlds);
82159f8d151SDan Williams int cxl_enumerate_cmds(struct cxl_memdev_state *mds);
82259f8d151SDan Williams int cxl_mem_create_range_info(struct cxl_memdev_state *mds);
82359f8d151SDan Williams struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev);
82459f8d151SDan Williams void set_exclusive_cxl_commands(struct cxl_memdev_state *mds,
82559f8d151SDan Williams unsigned long *cmds);
82659f8d151SDan Williams void clear_exclusive_cxl_commands(struct cxl_memdev_state *mds,
82759f8d151SDan Williams unsigned long *cmds);
82859f8d151SDan Williams void cxl_mem_get_event_records(struct cxl_memdev_state *mds, u32 status);
829dc97f634SIra Weiny void cxl_event_trace_record(const struct cxl_memdev *cxlmd,
830dc97f634SIra Weiny enum cxl_event_log_type type,
831dc97f634SIra Weiny enum cxl_event_type event_type,
832dc97f634SIra Weiny const uuid_t *uuid, union cxl_event *evt);
83359f8d151SDan Williams int cxl_set_timestamp(struct cxl_memdev_state *mds);
83459f8d151SDan Williams int cxl_poison_state_init(struct cxl_memdev_state *mds);
835ed83f7caSAlison Schofield int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len,
836ed83f7caSAlison Schofield struct cxl_region *cxlr);
8377ff6ad10SAlison Schofield int cxl_trigger_poison_list(struct cxl_memdev *cxlmd);
838d2fbc486SAlison Schofield int cxl_inject_poison(struct cxl_memdev *cxlmd, u64 dpa);
8399690b077SAlison Schofield int cxl_clear_poison(struct cxl_memdev *cxlmd, u64 dpa);
840fa884345SJonathan Cameron
8419ea4dcf4SDan Williams #ifdef CONFIG_CXL_SUSPEND
8429ea4dcf4SDan Williams void cxl_mem_active_inc(void);
8439ea4dcf4SDan Williams void cxl_mem_active_dec(void);
8449ea4dcf4SDan Williams #else
cxl_mem_active_inc(void)8459ea4dcf4SDan Williams static inline void cxl_mem_active_inc(void)
8469ea4dcf4SDan Williams {
8479ea4dcf4SDan Williams }
cxl_mem_active_dec(void)8489ea4dcf4SDan Williams static inline void cxl_mem_active_dec(void)
8499ea4dcf4SDan Williams {
8509ea4dcf4SDan Williams }
8519ea4dcf4SDan Williams #endif
852d17d0540SDan Williams
85333981838SDan Williams int cxl_mem_sanitize(struct cxl_memdev *cxlmd, u16 cmd);
85448dcdbb1SDavidlohr Bueso
85584328c5aSYao Xingtao /**
85684328c5aSYao Xingtao * struct cxl_hdm - HDM Decoder registers and cached / decoded capabilities
85784328c5aSYao Xingtao * @regs: mapped registers, see devm_cxl_setup_hdm()
85884328c5aSYao Xingtao * @decoder_count: number of decoders for this port
85984328c5aSYao Xingtao * @target_count: for switch decoders, max downstream port targets
86084328c5aSYao Xingtao * @interleave_mask: interleave granularity capability, see check_interleave_cap()
86184328c5aSYao Xingtao * @iw_cap_mask: bitmask of supported interleave ways, see check_interleave_cap()
86284328c5aSYao Xingtao * @port: mapped cxl_port, see devm_cxl_setup_hdm()
86384328c5aSYao Xingtao */
864d17d0540SDan Williams struct cxl_hdm {
865d17d0540SDan Williams struct cxl_component_regs regs;
866d17d0540SDan Williams unsigned int decoder_count;
867d17d0540SDan Williams unsigned int target_count;
868d17d0540SDan Williams unsigned int interleave_mask;
86984328c5aSYao Xingtao unsigned long iw_cap_mask;
870d17d0540SDan Williams struct cxl_port *port;
871d17d0540SDan Williams };
872cc2a4878SDan Williams
873cc2a4878SDan Williams struct seq_file;
874cc2a4878SDan Williams struct dentry *cxl_debugfs_create_dir(const char *dir);
875cc2a4878SDan Williams void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds);
8765161a55cSBen Widawsky #endif /* __CXL_MEM_H__ */
877