1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020 Intel Corporation. */ 3 4 #ifndef __CXL_H__ 5 #define __CXL_H__ 6 7 #include <linux/libnvdimm.h> 8 #include <linux/bitfield.h> 9 #include <linux/bitops.h> 10 #include <linux/log2.h> 11 #include <linux/io.h> 12 13 /** 14 * DOC: cxl objects 15 * 16 * The CXL core objects like ports, decoders, and regions are shared 17 * between the subsystem drivers cxl_acpi, cxl_pci, and core drivers 18 * (port-driver, region-driver, nvdimm object-drivers... etc). 19 */ 20 21 /* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */ 22 #define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K 23 24 /* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/ 25 #define CXL_CM_OFFSET 0x1000 26 #define CXL_CM_CAP_HDR_OFFSET 0x0 27 #define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0) 28 #define CM_CAP_HDR_CAP_ID 1 29 #define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16) 30 #define CM_CAP_HDR_CAP_VERSION 1 31 #define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20) 32 #define CM_CAP_HDR_CACHE_MEM_VERSION 1 33 #define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24) 34 #define CXL_CM_CAP_PTR_MASK GENMASK(31, 20) 35 36 #define CXL_CM_CAP_CAP_ID_RAS 0x2 37 #define CXL_CM_CAP_CAP_ID_HDM 0x5 38 #define CXL_CM_CAP_CAP_HDM_VERSION 1 39 40 /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */ 41 #define CXL_HDM_DECODER_CAP_OFFSET 0x0 42 #define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0) 43 #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4) 44 #define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8) 45 #define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9) 46 #define CXL_HDM_DECODER_CTRL_OFFSET 0x4 47 #define CXL_HDM_DECODER_ENABLE BIT(1) 48 #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10) 49 #define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14) 50 #define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18) 51 #define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c) 52 #define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20) 53 #define CXL_HDM_DECODER0_CTRL_IG_MASK GENMASK(3, 0) 54 #define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4) 55 #define CXL_HDM_DECODER0_CTRL_LOCK BIT(8) 56 #define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9) 57 #define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10) 58 #define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11) 59 #define CXL_HDM_DECODER0_CTRL_TYPE BIT(12) 60 #define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24) 61 #define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28) 62 #define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i) 63 #define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i) 64 65 /* HDM decoder control register constants CXL 3.0 8.2.5.19.7 */ 66 #define CXL_DECODER_MIN_GRANULARITY 256 67 #define CXL_DECODER_MAX_ENCODED_IG 6 68 69 static inline int cxl_hdm_decoder_count(u32 cap_hdr) 70 { 71 int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr); 72 73 return val ? val * 2 : 1; 74 } 75 76 /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ 77 static inline int eig_to_granularity(u16 eig, unsigned int *granularity) 78 { 79 if (eig > CXL_DECODER_MAX_ENCODED_IG) 80 return -EINVAL; 81 *granularity = CXL_DECODER_MIN_GRANULARITY << eig; 82 return 0; 83 } 84 85 /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */ 86 static inline int eiw_to_ways(u8 eiw, unsigned int *ways) 87 { 88 switch (eiw) { 89 case 0 ... 4: 90 *ways = 1 << eiw; 91 break; 92 case 8 ... 10: 93 *ways = 3 << (eiw - 8); 94 break; 95 default: 96 return -EINVAL; 97 } 98 99 return 0; 100 } 101 102 static inline int granularity_to_eig(int granularity, u16 *eig) 103 { 104 if (granularity > SZ_16K || granularity < CXL_DECODER_MIN_GRANULARITY || 105 !is_power_of_2(granularity)) 106 return -EINVAL; 107 *eig = ilog2(granularity) - 8; 108 return 0; 109 } 110 111 static inline int ways_to_eiw(unsigned int ways, u8 *eiw) 112 { 113 if (ways > 16) 114 return -EINVAL; 115 if (is_power_of_2(ways)) { 116 *eiw = ilog2(ways); 117 return 0; 118 } 119 if (ways % 3) 120 return -EINVAL; 121 ways /= 3; 122 if (!is_power_of_2(ways)) 123 return -EINVAL; 124 *eiw = ilog2(ways) + 8; 125 return 0; 126 } 127 128 /* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */ 129 #define CXL_RAS_UNCORRECTABLE_STATUS_OFFSET 0x0 130 #define CXL_RAS_UNCORRECTABLE_STATUS_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 131 #define CXL_RAS_UNCORRECTABLE_MASK_OFFSET 0x4 132 #define CXL_RAS_UNCORRECTABLE_MASK_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 133 #define CXL_RAS_UNCORRECTABLE_SEVERITY_OFFSET 0x8 134 #define CXL_RAS_UNCORRECTABLE_SEVERITY_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 135 #define CXL_RAS_CORRECTABLE_STATUS_OFFSET 0xC 136 #define CXL_RAS_CORRECTABLE_STATUS_MASK GENMASK(6, 0) 137 #define CXL_RAS_CORRECTABLE_MASK_OFFSET 0x10 138 #define CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0) 139 #define CXL_RAS_CAP_CONTROL_OFFSET 0x14 140 #define CXL_RAS_CAP_CONTROL_FE_MASK GENMASK(5, 0) 141 #define CXL_RAS_HEADER_LOG_OFFSET 0x18 142 #define CXL_RAS_CAPABILITY_LENGTH 0x58 143 #define CXL_HEADERLOG_SIZE SZ_512 144 #define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32) 145 146 /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ 147 #define CXLDEV_CAP_ARRAY_OFFSET 0x0 148 #define CXLDEV_CAP_ARRAY_CAP_ID 0 149 #define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0) 150 #define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32) 151 /* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */ 152 #define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0) 153 /* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */ 154 #define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1 155 #define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2 156 #define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3 157 #define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000 158 159 /* CXL 2.0 8.2.8.4 Mailbox Registers */ 160 #define CXLDEV_MBOX_CAPS_OFFSET 0x00 161 #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0) 162 #define CXLDEV_MBOX_CTRL_OFFSET 0x04 163 #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0) 164 #define CXLDEV_MBOX_CMD_OFFSET 0x08 165 #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) 166 #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16) 167 #define CXLDEV_MBOX_STATUS_OFFSET 0x10 168 #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32) 169 #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18 170 #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20 171 172 /* 173 * Using struct_group() allows for per register-block-type helper routines, 174 * without requiring block-type agnostic code to include the prefix. 175 */ 176 struct cxl_regs { 177 /* 178 * Common set of CXL Component register block base pointers 179 * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure 180 * @ras: CXL 2.0 8.2.5.9 CXL RAS Capability Structure 181 */ 182 struct_group_tagged(cxl_component_regs, component, 183 void __iomem *hdm_decoder; 184 void __iomem *ras; 185 ); 186 /* 187 * Common set of CXL Device register block base pointers 188 * @status: CXL 2.0 8.2.8.3 Device Status Registers 189 * @mbox: CXL 2.0 8.2.8.4 Mailbox Registers 190 * @memdev: CXL 2.0 8.2.8.5 Memory Device Registers 191 */ 192 struct_group_tagged(cxl_device_regs, device_regs, 193 void __iomem *status, *mbox, *memdev; 194 ); 195 }; 196 197 struct cxl_reg_map { 198 bool valid; 199 int id; 200 unsigned long offset; 201 unsigned long size; 202 }; 203 204 struct cxl_component_reg_map { 205 struct cxl_reg_map hdm_decoder; 206 struct cxl_reg_map ras; 207 }; 208 209 struct cxl_device_reg_map { 210 struct cxl_reg_map status; 211 struct cxl_reg_map mbox; 212 struct cxl_reg_map memdev; 213 }; 214 215 /** 216 * struct cxl_register_map - DVSEC harvested register block mapping parameters 217 * @base: virtual base of the register-block-BAR + @block_offset 218 * @resource: physical resource base of the register block 219 * @max_size: maximum mapping size to perform register search 220 * @reg_type: see enum cxl_regloc_type 221 * @component_map: cxl_reg_map for component registers 222 * @device_map: cxl_reg_maps for device registers 223 */ 224 struct cxl_register_map { 225 void __iomem *base; 226 resource_size_t resource; 227 resource_size_t max_size; 228 u8 reg_type; 229 union { 230 struct cxl_component_reg_map component_map; 231 struct cxl_device_reg_map device_map; 232 }; 233 }; 234 235 void cxl_probe_component_regs(struct device *dev, void __iomem *base, 236 struct cxl_component_reg_map *map); 237 void cxl_probe_device_regs(struct device *dev, void __iomem *base, 238 struct cxl_device_reg_map *map); 239 int cxl_map_component_regs(struct device *dev, struct cxl_component_regs *regs, 240 struct cxl_register_map *map, 241 unsigned long map_mask); 242 int cxl_map_device_regs(struct device *dev, struct cxl_device_regs *regs, 243 struct cxl_register_map *map); 244 245 enum cxl_regloc_type; 246 int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, 247 struct cxl_register_map *map); 248 249 enum cxl_rcrb { 250 CXL_RCRB_DOWNSTREAM, 251 CXL_RCRB_UPSTREAM, 252 }; 253 resource_size_t cxl_rcrb_to_component(struct device *dev, 254 resource_size_t rcrb, 255 enum cxl_rcrb which); 256 257 #define CXL_RESOURCE_NONE ((resource_size_t) -1) 258 #define CXL_TARGET_STRLEN 20 259 260 /* 261 * cxl_decoder flags that define the type of memory / devices this 262 * decoder supports as well as configuration lock status See "CXL 2.0 263 * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details. 264 * Additionally indicate whether decoder settings were autodetected, 265 * user customized. 266 */ 267 #define CXL_DECODER_F_RAM BIT(0) 268 #define CXL_DECODER_F_PMEM BIT(1) 269 #define CXL_DECODER_F_TYPE2 BIT(2) 270 #define CXL_DECODER_F_TYPE3 BIT(3) 271 #define CXL_DECODER_F_LOCK BIT(4) 272 #define CXL_DECODER_F_ENABLE BIT(5) 273 #define CXL_DECODER_F_MASK GENMASK(5, 0) 274 275 enum cxl_decoder_type { 276 CXL_DECODER_ACCELERATOR = 2, 277 CXL_DECODER_EXPANDER = 3, 278 }; 279 280 /* 281 * Current specification goes up to 8, double that seems a reasonable 282 * software max for the foreseeable future 283 */ 284 #define CXL_DECODER_MAX_INTERLEAVE 16 285 286 287 /** 288 * struct cxl_decoder - Common CXL HDM Decoder Attributes 289 * @dev: this decoder's device 290 * @id: kernel device name id 291 * @hpa_range: Host physical address range mapped by this decoder 292 * @interleave_ways: number of cxl_dports in this decode 293 * @interleave_granularity: data stride per dport 294 * @target_type: accelerator vs expander (type2 vs type3) selector 295 * @region: currently assigned region for this decoder 296 * @flags: memory type capabilities and locking 297 * @commit: device/decoder-type specific callback to commit settings to hw 298 * @reset: device/decoder-type specific callback to reset hw settings 299 */ 300 struct cxl_decoder { 301 struct device dev; 302 int id; 303 struct range hpa_range; 304 int interleave_ways; 305 int interleave_granularity; 306 enum cxl_decoder_type target_type; 307 struct cxl_region *region; 308 unsigned long flags; 309 int (*commit)(struct cxl_decoder *cxld); 310 int (*reset)(struct cxl_decoder *cxld); 311 }; 312 313 /* 314 * CXL_DECODER_DEAD prevents endpoints from being reattached to regions 315 * while cxld_unregister() is running 316 */ 317 enum cxl_decoder_mode { 318 CXL_DECODER_NONE, 319 CXL_DECODER_RAM, 320 CXL_DECODER_PMEM, 321 CXL_DECODER_MIXED, 322 CXL_DECODER_DEAD, 323 }; 324 325 static inline const char *cxl_decoder_mode_name(enum cxl_decoder_mode mode) 326 { 327 static const char * const names[] = { 328 [CXL_DECODER_NONE] = "none", 329 [CXL_DECODER_RAM] = "ram", 330 [CXL_DECODER_PMEM] = "pmem", 331 [CXL_DECODER_MIXED] = "mixed", 332 }; 333 334 if (mode >= CXL_DECODER_NONE && mode <= CXL_DECODER_MIXED) 335 return names[mode]; 336 return "mixed"; 337 } 338 339 /* 340 * Track whether this decoder is reserved for region autodiscovery, or 341 * free for userspace provisioning. 342 */ 343 enum cxl_decoder_state { 344 CXL_DECODER_STATE_MANUAL, 345 CXL_DECODER_STATE_AUTO, 346 }; 347 348 /** 349 * struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder 350 * @cxld: base cxl_decoder_object 351 * @dpa_res: actively claimed DPA span of this decoder 352 * @skip: offset into @dpa_res where @cxld.hpa_range maps 353 * @mode: which memory type / access-mode-partition this decoder targets 354 * @state: autodiscovery state 355 * @pos: interleave position in @cxld.region 356 */ 357 struct cxl_endpoint_decoder { 358 struct cxl_decoder cxld; 359 struct resource *dpa_res; 360 resource_size_t skip; 361 enum cxl_decoder_mode mode; 362 enum cxl_decoder_state state; 363 int pos; 364 }; 365 366 /** 367 * struct cxl_switch_decoder - Switch specific CXL HDM Decoder 368 * @cxld: base cxl_decoder object 369 * @target_lock: coordinate coherent reads of the target list 370 * @nr_targets: number of elements in @target 371 * @target: active ordered target list in current decoder configuration 372 * 373 * The 'switch' decoder type represents the decoder instances of cxl_port's that 374 * route from the root of a CXL memory decode topology to the endpoints. They 375 * come in two flavors, root-level decoders, statically defined by platform 376 * firmware, and mid-level decoders, where interleave-granularity, 377 * interleave-width, and the target list are mutable. 378 */ 379 struct cxl_switch_decoder { 380 struct cxl_decoder cxld; 381 seqlock_t target_lock; 382 int nr_targets; 383 struct cxl_dport *target[]; 384 }; 385 386 struct cxl_root_decoder; 387 typedef struct cxl_dport *(*cxl_calc_hb_fn)(struct cxl_root_decoder *cxlrd, 388 int pos); 389 390 /** 391 * struct cxl_root_decoder - Static platform CXL address decoder 392 * @res: host / parent resource for region allocations 393 * @region_id: region id for next region provisioning event 394 * @calc_hb: which host bridge covers the n'th position by granularity 395 * @platform_data: platform specific configuration data 396 * @range_lock: sync region autodiscovery by address range 397 * @cxlsd: base cxl switch decoder 398 */ 399 struct cxl_root_decoder { 400 struct resource *res; 401 atomic_t region_id; 402 cxl_calc_hb_fn calc_hb; 403 void *platform_data; 404 struct mutex range_lock; 405 struct cxl_switch_decoder cxlsd; 406 }; 407 408 /* 409 * enum cxl_config_state - State machine for region configuration 410 * @CXL_CONFIG_IDLE: Any sysfs attribute can be written freely 411 * @CXL_CONFIG_INTERLEAVE_ACTIVE: region size has been set, no more 412 * changes to interleave_ways or interleave_granularity 413 * @CXL_CONFIG_ACTIVE: All targets have been added the region is now 414 * active 415 * @CXL_CONFIG_RESET_PENDING: see commit_store() 416 * @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware 417 */ 418 enum cxl_config_state { 419 CXL_CONFIG_IDLE, 420 CXL_CONFIG_INTERLEAVE_ACTIVE, 421 CXL_CONFIG_ACTIVE, 422 CXL_CONFIG_RESET_PENDING, 423 CXL_CONFIG_COMMIT, 424 }; 425 426 /** 427 * struct cxl_region_params - region settings 428 * @state: allow the driver to lockdown further parameter changes 429 * @uuid: unique id for persistent regions 430 * @interleave_ways: number of endpoints in the region 431 * @interleave_granularity: capacity each endpoint contributes to a stripe 432 * @res: allocated iomem capacity for this region 433 * @targets: active ordered targets in current decoder configuration 434 * @nr_targets: number of targets 435 * 436 * State transitions are protected by the cxl_region_rwsem 437 */ 438 struct cxl_region_params { 439 enum cxl_config_state state; 440 uuid_t uuid; 441 int interleave_ways; 442 int interleave_granularity; 443 struct resource *res; 444 struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE]; 445 int nr_targets; 446 }; 447 448 /* 449 * Flag whether this region needs to have its HPA span synchronized with 450 * CPU cache state at region activation time. 451 */ 452 #define CXL_REGION_F_INCOHERENT 0 453 454 /* 455 * Indicate whether this region has been assembled by autodetection or 456 * userspace assembly. Prevent endpoint decoders outside of automatic 457 * detection from being added to the region. 458 */ 459 #define CXL_REGION_F_AUTO 1 460 461 /** 462 * struct cxl_region - CXL region 463 * @dev: This region's device 464 * @id: This region's id. Id is globally unique across all regions 465 * @mode: Endpoint decoder allocation / access mode 466 * @type: Endpoint decoder target type 467 * @cxl_nvb: nvdimm bridge for coordinating @cxlr_pmem setup / shutdown 468 * @cxlr_pmem: (for pmem regions) cached copy of the nvdimm bridge 469 * @flags: Region state flags 470 * @params: active + config params for the region 471 */ 472 struct cxl_region { 473 struct device dev; 474 int id; 475 enum cxl_decoder_mode mode; 476 enum cxl_decoder_type type; 477 struct cxl_nvdimm_bridge *cxl_nvb; 478 struct cxl_pmem_region *cxlr_pmem; 479 unsigned long flags; 480 struct cxl_region_params params; 481 }; 482 483 struct cxl_nvdimm_bridge { 484 int id; 485 struct device dev; 486 struct cxl_port *port; 487 struct nvdimm_bus *nvdimm_bus; 488 struct nvdimm_bus_descriptor nd_desc; 489 }; 490 491 #define CXL_DEV_ID_LEN 19 492 493 struct cxl_nvdimm { 494 struct device dev; 495 struct cxl_memdev *cxlmd; 496 u8 dev_id[CXL_DEV_ID_LEN]; /* for nvdimm, string of 'serial' */ 497 }; 498 499 struct cxl_pmem_region_mapping { 500 struct cxl_memdev *cxlmd; 501 struct cxl_nvdimm *cxl_nvd; 502 u64 start; 503 u64 size; 504 int position; 505 }; 506 507 struct cxl_pmem_region { 508 struct device dev; 509 struct cxl_region *cxlr; 510 struct nd_region *nd_region; 511 struct range hpa_range; 512 int nr_mappings; 513 struct cxl_pmem_region_mapping mapping[]; 514 }; 515 516 /** 517 * struct cxl_port - logical collection of upstream port devices and 518 * downstream port devices to construct a CXL memory 519 * decode hierarchy. 520 * @dev: this port's device 521 * @uport: PCI or platform device implementing the upstream port capability 522 * @host_bridge: Shortcut to the platform attach point for this port 523 * @id: id for port device-name 524 * @dports: cxl_dport instances referenced by decoders 525 * @endpoints: cxl_ep instances, endpoints that are a descendant of this port 526 * @regions: cxl_region_ref instances, regions mapped by this port 527 * @parent_dport: dport that points to this port in the parent 528 * @decoder_ida: allocator for decoder ids 529 * @nr_dports: number of entries in @dports 530 * @hdm_end: track last allocated HDM decoder instance for allocation ordering 531 * @commit_end: cursor to track highest committed decoder for commit ordering 532 * @component_reg_phys: component register capability base address (optional) 533 * @dead: last ep has been removed, force port re-creation 534 * @depth: How deep this port is relative to the root. depth 0 is the root. 535 * @cdat: Cached CDAT data 536 * @cdat_available: Should a CDAT attribute be available in sysfs 537 */ 538 struct cxl_port { 539 struct device dev; 540 struct device *uport; 541 struct device *host_bridge; 542 int id; 543 struct xarray dports; 544 struct xarray endpoints; 545 struct xarray regions; 546 struct cxl_dport *parent_dport; 547 struct ida decoder_ida; 548 int nr_dports; 549 int hdm_end; 550 int commit_end; 551 resource_size_t component_reg_phys; 552 bool dead; 553 unsigned int depth; 554 struct cxl_cdat { 555 void *table; 556 size_t length; 557 } cdat; 558 bool cdat_available; 559 }; 560 561 static inline struct cxl_dport * 562 cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev) 563 { 564 return xa_load(&port->dports, (unsigned long)dport_dev); 565 } 566 567 /** 568 * struct cxl_dport - CXL downstream port 569 * @dport: PCI bridge or firmware device representing the downstream link 570 * @port_id: unique hardware identifier for dport in decoder target list 571 * @component_reg_phys: downstream port component registers 572 * @rcrb: base address for the Root Complex Register Block 573 * @rch: Indicate whether this dport was enumerated in RCH or VH mode 574 * @port: reference to cxl_port that contains this downstream port 575 */ 576 struct cxl_dport { 577 struct device *dport; 578 int port_id; 579 resource_size_t component_reg_phys; 580 resource_size_t rcrb; 581 bool rch; 582 struct cxl_port *port; 583 }; 584 585 /** 586 * struct cxl_ep - track an endpoint's interest in a port 587 * @ep: device that hosts a generic CXL endpoint (expander or accelerator) 588 * @dport: which dport routes to this endpoint on @port 589 * @next: cxl switch port across the link attached to @dport NULL if 590 * attached to an endpoint 591 */ 592 struct cxl_ep { 593 struct device *ep; 594 struct cxl_dport *dport; 595 struct cxl_port *next; 596 }; 597 598 /** 599 * struct cxl_region_ref - track a region's interest in a port 600 * @port: point in topology to install this reference 601 * @decoder: decoder assigned for @region in @port 602 * @region: region for this reference 603 * @endpoints: cxl_ep references for region members beneath @port 604 * @nr_targets_set: track how many targets have been programmed during setup 605 * @nr_eps: number of endpoints beneath @port 606 * @nr_targets: number of distinct targets needed to reach @nr_eps 607 */ 608 struct cxl_region_ref { 609 struct cxl_port *port; 610 struct cxl_decoder *decoder; 611 struct cxl_region *region; 612 struct xarray endpoints; 613 int nr_targets_set; 614 int nr_eps; 615 int nr_targets; 616 }; 617 618 /* 619 * The platform firmware device hosting the root is also the top of the 620 * CXL port topology. All other CXL ports have another CXL port as their 621 * parent and their ->uport / host device is out-of-line of the port 622 * ancestry. 623 */ 624 static inline bool is_cxl_root(struct cxl_port *port) 625 { 626 return port->uport == port->dev.parent; 627 } 628 629 bool is_cxl_port(struct device *dev); 630 struct cxl_port *to_cxl_port(struct device *dev); 631 struct pci_bus; 632 int devm_cxl_register_pci_bus(struct device *host, struct device *uport, 633 struct pci_bus *bus); 634 struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port); 635 struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport, 636 resource_size_t component_reg_phys, 637 struct cxl_dport *parent_dport); 638 struct cxl_port *find_cxl_root(struct device *dev); 639 int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); 640 void cxl_bus_rescan(void); 641 void cxl_bus_drain(void); 642 struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd, 643 struct cxl_dport **dport); 644 bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd); 645 646 struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, 647 struct device *dport, int port_id, 648 resource_size_t component_reg_phys); 649 struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, 650 struct device *dport_dev, int port_id, 651 resource_size_t component_reg_phys, 652 resource_size_t rcrb); 653 654 struct cxl_decoder *to_cxl_decoder(struct device *dev); 655 struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev); 656 struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev); 657 struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev); 658 bool is_root_decoder(struct device *dev); 659 bool is_switch_decoder(struct device *dev); 660 bool is_endpoint_decoder(struct device *dev); 661 struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, 662 unsigned int nr_targets, 663 cxl_calc_hb_fn calc_hb); 664 struct cxl_dport *cxl_hb_modulo(struct cxl_root_decoder *cxlrd, int pos); 665 struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port, 666 unsigned int nr_targets); 667 int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map); 668 struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port); 669 int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map); 670 int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld); 671 int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint); 672 673 struct cxl_hdm; 674 struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port); 675 int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm); 676 int devm_cxl_add_passthrough_decoder(struct cxl_port *port); 677 678 bool is_cxl_region(struct device *dev); 679 680 extern struct bus_type cxl_bus_type; 681 682 struct cxl_driver { 683 const char *name; 684 int (*probe)(struct device *dev); 685 void (*remove)(struct device *dev); 686 struct device_driver drv; 687 int id; 688 }; 689 690 static inline struct cxl_driver *to_cxl_drv(struct device_driver *drv) 691 { 692 return container_of(drv, struct cxl_driver, drv); 693 } 694 695 int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner, 696 const char *modname); 697 #define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME) 698 void cxl_driver_unregister(struct cxl_driver *cxl_drv); 699 700 #define module_cxl_driver(__cxl_driver) \ 701 module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister) 702 703 #define CXL_DEVICE_NVDIMM_BRIDGE 1 704 #define CXL_DEVICE_NVDIMM 2 705 #define CXL_DEVICE_PORT 3 706 #define CXL_DEVICE_ROOT 4 707 #define CXL_DEVICE_MEMORY_EXPANDER 5 708 #define CXL_DEVICE_REGION 6 709 #define CXL_DEVICE_PMEM_REGION 7 710 711 #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*") 712 #define CXL_MODALIAS_FMT "cxl:t%d" 713 714 struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev); 715 struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host, 716 struct cxl_port *port); 717 struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev); 718 bool is_cxl_nvdimm(struct device *dev); 719 bool is_cxl_nvdimm_bridge(struct device *dev); 720 int devm_cxl_add_nvdimm(struct cxl_memdev *cxlmd); 721 struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct device *dev); 722 723 #ifdef CONFIG_CXL_REGION 724 bool is_cxl_pmem_region(struct device *dev); 725 struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev); 726 int cxl_add_to_region(struct cxl_port *root, 727 struct cxl_endpoint_decoder *cxled); 728 #else 729 static inline bool is_cxl_pmem_region(struct device *dev) 730 { 731 return false; 732 } 733 static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev) 734 { 735 return NULL; 736 } 737 static inline int cxl_add_to_region(struct cxl_port *root, 738 struct cxl_endpoint_decoder *cxled) 739 { 740 return 0; 741 } 742 #endif 743 744 /* 745 * Unit test builds overrides this to __weak, find the 'strong' version 746 * of these symbols in tools/testing/cxl/. 747 */ 748 #ifndef __mock 749 #define __mock static 750 #endif 751 752 #endif /* __CXL_H__ */ 753