1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020 Intel Corporation. */ 3 4 #ifndef __CXL_H__ 5 #define __CXL_H__ 6 7 #include <linux/libnvdimm.h> 8 #include <linux/bitfield.h> 9 #include <linux/notifier.h> 10 #include <linux/bitops.h> 11 #include <linux/log2.h> 12 #include <linux/node.h> 13 #include <linux/io.h> 14 #include <linux/range.h> 15 16 extern const struct nvdimm_security_ops *cxl_security_ops; 17 18 /** 19 * DOC: cxl objects 20 * 21 * The CXL core objects like ports, decoders, and regions are shared 22 * between the subsystem drivers cxl_acpi, cxl_pci, and core drivers 23 * (port-driver, region-driver, nvdimm object-drivers... etc). 24 */ 25 26 /* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */ 27 #define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K 28 29 /* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/ 30 #define CXL_CM_OFFSET 0x1000 31 #define CXL_CM_CAP_HDR_OFFSET 0x0 32 #define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0) 33 #define CM_CAP_HDR_CAP_ID 1 34 #define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16) 35 #define CM_CAP_HDR_CAP_VERSION 1 36 #define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20) 37 #define CM_CAP_HDR_CACHE_MEM_VERSION 1 38 #define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24) 39 #define CXL_CM_CAP_PTR_MASK GENMASK(31, 20) 40 41 #define CXL_CM_CAP_CAP_ID_RAS 0x2 42 #define CXL_CM_CAP_CAP_ID_HDM 0x5 43 #define CXL_CM_CAP_CAP_HDM_VERSION 1 44 45 /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */ 46 #define CXL_HDM_DECODER_CAP_OFFSET 0x0 47 #define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0) 48 #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4) 49 #define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8) 50 #define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9) 51 #define CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY BIT(11) 52 #define CXL_HDM_DECODER_INTERLEAVE_16_WAY BIT(12) 53 #define CXL_HDM_DECODER_CTRL_OFFSET 0x4 54 #define CXL_HDM_DECODER_ENABLE BIT(1) 55 #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10) 56 #define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14) 57 #define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18) 58 #define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c) 59 #define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20) 60 #define CXL_HDM_DECODER0_CTRL_IG_MASK GENMASK(3, 0) 61 #define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4) 62 #define CXL_HDM_DECODER0_CTRL_LOCK BIT(8) 63 #define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9) 64 #define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10) 65 #define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11) 66 #define CXL_HDM_DECODER0_CTRL_HOSTONLY BIT(12) 67 #define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24) 68 #define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28) 69 #define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i) 70 #define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i) 71 72 /* HDM decoder control register constants CXL 3.0 8.2.5.19.7 */ 73 #define CXL_DECODER_MIN_GRANULARITY 256 74 #define CXL_DECODER_MAX_ENCODED_IG 6 75 76 static inline int cxl_hdm_decoder_count(u32 cap_hdr) 77 { 78 int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr); 79 80 return val ? val * 2 : 1; 81 } 82 83 /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ 84 static inline int eig_to_granularity(u16 eig, unsigned int *granularity) 85 { 86 if (eig > CXL_DECODER_MAX_ENCODED_IG) 87 return -EINVAL; 88 *granularity = CXL_DECODER_MIN_GRANULARITY << eig; 89 return 0; 90 } 91 92 /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */ 93 static inline int eiw_to_ways(u8 eiw, unsigned int *ways) 94 { 95 switch (eiw) { 96 case 0 ... 4: 97 *ways = 1 << eiw; 98 break; 99 case 8 ... 10: 100 *ways = 3 << (eiw - 8); 101 break; 102 default: 103 return -EINVAL; 104 } 105 106 return 0; 107 } 108 109 static inline int granularity_to_eig(int granularity, u16 *eig) 110 { 111 if (granularity > SZ_16K || granularity < CXL_DECODER_MIN_GRANULARITY || 112 !is_power_of_2(granularity)) 113 return -EINVAL; 114 *eig = ilog2(granularity) - 8; 115 return 0; 116 } 117 118 static inline int ways_to_eiw(unsigned int ways, u8 *eiw) 119 { 120 if (ways > 16) 121 return -EINVAL; 122 if (is_power_of_2(ways)) { 123 *eiw = ilog2(ways); 124 return 0; 125 } 126 if (ways % 3) 127 return -EINVAL; 128 ways /= 3; 129 if (!is_power_of_2(ways)) 130 return -EINVAL; 131 *eiw = ilog2(ways) + 8; 132 return 0; 133 } 134 135 /* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */ 136 #define CXL_RAS_UNCORRECTABLE_STATUS_OFFSET 0x0 137 #define CXL_RAS_UNCORRECTABLE_STATUS_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 138 #define CXL_RAS_UNCORRECTABLE_MASK_OFFSET 0x4 139 #define CXL_RAS_UNCORRECTABLE_MASK_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 140 #define CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK BIT(8) 141 #define CXL_RAS_UNCORRECTABLE_SEVERITY_OFFSET 0x8 142 #define CXL_RAS_UNCORRECTABLE_SEVERITY_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 143 #define CXL_RAS_CORRECTABLE_STATUS_OFFSET 0xC 144 #define CXL_RAS_CORRECTABLE_STATUS_MASK GENMASK(6, 0) 145 #define CXL_RAS_CORRECTABLE_MASK_OFFSET 0x10 146 #define CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0) 147 #define CXL_RAS_CAP_CONTROL_OFFSET 0x14 148 #define CXL_RAS_CAP_CONTROL_FE_MASK GENMASK(5, 0) 149 #define CXL_RAS_HEADER_LOG_OFFSET 0x18 150 #define CXL_RAS_CAPABILITY_LENGTH 0x58 151 #define CXL_HEADERLOG_SIZE SZ_512 152 #define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32) 153 154 /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ 155 #define CXLDEV_CAP_ARRAY_OFFSET 0x0 156 #define CXLDEV_CAP_ARRAY_CAP_ID 0 157 #define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0) 158 #define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32) 159 /* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */ 160 #define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0) 161 /* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */ 162 #define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1 163 #define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2 164 #define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3 165 #define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000 166 167 /* CXL 3.0 8.2.8.3.1 Event Status Register */ 168 #define CXLDEV_DEV_EVENT_STATUS_OFFSET 0x00 169 #define CXLDEV_EVENT_STATUS_INFO BIT(0) 170 #define CXLDEV_EVENT_STATUS_WARN BIT(1) 171 #define CXLDEV_EVENT_STATUS_FAIL BIT(2) 172 #define CXLDEV_EVENT_STATUS_FATAL BIT(3) 173 174 #define CXLDEV_EVENT_STATUS_ALL (CXLDEV_EVENT_STATUS_INFO | \ 175 CXLDEV_EVENT_STATUS_WARN | \ 176 CXLDEV_EVENT_STATUS_FAIL | \ 177 CXLDEV_EVENT_STATUS_FATAL) 178 179 /* CXL rev 3.0 section 8.2.9.2.4; Table 8-52 */ 180 #define CXLDEV_EVENT_INT_MODE_MASK GENMASK(1, 0) 181 #define CXLDEV_EVENT_INT_MSGNUM_MASK GENMASK(7, 4) 182 183 /* CXL 2.0 8.2.8.4 Mailbox Registers */ 184 #define CXLDEV_MBOX_CAPS_OFFSET 0x00 185 #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0) 186 #define CXLDEV_MBOX_CAP_BG_CMD_IRQ BIT(6) 187 #define CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK GENMASK(10, 7) 188 #define CXLDEV_MBOX_CTRL_OFFSET 0x04 189 #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0) 190 #define CXLDEV_MBOX_CTRL_BG_CMD_IRQ BIT(2) 191 #define CXLDEV_MBOX_CMD_OFFSET 0x08 192 #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) 193 #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16) 194 #define CXLDEV_MBOX_STATUS_OFFSET 0x10 195 #define CXLDEV_MBOX_STATUS_BG_CMD BIT(0) 196 #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32) 197 #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18 198 #define CXLDEV_MBOX_BG_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) 199 #define CXLDEV_MBOX_BG_CMD_COMMAND_PCT_MASK GENMASK_ULL(22, 16) 200 #define CXLDEV_MBOX_BG_CMD_COMMAND_RC_MASK GENMASK_ULL(47, 32) 201 #define CXLDEV_MBOX_BG_CMD_COMMAND_VENDOR_MASK GENMASK_ULL(63, 48) 202 #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20 203 204 /* 205 * Using struct_group() allows for per register-block-type helper routines, 206 * without requiring block-type agnostic code to include the prefix. 207 */ 208 struct cxl_regs { 209 /* 210 * Common set of CXL Component register block base pointers 211 * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure 212 * @ras: CXL 2.0 8.2.5.9 CXL RAS Capability Structure 213 */ 214 struct_group_tagged(cxl_component_regs, component, 215 void __iomem *hdm_decoder; 216 void __iomem *ras; 217 ); 218 /* 219 * Common set of CXL Device register block base pointers 220 * @status: CXL 2.0 8.2.8.3 Device Status Registers 221 * @mbox: CXL 2.0 8.2.8.4 Mailbox Registers 222 * @memdev: CXL 2.0 8.2.8.5 Memory Device Registers 223 */ 224 struct_group_tagged(cxl_device_regs, device_regs, 225 void __iomem *status, *mbox, *memdev; 226 ); 227 228 struct_group_tagged(cxl_pmu_regs, pmu_regs, 229 void __iomem *pmu; 230 ); 231 232 /* 233 * RCH downstream port specific RAS register 234 * @aer: CXL 3.0 8.2.1.1 RCH Downstream Port RCRB 235 */ 236 struct_group_tagged(cxl_rch_regs, rch_regs, 237 void __iomem *dport_aer; 238 ); 239 240 /* 241 * RCD upstream port specific PCIe cap register 242 * @pcie_cap: CXL 3.0 8.2.1.2 RCD Upstream Port RCRB 243 */ 244 struct_group_tagged(cxl_rcd_regs, rcd_regs, 245 void __iomem *rcd_pcie_cap; 246 ); 247 }; 248 249 struct cxl_reg_map { 250 bool valid; 251 int id; 252 unsigned long offset; 253 unsigned long size; 254 }; 255 256 struct cxl_component_reg_map { 257 struct cxl_reg_map hdm_decoder; 258 struct cxl_reg_map ras; 259 }; 260 261 struct cxl_device_reg_map { 262 struct cxl_reg_map status; 263 struct cxl_reg_map mbox; 264 struct cxl_reg_map memdev; 265 }; 266 267 struct cxl_pmu_reg_map { 268 struct cxl_reg_map pmu; 269 }; 270 271 /** 272 * struct cxl_register_map - DVSEC harvested register block mapping parameters 273 * @host: device for devm operations and logging 274 * @base: virtual base of the register-block-BAR + @block_offset 275 * @resource: physical resource base of the register block 276 * @max_size: maximum mapping size to perform register search 277 * @reg_type: see enum cxl_regloc_type 278 * @component_map: cxl_reg_map for component registers 279 * @device_map: cxl_reg_maps for device registers 280 * @pmu_map: cxl_reg_maps for CXL Performance Monitoring Units 281 */ 282 struct cxl_register_map { 283 struct device *host; 284 void __iomem *base; 285 resource_size_t resource; 286 resource_size_t max_size; 287 u8 reg_type; 288 union { 289 struct cxl_component_reg_map component_map; 290 struct cxl_device_reg_map device_map; 291 struct cxl_pmu_reg_map pmu_map; 292 }; 293 }; 294 295 void cxl_probe_component_regs(struct device *dev, void __iomem *base, 296 struct cxl_component_reg_map *map); 297 void cxl_probe_device_regs(struct device *dev, void __iomem *base, 298 struct cxl_device_reg_map *map); 299 int cxl_map_component_regs(const struct cxl_register_map *map, 300 struct cxl_component_regs *regs, 301 unsigned long map_mask); 302 int cxl_map_device_regs(const struct cxl_register_map *map, 303 struct cxl_device_regs *regs); 304 int cxl_map_pmu_regs(struct cxl_register_map *map, struct cxl_pmu_regs *regs); 305 306 #define CXL_INSTANCES_COUNT -1 307 enum cxl_regloc_type; 308 int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type); 309 int cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type, 310 struct cxl_register_map *map, unsigned int index); 311 int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, 312 struct cxl_register_map *map); 313 int cxl_setup_regs(struct cxl_register_map *map); 314 struct cxl_dport; 315 resource_size_t cxl_rcd_component_reg_phys(struct device *dev, 316 struct cxl_dport *dport); 317 int cxl_dport_map_rcd_linkcap(struct pci_dev *pdev, struct cxl_dport *dport); 318 319 #define CXL_RESOURCE_NONE ((resource_size_t) -1) 320 #define CXL_TARGET_STRLEN 20 321 322 /* 323 * cxl_decoder flags that define the type of memory / devices this 324 * decoder supports as well as configuration lock status See "CXL 2.0 325 * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details. 326 * Additionally indicate whether decoder settings were autodetected, 327 * user customized. 328 */ 329 #define CXL_DECODER_F_RAM BIT(0) 330 #define CXL_DECODER_F_PMEM BIT(1) 331 #define CXL_DECODER_F_TYPE2 BIT(2) 332 #define CXL_DECODER_F_TYPE3 BIT(3) 333 #define CXL_DECODER_F_LOCK BIT(4) 334 #define CXL_DECODER_F_ENABLE BIT(5) 335 #define CXL_DECODER_F_MASK GENMASK(5, 0) 336 337 enum cxl_decoder_type { 338 CXL_DECODER_DEVMEM = 2, 339 CXL_DECODER_HOSTONLYMEM = 3, 340 }; 341 342 /* 343 * Current specification goes up to 8, double that seems a reasonable 344 * software max for the foreseeable future 345 */ 346 #define CXL_DECODER_MAX_INTERLEAVE 16 347 348 #define CXL_QOS_CLASS_INVALID -1 349 350 /** 351 * struct cxl_decoder - Common CXL HDM Decoder Attributes 352 * @dev: this decoder's device 353 * @id: kernel device name id 354 * @hpa_range: Host physical address range mapped by this decoder 355 * @interleave_ways: number of cxl_dports in this decode 356 * @interleave_granularity: data stride per dport 357 * @target_type: accelerator vs expander (type2 vs type3) selector 358 * @region: currently assigned region for this decoder 359 * @flags: memory type capabilities and locking 360 * @commit: device/decoder-type specific callback to commit settings to hw 361 * @reset: device/decoder-type specific callback to reset hw settings 362 */ 363 struct cxl_decoder { 364 struct device dev; 365 int id; 366 struct range hpa_range; 367 int interleave_ways; 368 int interleave_granularity; 369 enum cxl_decoder_type target_type; 370 struct cxl_region *region; 371 unsigned long flags; 372 int (*commit)(struct cxl_decoder *cxld); 373 void (*reset)(struct cxl_decoder *cxld); 374 }; 375 376 /* 377 * Track whether this decoder is reserved for region autodiscovery, or 378 * free for userspace provisioning. 379 */ 380 enum cxl_decoder_state { 381 CXL_DECODER_STATE_MANUAL, 382 CXL_DECODER_STATE_AUTO, 383 }; 384 385 /** 386 * struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder 387 * @cxld: base cxl_decoder_object 388 * @dpa_res: actively claimed DPA span of this decoder 389 * @skip: offset into @dpa_res where @cxld.hpa_range maps 390 * @state: autodiscovery state 391 * @part: partition index this decoder maps 392 * @pos: interleave position in @cxld.region 393 */ 394 struct cxl_endpoint_decoder { 395 struct cxl_decoder cxld; 396 struct resource *dpa_res; 397 resource_size_t skip; 398 enum cxl_decoder_state state; 399 int part; 400 int pos; 401 }; 402 403 /** 404 * struct cxl_switch_decoder - Switch specific CXL HDM Decoder 405 * @cxld: base cxl_decoder object 406 * @nr_targets: number of elements in @target 407 * @target: active ordered target list in current decoder configuration 408 * 409 * The 'switch' decoder type represents the decoder instances of cxl_port's that 410 * route from the root of a CXL memory decode topology to the endpoints. They 411 * come in two flavors, root-level decoders, statically defined by platform 412 * firmware, and mid-level decoders, where interleave-granularity, 413 * interleave-width, and the target list are mutable. 414 */ 415 struct cxl_switch_decoder { 416 struct cxl_decoder cxld; 417 int nr_targets; 418 struct cxl_dport *target[]; 419 }; 420 421 struct cxl_root_decoder; 422 typedef u64 (*cxl_hpa_to_spa_fn)(struct cxl_root_decoder *cxlrd, u64 hpa); 423 424 /** 425 * struct cxl_root_decoder - Static platform CXL address decoder 426 * @res: host / parent resource for region allocations 427 * @cache_size: extended linear cache size if exists, otherwise zero. 428 * @region_id: region id for next region provisioning event 429 * @hpa_to_spa: translate CXL host-physical-address to Platform system-physical-address 430 * @platform_data: platform specific configuration data 431 * @range_lock: sync region autodiscovery by address range 432 * @qos_class: QoS performance class cookie 433 * @cxlsd: base cxl switch decoder 434 */ 435 struct cxl_root_decoder { 436 struct resource *res; 437 resource_size_t cache_size; 438 atomic_t region_id; 439 cxl_hpa_to_spa_fn hpa_to_spa; 440 void *platform_data; 441 struct mutex range_lock; 442 int qos_class; 443 struct cxl_switch_decoder cxlsd; 444 }; 445 446 /* 447 * enum cxl_config_state - State machine for region configuration 448 * @CXL_CONFIG_IDLE: Any sysfs attribute can be written freely 449 * @CXL_CONFIG_INTERLEAVE_ACTIVE: region size has been set, no more 450 * changes to interleave_ways or interleave_granularity 451 * @CXL_CONFIG_ACTIVE: All targets have been added the region is now 452 * active 453 * @CXL_CONFIG_RESET_PENDING: see commit_store() 454 * @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware 455 */ 456 enum cxl_config_state { 457 CXL_CONFIG_IDLE, 458 CXL_CONFIG_INTERLEAVE_ACTIVE, 459 CXL_CONFIG_ACTIVE, 460 CXL_CONFIG_RESET_PENDING, 461 CXL_CONFIG_COMMIT, 462 }; 463 464 /** 465 * struct cxl_region_params - region settings 466 * @state: allow the driver to lockdown further parameter changes 467 * @uuid: unique id for persistent regions 468 * @interleave_ways: number of endpoints in the region 469 * @interleave_granularity: capacity each endpoint contributes to a stripe 470 * @res: allocated iomem capacity for this region 471 * @targets: active ordered targets in current decoder configuration 472 * @nr_targets: number of targets 473 * @cache_size: extended linear cache size if exists, otherwise zero. 474 * 475 * State transitions are protected by cxl_rwsem.region 476 */ 477 struct cxl_region_params { 478 enum cxl_config_state state; 479 uuid_t uuid; 480 int interleave_ways; 481 int interleave_granularity; 482 struct resource *res; 483 struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE]; 484 int nr_targets; 485 resource_size_t cache_size; 486 }; 487 488 enum cxl_partition_mode { 489 CXL_PARTMODE_RAM, 490 CXL_PARTMODE_PMEM, 491 }; 492 493 /* 494 * Indicate whether this region has been assembled by autodetection or 495 * userspace assembly. Prevent endpoint decoders outside of automatic 496 * detection from being added to the region. 497 */ 498 #define CXL_REGION_F_AUTO 0 499 500 /* 501 * Require that a committed region successfully complete a teardown once 502 * any of its associated decoders have been torn down. This maintains 503 * the commit state for the region since there are committed decoders, 504 * but blocks cxl_region_probe(). 505 */ 506 #define CXL_REGION_F_NEEDS_RESET 1 507 508 /** 509 * struct cxl_region - CXL region 510 * @dev: This region's device 511 * @id: This region's id. Id is globally unique across all regions 512 * @mode: Operational mode of the mapped capacity 513 * @type: Endpoint decoder target type 514 * @cxl_nvb: nvdimm bridge for coordinating @cxlr_pmem setup / shutdown 515 * @cxlr_pmem: (for pmem regions) cached copy of the nvdimm bridge 516 * @flags: Region state flags 517 * @params: active + config params for the region 518 * @coord: QoS access coordinates for the region 519 * @node_notifier: notifier for setting the access coordinates to node 520 * @adist_notifier: notifier for calculating the abstract distance of node 521 */ 522 struct cxl_region { 523 struct device dev; 524 int id; 525 enum cxl_partition_mode mode; 526 enum cxl_decoder_type type; 527 struct cxl_nvdimm_bridge *cxl_nvb; 528 struct cxl_pmem_region *cxlr_pmem; 529 unsigned long flags; 530 struct cxl_region_params params; 531 struct access_coordinate coord[ACCESS_COORDINATE_MAX]; 532 struct notifier_block node_notifier; 533 struct notifier_block adist_notifier; 534 }; 535 536 struct cxl_nvdimm_bridge { 537 int id; 538 struct device dev; 539 struct cxl_port *port; 540 struct nvdimm_bus *nvdimm_bus; 541 struct nvdimm_bus_descriptor nd_desc; 542 }; 543 544 #define CXL_DEV_ID_LEN 19 545 546 struct cxl_nvdimm { 547 struct device dev; 548 struct cxl_memdev *cxlmd; 549 u8 dev_id[CXL_DEV_ID_LEN]; /* for nvdimm, string of 'serial' */ 550 u64 dirty_shutdowns; 551 }; 552 553 struct cxl_pmem_region_mapping { 554 struct cxl_memdev *cxlmd; 555 struct cxl_nvdimm *cxl_nvd; 556 u64 start; 557 u64 size; 558 int position; 559 }; 560 561 struct cxl_pmem_region { 562 struct device dev; 563 struct cxl_region *cxlr; 564 struct nd_region *nd_region; 565 struct range hpa_range; 566 int nr_mappings; 567 struct cxl_pmem_region_mapping mapping[]; 568 }; 569 570 struct cxl_dax_region { 571 struct device dev; 572 struct cxl_region *cxlr; 573 struct range hpa_range; 574 }; 575 576 /** 577 * struct cxl_port - logical collection of upstream port devices and 578 * downstream port devices to construct a CXL memory 579 * decode hierarchy. 580 * @dev: this port's device 581 * @uport_dev: PCI or platform device implementing the upstream port capability 582 * @host_bridge: Shortcut to the platform attach point for this port 583 * @id: id for port device-name 584 * @dports: cxl_dport instances referenced by decoders 585 * @endpoints: cxl_ep instances, endpoints that are a descendant of this port 586 * @regions: cxl_region_ref instances, regions mapped by this port 587 * @parent_dport: dport that points to this port in the parent 588 * @decoder_ida: allocator for decoder ids 589 * @reg_map: component and ras register mapping parameters 590 * @nr_dports: number of entries in @dports 591 * @hdm_end: track last allocated HDM decoder instance for allocation ordering 592 * @commit_end: cursor to track highest committed decoder for commit ordering 593 * @dead: last ep has been removed, force port re-creation 594 * @depth: How deep this port is relative to the root. depth 0 is the root. 595 * @cdat: Cached CDAT data 596 * @cdat_available: Should a CDAT attribute be available in sysfs 597 * @pci_latency: Upstream latency in picoseconds 598 */ 599 struct cxl_port { 600 struct device dev; 601 struct device *uport_dev; 602 struct device *host_bridge; 603 int id; 604 struct xarray dports; 605 struct xarray endpoints; 606 struct xarray regions; 607 struct cxl_dport *parent_dport; 608 struct ida decoder_ida; 609 struct cxl_register_map reg_map; 610 int nr_dports; 611 int hdm_end; 612 int commit_end; 613 bool dead; 614 unsigned int depth; 615 struct cxl_cdat { 616 void *table; 617 size_t length; 618 } cdat; 619 bool cdat_available; 620 long pci_latency; 621 }; 622 623 /** 624 * struct cxl_root - logical collection of root cxl_port items 625 * 626 * @port: cxl_port member 627 * @ops: cxl root operations 628 */ 629 struct cxl_root { 630 struct cxl_port port; 631 const struct cxl_root_ops *ops; 632 }; 633 634 static inline struct cxl_root * 635 to_cxl_root(const struct cxl_port *port) 636 { 637 return container_of(port, struct cxl_root, port); 638 } 639 640 struct cxl_root_ops { 641 int (*qos_class)(struct cxl_root *cxl_root, 642 struct access_coordinate *coord, int entries, 643 int *qos_class); 644 }; 645 646 static inline struct cxl_dport * 647 cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev) 648 { 649 return xa_load(&port->dports, (unsigned long)dport_dev); 650 } 651 652 struct cxl_rcrb_info { 653 resource_size_t base; 654 u16 aer_cap; 655 }; 656 657 /** 658 * struct cxl_dport - CXL downstream port 659 * @dport_dev: PCI bridge or firmware device representing the downstream link 660 * @reg_map: component and ras register mapping parameters 661 * @port_id: unique hardware identifier for dport in decoder target list 662 * @rcrb: Data about the Root Complex Register Block layout 663 * @rch: Indicate whether this dport was enumerated in RCH or VH mode 664 * @port: reference to cxl_port that contains this downstream port 665 * @regs: Dport parsed register blocks 666 * @coord: access coordinates (bandwidth and latency performance attributes) 667 * @link_latency: calculated PCIe downstream latency 668 * @gpf_dvsec: Cached GPF port DVSEC 669 */ 670 struct cxl_dport { 671 struct device *dport_dev; 672 struct cxl_register_map reg_map; 673 int port_id; 674 struct cxl_rcrb_info rcrb; 675 bool rch; 676 struct cxl_port *port; 677 struct cxl_regs regs; 678 struct access_coordinate coord[ACCESS_COORDINATE_MAX]; 679 long link_latency; 680 int gpf_dvsec; 681 }; 682 683 /** 684 * struct cxl_ep - track an endpoint's interest in a port 685 * @ep: device that hosts a generic CXL endpoint (expander or accelerator) 686 * @dport: which dport routes to this endpoint on @port 687 * @next: cxl switch port across the link attached to @dport NULL if 688 * attached to an endpoint 689 */ 690 struct cxl_ep { 691 struct device *ep; 692 struct cxl_dport *dport; 693 struct cxl_port *next; 694 }; 695 696 /** 697 * struct cxl_region_ref - track a region's interest in a port 698 * @port: point in topology to install this reference 699 * @decoder: decoder assigned for @region in @port 700 * @region: region for this reference 701 * @endpoints: cxl_ep references for region members beneath @port 702 * @nr_targets_set: track how many targets have been programmed during setup 703 * @nr_eps: number of endpoints beneath @port 704 * @nr_targets: number of distinct targets needed to reach @nr_eps 705 */ 706 struct cxl_region_ref { 707 struct cxl_port *port; 708 struct cxl_decoder *decoder; 709 struct cxl_region *region; 710 struct xarray endpoints; 711 int nr_targets_set; 712 int nr_eps; 713 int nr_targets; 714 }; 715 716 /* 717 * The platform firmware device hosting the root is also the top of the 718 * CXL port topology. All other CXL ports have another CXL port as their 719 * parent and their ->uport_dev / host device is out-of-line of the port 720 * ancestry. 721 */ 722 static inline bool is_cxl_root(struct cxl_port *port) 723 { 724 return port->uport_dev == port->dev.parent; 725 } 726 727 int cxl_num_decoders_committed(struct cxl_port *port); 728 bool is_cxl_port(const struct device *dev); 729 struct cxl_port *to_cxl_port(const struct device *dev); 730 struct cxl_port *parent_port_of(struct cxl_port *port); 731 void cxl_port_commit_reap(struct cxl_decoder *cxld); 732 struct pci_bus; 733 int devm_cxl_register_pci_bus(struct device *host, struct device *uport_dev, 734 struct pci_bus *bus); 735 struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port); 736 struct cxl_port *devm_cxl_add_port(struct device *host, 737 struct device *uport_dev, 738 resource_size_t component_reg_phys, 739 struct cxl_dport *parent_dport); 740 struct cxl_root *devm_cxl_add_root(struct device *host, 741 const struct cxl_root_ops *ops); 742 struct cxl_root *find_cxl_root(struct cxl_port *port); 743 744 DEFINE_FREE(put_cxl_root, struct cxl_root *, if (_T) put_device(&_T->port.dev)) 745 DEFINE_FREE(put_cxl_port, struct cxl_port *, if (!IS_ERR_OR_NULL(_T)) put_device(&_T->dev)) 746 DEFINE_FREE(put_cxl_root_decoder, struct cxl_root_decoder *, if (!IS_ERR_OR_NULL(_T)) put_device(&_T->cxlsd.cxld.dev)) 747 DEFINE_FREE(put_cxl_region, struct cxl_region *, if (!IS_ERR_OR_NULL(_T)) put_device(&_T->dev)) 748 749 int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); 750 void cxl_bus_rescan(void); 751 void cxl_bus_drain(void); 752 struct cxl_port *cxl_pci_find_port(struct pci_dev *pdev, 753 struct cxl_dport **dport); 754 struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd, 755 struct cxl_dport **dport); 756 bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd); 757 758 struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, 759 struct device *dport, int port_id, 760 resource_size_t component_reg_phys); 761 struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, 762 struct device *dport_dev, int port_id, 763 resource_size_t rcrb); 764 765 #ifdef CONFIG_PCIEAER_CXL 766 void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport); 767 void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host); 768 #else 769 static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport, 770 struct device *host) { } 771 #endif 772 773 struct cxl_decoder *to_cxl_decoder(struct device *dev); 774 struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev); 775 struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev); 776 struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev); 777 bool is_root_decoder(struct device *dev); 778 bool is_switch_decoder(struct device *dev); 779 bool is_endpoint_decoder(struct device *dev); 780 struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, 781 unsigned int nr_targets); 782 struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port, 783 unsigned int nr_targets); 784 int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map); 785 struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port); 786 int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map); 787 int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld); 788 static inline int cxl_root_decoder_autoremove(struct device *host, 789 struct cxl_root_decoder *cxlrd) 790 { 791 return cxl_decoder_autoremove(host, &cxlrd->cxlsd.cxld); 792 } 793 int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint); 794 795 /** 796 * struct cxl_endpoint_dvsec_info - Cached DVSEC info 797 * @mem_enabled: cached value of mem_enabled in the DVSEC at init time 798 * @ranges: Number of active HDM ranges this device uses. 799 * @port: endpoint port associated with this info instance 800 * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE 801 */ 802 struct cxl_endpoint_dvsec_info { 803 bool mem_enabled; 804 int ranges; 805 struct cxl_port *port; 806 struct range dvsec_range[2]; 807 }; 808 809 struct cxl_hdm; 810 struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port, 811 struct cxl_endpoint_dvsec_info *info); 812 int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm, 813 struct cxl_endpoint_dvsec_info *info); 814 int devm_cxl_add_passthrough_decoder(struct cxl_port *port); 815 struct cxl_dev_state; 816 int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds, 817 struct cxl_endpoint_dvsec_info *info); 818 819 bool is_cxl_region(struct device *dev); 820 821 extern const struct bus_type cxl_bus_type; 822 823 struct cxl_driver { 824 const char *name; 825 int (*probe)(struct device *dev); 826 void (*remove)(struct device *dev); 827 struct device_driver drv; 828 int id; 829 }; 830 831 #define to_cxl_drv(__drv) container_of_const(__drv, struct cxl_driver, drv) 832 833 int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner, 834 const char *modname); 835 #define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME) 836 void cxl_driver_unregister(struct cxl_driver *cxl_drv); 837 838 #define module_cxl_driver(__cxl_driver) \ 839 module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister) 840 841 #define CXL_DEVICE_NVDIMM_BRIDGE 1 842 #define CXL_DEVICE_NVDIMM 2 843 #define CXL_DEVICE_PORT 3 844 #define CXL_DEVICE_ROOT 4 845 #define CXL_DEVICE_MEMORY_EXPANDER 5 846 #define CXL_DEVICE_REGION 6 847 #define CXL_DEVICE_PMEM_REGION 7 848 #define CXL_DEVICE_DAX_REGION 8 849 #define CXL_DEVICE_PMU 9 850 851 #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*") 852 #define CXL_MODALIAS_FMT "cxl:t%d" 853 854 struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev); 855 struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host, 856 struct cxl_port *port); 857 struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev); 858 bool is_cxl_nvdimm(struct device *dev); 859 int devm_cxl_add_nvdimm(struct cxl_port *parent_port, struct cxl_memdev *cxlmd); 860 struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_port *port); 861 862 #ifdef CONFIG_CXL_REGION 863 bool is_cxl_pmem_region(struct device *dev); 864 struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev); 865 int cxl_add_to_region(struct cxl_endpoint_decoder *cxled); 866 struct cxl_dax_region *to_cxl_dax_region(struct device *dev); 867 u64 cxl_port_get_spa_cache_alias(struct cxl_port *endpoint, u64 spa); 868 #else 869 static inline bool is_cxl_pmem_region(struct device *dev) 870 { 871 return false; 872 } 873 static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev) 874 { 875 return NULL; 876 } 877 static inline int cxl_add_to_region(struct cxl_endpoint_decoder *cxled) 878 { 879 return 0; 880 } 881 static inline struct cxl_dax_region *to_cxl_dax_region(struct device *dev) 882 { 883 return NULL; 884 } 885 static inline u64 cxl_port_get_spa_cache_alias(struct cxl_port *endpoint, 886 u64 spa) 887 { 888 return 0; 889 } 890 #endif 891 892 void cxl_endpoint_parse_cdat(struct cxl_port *port); 893 void cxl_switch_parse_cdat(struct cxl_port *port); 894 895 int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, 896 struct access_coordinate *coord); 897 void cxl_region_perf_data_calculate(struct cxl_region *cxlr, 898 struct cxl_endpoint_decoder *cxled); 899 void cxl_region_shared_upstream_bandwidth_update(struct cxl_region *cxlr); 900 901 void cxl_memdev_update_perf(struct cxl_memdev *cxlmd); 902 903 void cxl_coordinates_combine(struct access_coordinate *out, 904 struct access_coordinate *c1, 905 struct access_coordinate *c2); 906 907 bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port); 908 909 /* 910 * Unit test builds overrides this to __weak, find the 'strong' version 911 * of these symbols in tools/testing/cxl/. 912 */ 913 #ifndef __mock 914 #define __mock static 915 #endif 916 917 u16 cxl_gpf_get_dvsec(struct device *dev); 918 #endif /* __CXL_H__ */ 919