1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020 Intel Corporation. */ 3 4 #ifndef __CXL_H__ 5 #define __CXL_H__ 6 7 #include <linux/libnvdimm.h> 8 #include <linux/bitfield.h> 9 #include <linux/bitops.h> 10 #include <linux/log2.h> 11 #include <linux/io.h> 12 13 /** 14 * DOC: cxl objects 15 * 16 * The CXL core objects like ports, decoders, and regions are shared 17 * between the subsystem drivers cxl_acpi, cxl_pci, and core drivers 18 * (port-driver, region-driver, nvdimm object-drivers... etc). 19 */ 20 21 /* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */ 22 #define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K 23 24 /* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/ 25 #define CXL_CM_OFFSET 0x1000 26 #define CXL_CM_CAP_HDR_OFFSET 0x0 27 #define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0) 28 #define CM_CAP_HDR_CAP_ID 1 29 #define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16) 30 #define CM_CAP_HDR_CAP_VERSION 1 31 #define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20) 32 #define CM_CAP_HDR_CACHE_MEM_VERSION 1 33 #define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24) 34 #define CXL_CM_CAP_PTR_MASK GENMASK(31, 20) 35 36 #define CXL_CM_CAP_CAP_ID_RAS 0x2 37 #define CXL_CM_CAP_CAP_ID_HDM 0x5 38 #define CXL_CM_CAP_CAP_HDM_VERSION 1 39 40 /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */ 41 #define CXL_HDM_DECODER_CAP_OFFSET 0x0 42 #define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0) 43 #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4) 44 #define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8) 45 #define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9) 46 #define CXL_HDM_DECODER_CTRL_OFFSET 0x4 47 #define CXL_HDM_DECODER_ENABLE BIT(1) 48 #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10) 49 #define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14) 50 #define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18) 51 #define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c) 52 #define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20) 53 #define CXL_HDM_DECODER0_CTRL_IG_MASK GENMASK(3, 0) 54 #define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4) 55 #define CXL_HDM_DECODER0_CTRL_LOCK BIT(8) 56 #define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9) 57 #define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10) 58 #define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11) 59 #define CXL_HDM_DECODER0_CTRL_HOSTONLY BIT(12) 60 #define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24) 61 #define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28) 62 #define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i) 63 #define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i) 64 65 /* HDM decoder control register constants CXL 3.0 8.2.5.19.7 */ 66 #define CXL_DECODER_MIN_GRANULARITY 256 67 #define CXL_DECODER_MAX_ENCODED_IG 6 68 69 static inline int cxl_hdm_decoder_count(u32 cap_hdr) 70 { 71 int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr); 72 73 return val ? val * 2 : 1; 74 } 75 76 /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ 77 static inline int eig_to_granularity(u16 eig, unsigned int *granularity) 78 { 79 if (eig > CXL_DECODER_MAX_ENCODED_IG) 80 return -EINVAL; 81 *granularity = CXL_DECODER_MIN_GRANULARITY << eig; 82 return 0; 83 } 84 85 /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */ 86 static inline int eiw_to_ways(u8 eiw, unsigned int *ways) 87 { 88 switch (eiw) { 89 case 0 ... 4: 90 *ways = 1 << eiw; 91 break; 92 case 8 ... 10: 93 *ways = 3 << (eiw - 8); 94 break; 95 default: 96 return -EINVAL; 97 } 98 99 return 0; 100 } 101 102 static inline int granularity_to_eig(int granularity, u16 *eig) 103 { 104 if (granularity > SZ_16K || granularity < CXL_DECODER_MIN_GRANULARITY || 105 !is_power_of_2(granularity)) 106 return -EINVAL; 107 *eig = ilog2(granularity) - 8; 108 return 0; 109 } 110 111 static inline int ways_to_eiw(unsigned int ways, u8 *eiw) 112 { 113 if (ways > 16) 114 return -EINVAL; 115 if (is_power_of_2(ways)) { 116 *eiw = ilog2(ways); 117 return 0; 118 } 119 if (ways % 3) 120 return -EINVAL; 121 ways /= 3; 122 if (!is_power_of_2(ways)) 123 return -EINVAL; 124 *eiw = ilog2(ways) + 8; 125 return 0; 126 } 127 128 /* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */ 129 #define CXL_RAS_UNCORRECTABLE_STATUS_OFFSET 0x0 130 #define CXL_RAS_UNCORRECTABLE_STATUS_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 131 #define CXL_RAS_UNCORRECTABLE_MASK_OFFSET 0x4 132 #define CXL_RAS_UNCORRECTABLE_MASK_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 133 #define CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK BIT(8) 134 #define CXL_RAS_UNCORRECTABLE_SEVERITY_OFFSET 0x8 135 #define CXL_RAS_UNCORRECTABLE_SEVERITY_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 136 #define CXL_RAS_CORRECTABLE_STATUS_OFFSET 0xC 137 #define CXL_RAS_CORRECTABLE_STATUS_MASK GENMASK(6, 0) 138 #define CXL_RAS_CORRECTABLE_MASK_OFFSET 0x10 139 #define CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0) 140 #define CXL_RAS_CAP_CONTROL_OFFSET 0x14 141 #define CXL_RAS_CAP_CONTROL_FE_MASK GENMASK(5, 0) 142 #define CXL_RAS_HEADER_LOG_OFFSET 0x18 143 #define CXL_RAS_CAPABILITY_LENGTH 0x58 144 #define CXL_HEADERLOG_SIZE SZ_512 145 #define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32) 146 147 /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ 148 #define CXLDEV_CAP_ARRAY_OFFSET 0x0 149 #define CXLDEV_CAP_ARRAY_CAP_ID 0 150 #define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0) 151 #define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32) 152 /* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */ 153 #define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0) 154 /* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */ 155 #define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1 156 #define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2 157 #define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3 158 #define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000 159 160 /* CXL 3.0 8.2.8.3.1 Event Status Register */ 161 #define CXLDEV_DEV_EVENT_STATUS_OFFSET 0x00 162 #define CXLDEV_EVENT_STATUS_INFO BIT(0) 163 #define CXLDEV_EVENT_STATUS_WARN BIT(1) 164 #define CXLDEV_EVENT_STATUS_FAIL BIT(2) 165 #define CXLDEV_EVENT_STATUS_FATAL BIT(3) 166 167 #define CXLDEV_EVENT_STATUS_ALL (CXLDEV_EVENT_STATUS_INFO | \ 168 CXLDEV_EVENT_STATUS_WARN | \ 169 CXLDEV_EVENT_STATUS_FAIL | \ 170 CXLDEV_EVENT_STATUS_FATAL) 171 172 /* CXL rev 3.0 section 8.2.9.2.4; Table 8-52 */ 173 #define CXLDEV_EVENT_INT_MODE_MASK GENMASK(1, 0) 174 #define CXLDEV_EVENT_INT_MSGNUM_MASK GENMASK(7, 4) 175 176 /* CXL 2.0 8.2.8.4 Mailbox Registers */ 177 #define CXLDEV_MBOX_CAPS_OFFSET 0x00 178 #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0) 179 #define CXLDEV_MBOX_CAP_BG_CMD_IRQ BIT(6) 180 #define CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK GENMASK(10, 7) 181 #define CXLDEV_MBOX_CTRL_OFFSET 0x04 182 #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0) 183 #define CXLDEV_MBOX_CTRL_BG_CMD_IRQ BIT(2) 184 #define CXLDEV_MBOX_CMD_OFFSET 0x08 185 #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) 186 #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16) 187 #define CXLDEV_MBOX_STATUS_OFFSET 0x10 188 #define CXLDEV_MBOX_STATUS_BG_CMD BIT(0) 189 #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32) 190 #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18 191 #define CXLDEV_MBOX_BG_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) 192 #define CXLDEV_MBOX_BG_CMD_COMMAND_PCT_MASK GENMASK_ULL(22, 16) 193 #define CXLDEV_MBOX_BG_CMD_COMMAND_RC_MASK GENMASK_ULL(47, 32) 194 #define CXLDEV_MBOX_BG_CMD_COMMAND_VENDOR_MASK GENMASK_ULL(63, 48) 195 #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20 196 197 /* 198 * Using struct_group() allows for per register-block-type helper routines, 199 * without requiring block-type agnostic code to include the prefix. 200 */ 201 struct cxl_regs { 202 /* 203 * Common set of CXL Component register block base pointers 204 * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure 205 * @ras: CXL 2.0 8.2.5.9 CXL RAS Capability Structure 206 */ 207 struct_group_tagged(cxl_component_regs, component, 208 void __iomem *hdm_decoder; 209 void __iomem *ras; 210 ); 211 /* 212 * Common set of CXL Device register block base pointers 213 * @status: CXL 2.0 8.2.8.3 Device Status Registers 214 * @mbox: CXL 2.0 8.2.8.4 Mailbox Registers 215 * @memdev: CXL 2.0 8.2.8.5 Memory Device Registers 216 */ 217 struct_group_tagged(cxl_device_regs, device_regs, 218 void __iomem *status, *mbox, *memdev; 219 ); 220 221 struct_group_tagged(cxl_pmu_regs, pmu_regs, 222 void __iomem *pmu; 223 ); 224 225 /* 226 * RCH downstream port specific RAS register 227 * @aer: CXL 3.0 8.2.1.1 RCH Downstream Port RCRB 228 */ 229 struct_group_tagged(cxl_rch_regs, rch_regs, 230 void __iomem *dport_aer; 231 ); 232 }; 233 234 struct cxl_reg_map { 235 bool valid; 236 int id; 237 unsigned long offset; 238 unsigned long size; 239 }; 240 241 struct cxl_component_reg_map { 242 struct cxl_reg_map hdm_decoder; 243 struct cxl_reg_map ras; 244 }; 245 246 struct cxl_device_reg_map { 247 struct cxl_reg_map status; 248 struct cxl_reg_map mbox; 249 struct cxl_reg_map memdev; 250 }; 251 252 struct cxl_pmu_reg_map { 253 struct cxl_reg_map pmu; 254 }; 255 256 /** 257 * struct cxl_register_map - DVSEC harvested register block mapping parameters 258 * @host: device for devm operations and logging 259 * @base: virtual base of the register-block-BAR + @block_offset 260 * @resource: physical resource base of the register block 261 * @max_size: maximum mapping size to perform register search 262 * @reg_type: see enum cxl_regloc_type 263 * @component_map: cxl_reg_map for component registers 264 * @device_map: cxl_reg_maps for device registers 265 * @pmu_map: cxl_reg_maps for CXL Performance Monitoring Units 266 */ 267 struct cxl_register_map { 268 struct device *host; 269 void __iomem *base; 270 resource_size_t resource; 271 resource_size_t max_size; 272 u8 reg_type; 273 union { 274 struct cxl_component_reg_map component_map; 275 struct cxl_device_reg_map device_map; 276 struct cxl_pmu_reg_map pmu_map; 277 }; 278 }; 279 280 void cxl_probe_component_regs(struct device *dev, void __iomem *base, 281 struct cxl_component_reg_map *map); 282 void cxl_probe_device_regs(struct device *dev, void __iomem *base, 283 struct cxl_device_reg_map *map); 284 int cxl_map_component_regs(const struct cxl_register_map *map, 285 struct cxl_component_regs *regs, 286 unsigned long map_mask); 287 int cxl_map_device_regs(const struct cxl_register_map *map, 288 struct cxl_device_regs *regs); 289 int cxl_map_pmu_regs(struct cxl_register_map *map, struct cxl_pmu_regs *regs); 290 291 enum cxl_regloc_type; 292 int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type); 293 int cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type, 294 struct cxl_register_map *map, int index); 295 int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, 296 struct cxl_register_map *map); 297 int cxl_setup_regs(struct cxl_register_map *map); 298 struct cxl_dport; 299 resource_size_t cxl_rcd_component_reg_phys(struct device *dev, 300 struct cxl_dport *dport); 301 302 #define CXL_RESOURCE_NONE ((resource_size_t) -1) 303 #define CXL_TARGET_STRLEN 20 304 305 /* 306 * cxl_decoder flags that define the type of memory / devices this 307 * decoder supports as well as configuration lock status See "CXL 2.0 308 * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details. 309 * Additionally indicate whether decoder settings were autodetected, 310 * user customized. 311 */ 312 #define CXL_DECODER_F_RAM BIT(0) 313 #define CXL_DECODER_F_PMEM BIT(1) 314 #define CXL_DECODER_F_TYPE2 BIT(2) 315 #define CXL_DECODER_F_TYPE3 BIT(3) 316 #define CXL_DECODER_F_LOCK BIT(4) 317 #define CXL_DECODER_F_ENABLE BIT(5) 318 #define CXL_DECODER_F_MASK GENMASK(5, 0) 319 320 enum cxl_decoder_type { 321 CXL_DECODER_DEVMEM = 2, 322 CXL_DECODER_HOSTONLYMEM = 3, 323 }; 324 325 /* 326 * Current specification goes up to 8, double that seems a reasonable 327 * software max for the foreseeable future 328 */ 329 #define CXL_DECODER_MAX_INTERLEAVE 16 330 331 #define CXL_QOS_CLASS_INVALID -1 332 333 /** 334 * struct cxl_decoder - Common CXL HDM Decoder Attributes 335 * @dev: this decoder's device 336 * @id: kernel device name id 337 * @hpa_range: Host physical address range mapped by this decoder 338 * @interleave_ways: number of cxl_dports in this decode 339 * @interleave_granularity: data stride per dport 340 * @target_type: accelerator vs expander (type2 vs type3) selector 341 * @region: currently assigned region for this decoder 342 * @flags: memory type capabilities and locking 343 * @commit: device/decoder-type specific callback to commit settings to hw 344 * @reset: device/decoder-type specific callback to reset hw settings 345 */ 346 struct cxl_decoder { 347 struct device dev; 348 int id; 349 struct range hpa_range; 350 int interleave_ways; 351 int interleave_granularity; 352 enum cxl_decoder_type target_type; 353 struct cxl_region *region; 354 unsigned long flags; 355 int (*commit)(struct cxl_decoder *cxld); 356 int (*reset)(struct cxl_decoder *cxld); 357 }; 358 359 /* 360 * CXL_DECODER_DEAD prevents endpoints from being reattached to regions 361 * while cxld_unregister() is running 362 */ 363 enum cxl_decoder_mode { 364 CXL_DECODER_NONE, 365 CXL_DECODER_RAM, 366 CXL_DECODER_PMEM, 367 CXL_DECODER_MIXED, 368 CXL_DECODER_DEAD, 369 }; 370 371 static inline const char *cxl_decoder_mode_name(enum cxl_decoder_mode mode) 372 { 373 static const char * const names[] = { 374 [CXL_DECODER_NONE] = "none", 375 [CXL_DECODER_RAM] = "ram", 376 [CXL_DECODER_PMEM] = "pmem", 377 [CXL_DECODER_MIXED] = "mixed", 378 }; 379 380 if (mode >= CXL_DECODER_NONE && mode <= CXL_DECODER_MIXED) 381 return names[mode]; 382 return "mixed"; 383 } 384 385 /* 386 * Track whether this decoder is reserved for region autodiscovery, or 387 * free for userspace provisioning. 388 */ 389 enum cxl_decoder_state { 390 CXL_DECODER_STATE_MANUAL, 391 CXL_DECODER_STATE_AUTO, 392 }; 393 394 /** 395 * struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder 396 * @cxld: base cxl_decoder_object 397 * @dpa_res: actively claimed DPA span of this decoder 398 * @skip: offset into @dpa_res where @cxld.hpa_range maps 399 * @mode: which memory type / access-mode-partition this decoder targets 400 * @state: autodiscovery state 401 * @pos: interleave position in @cxld.region 402 */ 403 struct cxl_endpoint_decoder { 404 struct cxl_decoder cxld; 405 struct resource *dpa_res; 406 resource_size_t skip; 407 enum cxl_decoder_mode mode; 408 enum cxl_decoder_state state; 409 int pos; 410 }; 411 412 /** 413 * struct cxl_switch_decoder - Switch specific CXL HDM Decoder 414 * @cxld: base cxl_decoder object 415 * @target_lock: coordinate coherent reads of the target list 416 * @nr_targets: number of elements in @target 417 * @target: active ordered target list in current decoder configuration 418 * 419 * The 'switch' decoder type represents the decoder instances of cxl_port's that 420 * route from the root of a CXL memory decode topology to the endpoints. They 421 * come in two flavors, root-level decoders, statically defined by platform 422 * firmware, and mid-level decoders, where interleave-granularity, 423 * interleave-width, and the target list are mutable. 424 */ 425 struct cxl_switch_decoder { 426 struct cxl_decoder cxld; 427 seqlock_t target_lock; 428 int nr_targets; 429 struct cxl_dport *target[]; 430 }; 431 432 struct cxl_root_decoder; 433 typedef struct cxl_dport *(*cxl_calc_hb_fn)(struct cxl_root_decoder *cxlrd, 434 int pos); 435 436 /** 437 * struct cxl_root_decoder - Static platform CXL address decoder 438 * @res: host / parent resource for region allocations 439 * @region_id: region id for next region provisioning event 440 * @calc_hb: which host bridge covers the n'th position by granularity 441 * @platform_data: platform specific configuration data 442 * @range_lock: sync region autodiscovery by address range 443 * @qos_class: QoS performance class cookie 444 * @cxlsd: base cxl switch decoder 445 */ 446 struct cxl_root_decoder { 447 struct resource *res; 448 atomic_t region_id; 449 cxl_calc_hb_fn calc_hb; 450 void *platform_data; 451 struct mutex range_lock; 452 int qos_class; 453 struct cxl_switch_decoder cxlsd; 454 }; 455 456 /* 457 * enum cxl_config_state - State machine for region configuration 458 * @CXL_CONFIG_IDLE: Any sysfs attribute can be written freely 459 * @CXL_CONFIG_INTERLEAVE_ACTIVE: region size has been set, no more 460 * changes to interleave_ways or interleave_granularity 461 * @CXL_CONFIG_ACTIVE: All targets have been added the region is now 462 * active 463 * @CXL_CONFIG_RESET_PENDING: see commit_store() 464 * @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware 465 */ 466 enum cxl_config_state { 467 CXL_CONFIG_IDLE, 468 CXL_CONFIG_INTERLEAVE_ACTIVE, 469 CXL_CONFIG_ACTIVE, 470 CXL_CONFIG_RESET_PENDING, 471 CXL_CONFIG_COMMIT, 472 }; 473 474 /** 475 * struct cxl_region_params - region settings 476 * @state: allow the driver to lockdown further parameter changes 477 * @uuid: unique id for persistent regions 478 * @interleave_ways: number of endpoints in the region 479 * @interleave_granularity: capacity each endpoint contributes to a stripe 480 * @res: allocated iomem capacity for this region 481 * @targets: active ordered targets in current decoder configuration 482 * @nr_targets: number of targets 483 * 484 * State transitions are protected by the cxl_region_rwsem 485 */ 486 struct cxl_region_params { 487 enum cxl_config_state state; 488 uuid_t uuid; 489 int interleave_ways; 490 int interleave_granularity; 491 struct resource *res; 492 struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE]; 493 int nr_targets; 494 }; 495 496 /* 497 * Indicate whether this region has been assembled by autodetection or 498 * userspace assembly. Prevent endpoint decoders outside of automatic 499 * detection from being added to the region. 500 */ 501 #define CXL_REGION_F_AUTO 0 502 503 /* 504 * Require that a committed region successfully complete a teardown once 505 * any of its associated decoders have been torn down. This maintains 506 * the commit state for the region since there are committed decoders, 507 * but blocks cxl_region_probe(). 508 */ 509 #define CXL_REGION_F_NEEDS_RESET 1 510 511 /** 512 * struct cxl_region - CXL region 513 * @dev: This region's device 514 * @id: This region's id. Id is globally unique across all regions 515 * @mode: Endpoint decoder allocation / access mode 516 * @type: Endpoint decoder target type 517 * @cxl_nvb: nvdimm bridge for coordinating @cxlr_pmem setup / shutdown 518 * @cxlr_pmem: (for pmem regions) cached copy of the nvdimm bridge 519 * @flags: Region state flags 520 * @params: active + config params for the region 521 */ 522 struct cxl_region { 523 struct device dev; 524 int id; 525 enum cxl_decoder_mode mode; 526 enum cxl_decoder_type type; 527 struct cxl_nvdimm_bridge *cxl_nvb; 528 struct cxl_pmem_region *cxlr_pmem; 529 unsigned long flags; 530 struct cxl_region_params params; 531 }; 532 533 struct cxl_nvdimm_bridge { 534 int id; 535 struct device dev; 536 struct cxl_port *port; 537 struct nvdimm_bus *nvdimm_bus; 538 struct nvdimm_bus_descriptor nd_desc; 539 }; 540 541 #define CXL_DEV_ID_LEN 19 542 543 struct cxl_nvdimm { 544 struct device dev; 545 struct cxl_memdev *cxlmd; 546 u8 dev_id[CXL_DEV_ID_LEN]; /* for nvdimm, string of 'serial' */ 547 }; 548 549 struct cxl_pmem_region_mapping { 550 struct cxl_memdev *cxlmd; 551 struct cxl_nvdimm *cxl_nvd; 552 u64 start; 553 u64 size; 554 int position; 555 }; 556 557 struct cxl_pmem_region { 558 struct device dev; 559 struct cxl_region *cxlr; 560 struct nd_region *nd_region; 561 struct range hpa_range; 562 int nr_mappings; 563 struct cxl_pmem_region_mapping mapping[]; 564 }; 565 566 struct cxl_dax_region { 567 struct device dev; 568 struct cxl_region *cxlr; 569 struct range hpa_range; 570 }; 571 572 /** 573 * struct cxl_port - logical collection of upstream port devices and 574 * downstream port devices to construct a CXL memory 575 * decode hierarchy. 576 * @dev: this port's device 577 * @uport_dev: PCI or platform device implementing the upstream port capability 578 * @host_bridge: Shortcut to the platform attach point for this port 579 * @id: id for port device-name 580 * @dports: cxl_dport instances referenced by decoders 581 * @endpoints: cxl_ep instances, endpoints that are a descendant of this port 582 * @regions: cxl_region_ref instances, regions mapped by this port 583 * @parent_dport: dport that points to this port in the parent 584 * @decoder_ida: allocator for decoder ids 585 * @reg_map: component and ras register mapping parameters 586 * @nr_dports: number of entries in @dports 587 * @hdm_end: track last allocated HDM decoder instance for allocation ordering 588 * @commit_end: cursor to track highest committed decoder for commit ordering 589 * @dead: last ep has been removed, force port re-creation 590 * @depth: How deep this port is relative to the root. depth 0 is the root. 591 * @cdat: Cached CDAT data 592 * @cdat_available: Should a CDAT attribute be available in sysfs 593 */ 594 struct cxl_port { 595 struct device dev; 596 struct device *uport_dev; 597 struct device *host_bridge; 598 int id; 599 struct xarray dports; 600 struct xarray endpoints; 601 struct xarray regions; 602 struct cxl_dport *parent_dport; 603 struct ida decoder_ida; 604 struct cxl_register_map reg_map; 605 int nr_dports; 606 int hdm_end; 607 int commit_end; 608 bool dead; 609 unsigned int depth; 610 struct cxl_cdat { 611 void *table; 612 size_t length; 613 } cdat; 614 bool cdat_available; 615 }; 616 617 static inline struct cxl_dport * 618 cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev) 619 { 620 return xa_load(&port->dports, (unsigned long)dport_dev); 621 } 622 623 struct cxl_rcrb_info { 624 resource_size_t base; 625 u16 aer_cap; 626 }; 627 628 /** 629 * struct cxl_dport - CXL downstream port 630 * @dport_dev: PCI bridge or firmware device representing the downstream link 631 * @reg_map: component and ras register mapping parameters 632 * @port_id: unique hardware identifier for dport in decoder target list 633 * @rcrb: Data about the Root Complex Register Block layout 634 * @rch: Indicate whether this dport was enumerated in RCH or VH mode 635 * @port: reference to cxl_port that contains this downstream port 636 * @regs: Dport parsed register blocks 637 */ 638 struct cxl_dport { 639 struct device *dport_dev; 640 struct cxl_register_map reg_map; 641 int port_id; 642 struct cxl_rcrb_info rcrb; 643 bool rch; 644 struct cxl_port *port; 645 struct cxl_regs regs; 646 }; 647 648 /** 649 * struct cxl_ep - track an endpoint's interest in a port 650 * @ep: device that hosts a generic CXL endpoint (expander or accelerator) 651 * @dport: which dport routes to this endpoint on @port 652 * @next: cxl switch port across the link attached to @dport NULL if 653 * attached to an endpoint 654 */ 655 struct cxl_ep { 656 struct device *ep; 657 struct cxl_dport *dport; 658 struct cxl_port *next; 659 }; 660 661 /** 662 * struct cxl_region_ref - track a region's interest in a port 663 * @port: point in topology to install this reference 664 * @decoder: decoder assigned for @region in @port 665 * @region: region for this reference 666 * @endpoints: cxl_ep references for region members beneath @port 667 * @nr_targets_set: track how many targets have been programmed during setup 668 * @nr_eps: number of endpoints beneath @port 669 * @nr_targets: number of distinct targets needed to reach @nr_eps 670 */ 671 struct cxl_region_ref { 672 struct cxl_port *port; 673 struct cxl_decoder *decoder; 674 struct cxl_region *region; 675 struct xarray endpoints; 676 int nr_targets_set; 677 int nr_eps; 678 int nr_targets; 679 }; 680 681 /* 682 * The platform firmware device hosting the root is also the top of the 683 * CXL port topology. All other CXL ports have another CXL port as their 684 * parent and their ->uport_dev / host device is out-of-line of the port 685 * ancestry. 686 */ 687 static inline bool is_cxl_root(struct cxl_port *port) 688 { 689 return port->uport_dev == port->dev.parent; 690 } 691 692 int cxl_num_decoders_committed(struct cxl_port *port); 693 bool is_cxl_port(const struct device *dev); 694 struct cxl_port *to_cxl_port(const struct device *dev); 695 struct pci_bus; 696 int devm_cxl_register_pci_bus(struct device *host, struct device *uport_dev, 697 struct pci_bus *bus); 698 struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port); 699 struct cxl_port *devm_cxl_add_port(struct device *host, 700 struct device *uport_dev, 701 resource_size_t component_reg_phys, 702 struct cxl_dport *parent_dport); 703 struct cxl_port *find_cxl_root(struct cxl_port *port); 704 int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); 705 void cxl_bus_rescan(void); 706 void cxl_bus_drain(void); 707 struct cxl_port *cxl_pci_find_port(struct pci_dev *pdev, 708 struct cxl_dport **dport); 709 struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd, 710 struct cxl_dport **dport); 711 bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd); 712 713 struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, 714 struct device *dport, int port_id, 715 resource_size_t component_reg_phys); 716 struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, 717 struct device *dport_dev, int port_id, 718 resource_size_t rcrb); 719 720 #ifdef CONFIG_PCIEAER_CXL 721 void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport); 722 #else 723 static inline void cxl_setup_parent_dport(struct device *host, 724 struct cxl_dport *dport) { } 725 #endif 726 727 struct cxl_decoder *to_cxl_decoder(struct device *dev); 728 struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev); 729 struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev); 730 struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev); 731 bool is_root_decoder(struct device *dev); 732 bool is_switch_decoder(struct device *dev); 733 bool is_endpoint_decoder(struct device *dev); 734 struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, 735 unsigned int nr_targets, 736 cxl_calc_hb_fn calc_hb); 737 struct cxl_dport *cxl_hb_modulo(struct cxl_root_decoder *cxlrd, int pos); 738 struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port, 739 unsigned int nr_targets); 740 int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map); 741 struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port); 742 int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map); 743 int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld); 744 int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint); 745 746 /** 747 * struct cxl_endpoint_dvsec_info - Cached DVSEC info 748 * @mem_enabled: cached value of mem_enabled in the DVSEC at init time 749 * @ranges: Number of active HDM ranges this device uses. 750 * @port: endpoint port associated with this info instance 751 * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE 752 */ 753 struct cxl_endpoint_dvsec_info { 754 bool mem_enabled; 755 int ranges; 756 struct cxl_port *port; 757 struct range dvsec_range[2]; 758 }; 759 760 struct cxl_hdm; 761 struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port, 762 struct cxl_endpoint_dvsec_info *info); 763 int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm, 764 struct cxl_endpoint_dvsec_info *info); 765 int devm_cxl_add_passthrough_decoder(struct cxl_port *port); 766 int cxl_dvsec_rr_decode(struct device *dev, int dvsec, 767 struct cxl_endpoint_dvsec_info *info); 768 769 bool is_cxl_region(struct device *dev); 770 771 extern struct bus_type cxl_bus_type; 772 773 struct cxl_driver { 774 const char *name; 775 int (*probe)(struct device *dev); 776 void (*remove)(struct device *dev); 777 struct device_driver drv; 778 int id; 779 }; 780 781 static inline struct cxl_driver *to_cxl_drv(struct device_driver *drv) 782 { 783 return container_of(drv, struct cxl_driver, drv); 784 } 785 786 int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner, 787 const char *modname); 788 #define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME) 789 void cxl_driver_unregister(struct cxl_driver *cxl_drv); 790 791 #define module_cxl_driver(__cxl_driver) \ 792 module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister) 793 794 #define CXL_DEVICE_NVDIMM_BRIDGE 1 795 #define CXL_DEVICE_NVDIMM 2 796 #define CXL_DEVICE_PORT 3 797 #define CXL_DEVICE_ROOT 4 798 #define CXL_DEVICE_MEMORY_EXPANDER 5 799 #define CXL_DEVICE_REGION 6 800 #define CXL_DEVICE_PMEM_REGION 7 801 #define CXL_DEVICE_DAX_REGION 8 802 #define CXL_DEVICE_PMU 9 803 804 #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*") 805 #define CXL_MODALIAS_FMT "cxl:t%d" 806 807 struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev); 808 struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host, 809 struct cxl_port *port); 810 struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev); 811 bool is_cxl_nvdimm(struct device *dev); 812 bool is_cxl_nvdimm_bridge(struct device *dev); 813 int devm_cxl_add_nvdimm(struct cxl_memdev *cxlmd); 814 struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd); 815 816 #ifdef CONFIG_CXL_REGION 817 bool is_cxl_pmem_region(struct device *dev); 818 struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev); 819 int cxl_add_to_region(struct cxl_port *root, 820 struct cxl_endpoint_decoder *cxled); 821 struct cxl_dax_region *to_cxl_dax_region(struct device *dev); 822 #else 823 static inline bool is_cxl_pmem_region(struct device *dev) 824 { 825 return false; 826 } 827 static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev) 828 { 829 return NULL; 830 } 831 static inline int cxl_add_to_region(struct cxl_port *root, 832 struct cxl_endpoint_decoder *cxled) 833 { 834 return 0; 835 } 836 static inline struct cxl_dax_region *to_cxl_dax_region(struct device *dev) 837 { 838 return NULL; 839 } 840 #endif 841 842 /* 843 * Unit test builds overrides this to __weak, find the 'strong' version 844 * of these symbols in tools/testing/cxl/. 845 */ 846 #ifndef __mock 847 #define __mock static 848 #endif 849 850 #endif /* __CXL_H__ */ 851