1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020 Intel Corporation. */ 3 4 #ifndef __CXL_H__ 5 #define __CXL_H__ 6 7 #include <linux/libnvdimm.h> 8 #include <linux/bitfield.h> 9 #include <linux/notifier.h> 10 #include <linux/bitops.h> 11 #include <linux/log2.h> 12 #include <linux/node.h> 13 #include <linux/io.h> 14 15 extern const struct nvdimm_security_ops *cxl_security_ops; 16 17 /** 18 * DOC: cxl objects 19 * 20 * The CXL core objects like ports, decoders, and regions are shared 21 * between the subsystem drivers cxl_acpi, cxl_pci, and core drivers 22 * (port-driver, region-driver, nvdimm object-drivers... etc). 23 */ 24 25 /* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */ 26 #define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K 27 28 /* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/ 29 #define CXL_CM_OFFSET 0x1000 30 #define CXL_CM_CAP_HDR_OFFSET 0x0 31 #define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0) 32 #define CM_CAP_HDR_CAP_ID 1 33 #define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16) 34 #define CM_CAP_HDR_CAP_VERSION 1 35 #define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20) 36 #define CM_CAP_HDR_CACHE_MEM_VERSION 1 37 #define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24) 38 #define CXL_CM_CAP_PTR_MASK GENMASK(31, 20) 39 40 #define CXL_CM_CAP_CAP_ID_RAS 0x2 41 #define CXL_CM_CAP_CAP_ID_HDM 0x5 42 #define CXL_CM_CAP_CAP_HDM_VERSION 1 43 44 /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */ 45 #define CXL_HDM_DECODER_CAP_OFFSET 0x0 46 #define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0) 47 #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4) 48 #define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8) 49 #define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9) 50 #define CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY BIT(11) 51 #define CXL_HDM_DECODER_INTERLEAVE_16_WAY BIT(12) 52 #define CXL_HDM_DECODER_CTRL_OFFSET 0x4 53 #define CXL_HDM_DECODER_ENABLE BIT(1) 54 #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10) 55 #define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14) 56 #define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18) 57 #define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c) 58 #define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20) 59 #define CXL_HDM_DECODER0_CTRL_IG_MASK GENMASK(3, 0) 60 #define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4) 61 #define CXL_HDM_DECODER0_CTRL_LOCK BIT(8) 62 #define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9) 63 #define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10) 64 #define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11) 65 #define CXL_HDM_DECODER0_CTRL_HOSTONLY BIT(12) 66 #define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24) 67 #define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28) 68 #define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i) 69 #define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i) 70 71 /* HDM decoder control register constants CXL 3.0 8.2.5.19.7 */ 72 #define CXL_DECODER_MIN_GRANULARITY 256 73 #define CXL_DECODER_MAX_ENCODED_IG 6 74 75 static inline int cxl_hdm_decoder_count(u32 cap_hdr) 76 { 77 int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr); 78 79 return val ? val * 2 : 1; 80 } 81 82 /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ 83 static inline int eig_to_granularity(u16 eig, unsigned int *granularity) 84 { 85 if (eig > CXL_DECODER_MAX_ENCODED_IG) 86 return -EINVAL; 87 *granularity = CXL_DECODER_MIN_GRANULARITY << eig; 88 return 0; 89 } 90 91 /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */ 92 static inline int eiw_to_ways(u8 eiw, unsigned int *ways) 93 { 94 switch (eiw) { 95 case 0 ... 4: 96 *ways = 1 << eiw; 97 break; 98 case 8 ... 10: 99 *ways = 3 << (eiw - 8); 100 break; 101 default: 102 return -EINVAL; 103 } 104 105 return 0; 106 } 107 108 static inline int granularity_to_eig(int granularity, u16 *eig) 109 { 110 if (granularity > SZ_16K || granularity < CXL_DECODER_MIN_GRANULARITY || 111 !is_power_of_2(granularity)) 112 return -EINVAL; 113 *eig = ilog2(granularity) - 8; 114 return 0; 115 } 116 117 static inline int ways_to_eiw(unsigned int ways, u8 *eiw) 118 { 119 if (ways > 16) 120 return -EINVAL; 121 if (is_power_of_2(ways)) { 122 *eiw = ilog2(ways); 123 return 0; 124 } 125 if (ways % 3) 126 return -EINVAL; 127 ways /= 3; 128 if (!is_power_of_2(ways)) 129 return -EINVAL; 130 *eiw = ilog2(ways) + 8; 131 return 0; 132 } 133 134 /* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */ 135 #define CXL_RAS_UNCORRECTABLE_STATUS_OFFSET 0x0 136 #define CXL_RAS_UNCORRECTABLE_STATUS_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 137 #define CXL_RAS_UNCORRECTABLE_MASK_OFFSET 0x4 138 #define CXL_RAS_UNCORRECTABLE_MASK_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 139 #define CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK BIT(8) 140 #define CXL_RAS_UNCORRECTABLE_SEVERITY_OFFSET 0x8 141 #define CXL_RAS_UNCORRECTABLE_SEVERITY_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 142 #define CXL_RAS_CORRECTABLE_STATUS_OFFSET 0xC 143 #define CXL_RAS_CORRECTABLE_STATUS_MASK GENMASK(6, 0) 144 #define CXL_RAS_CORRECTABLE_MASK_OFFSET 0x10 145 #define CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0) 146 #define CXL_RAS_CAP_CONTROL_OFFSET 0x14 147 #define CXL_RAS_CAP_CONTROL_FE_MASK GENMASK(5, 0) 148 #define CXL_RAS_HEADER_LOG_OFFSET 0x18 149 #define CXL_RAS_CAPABILITY_LENGTH 0x58 150 #define CXL_HEADERLOG_SIZE SZ_512 151 #define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32) 152 153 /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ 154 #define CXLDEV_CAP_ARRAY_OFFSET 0x0 155 #define CXLDEV_CAP_ARRAY_CAP_ID 0 156 #define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0) 157 #define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32) 158 /* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */ 159 #define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0) 160 /* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */ 161 #define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1 162 #define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2 163 #define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3 164 #define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000 165 166 /* CXL 3.0 8.2.8.3.1 Event Status Register */ 167 #define CXLDEV_DEV_EVENT_STATUS_OFFSET 0x00 168 #define CXLDEV_EVENT_STATUS_INFO BIT(0) 169 #define CXLDEV_EVENT_STATUS_WARN BIT(1) 170 #define CXLDEV_EVENT_STATUS_FAIL BIT(2) 171 #define CXLDEV_EVENT_STATUS_FATAL BIT(3) 172 173 #define CXLDEV_EVENT_STATUS_ALL (CXLDEV_EVENT_STATUS_INFO | \ 174 CXLDEV_EVENT_STATUS_WARN | \ 175 CXLDEV_EVENT_STATUS_FAIL | \ 176 CXLDEV_EVENT_STATUS_FATAL) 177 178 /* CXL rev 3.0 section 8.2.9.2.4; Table 8-52 */ 179 #define CXLDEV_EVENT_INT_MODE_MASK GENMASK(1, 0) 180 #define CXLDEV_EVENT_INT_MSGNUM_MASK GENMASK(7, 4) 181 182 /* CXL 2.0 8.2.8.4 Mailbox Registers */ 183 #define CXLDEV_MBOX_CAPS_OFFSET 0x00 184 #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0) 185 #define CXLDEV_MBOX_CAP_BG_CMD_IRQ BIT(6) 186 #define CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK GENMASK(10, 7) 187 #define CXLDEV_MBOX_CTRL_OFFSET 0x04 188 #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0) 189 #define CXLDEV_MBOX_CTRL_BG_CMD_IRQ BIT(2) 190 #define CXLDEV_MBOX_CMD_OFFSET 0x08 191 #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) 192 #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16) 193 #define CXLDEV_MBOX_STATUS_OFFSET 0x10 194 #define CXLDEV_MBOX_STATUS_BG_CMD BIT(0) 195 #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32) 196 #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18 197 #define CXLDEV_MBOX_BG_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) 198 #define CXLDEV_MBOX_BG_CMD_COMMAND_PCT_MASK GENMASK_ULL(22, 16) 199 #define CXLDEV_MBOX_BG_CMD_COMMAND_RC_MASK GENMASK_ULL(47, 32) 200 #define CXLDEV_MBOX_BG_CMD_COMMAND_VENDOR_MASK GENMASK_ULL(63, 48) 201 #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20 202 203 /* 204 * Using struct_group() allows for per register-block-type helper routines, 205 * without requiring block-type agnostic code to include the prefix. 206 */ 207 struct cxl_regs { 208 /* 209 * Common set of CXL Component register block base pointers 210 * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure 211 * @ras: CXL 2.0 8.2.5.9 CXL RAS Capability Structure 212 */ 213 struct_group_tagged(cxl_component_regs, component, 214 void __iomem *hdm_decoder; 215 void __iomem *ras; 216 ); 217 /* 218 * Common set of CXL Device register block base pointers 219 * @status: CXL 2.0 8.2.8.3 Device Status Registers 220 * @mbox: CXL 2.0 8.2.8.4 Mailbox Registers 221 * @memdev: CXL 2.0 8.2.8.5 Memory Device Registers 222 */ 223 struct_group_tagged(cxl_device_regs, device_regs, 224 void __iomem *status, *mbox, *memdev; 225 ); 226 227 struct_group_tagged(cxl_pmu_regs, pmu_regs, 228 void __iomem *pmu; 229 ); 230 231 /* 232 * RCH downstream port specific RAS register 233 * @aer: CXL 3.0 8.2.1.1 RCH Downstream Port RCRB 234 */ 235 struct_group_tagged(cxl_rch_regs, rch_regs, 236 void __iomem *dport_aer; 237 ); 238 239 /* 240 * RCD upstream port specific PCIe cap register 241 * @pcie_cap: CXL 3.0 8.2.1.2 RCD Upstream Port RCRB 242 */ 243 struct_group_tagged(cxl_rcd_regs, rcd_regs, 244 void __iomem *rcd_pcie_cap; 245 ); 246 }; 247 248 struct cxl_reg_map { 249 bool valid; 250 int id; 251 unsigned long offset; 252 unsigned long size; 253 }; 254 255 struct cxl_component_reg_map { 256 struct cxl_reg_map hdm_decoder; 257 struct cxl_reg_map ras; 258 }; 259 260 struct cxl_device_reg_map { 261 struct cxl_reg_map status; 262 struct cxl_reg_map mbox; 263 struct cxl_reg_map memdev; 264 }; 265 266 struct cxl_pmu_reg_map { 267 struct cxl_reg_map pmu; 268 }; 269 270 /** 271 * struct cxl_register_map - DVSEC harvested register block mapping parameters 272 * @host: device for devm operations and logging 273 * @base: virtual base of the register-block-BAR + @block_offset 274 * @resource: physical resource base of the register block 275 * @max_size: maximum mapping size to perform register search 276 * @reg_type: see enum cxl_regloc_type 277 * @component_map: cxl_reg_map for component registers 278 * @device_map: cxl_reg_maps for device registers 279 * @pmu_map: cxl_reg_maps for CXL Performance Monitoring Units 280 */ 281 struct cxl_register_map { 282 struct device *host; 283 void __iomem *base; 284 resource_size_t resource; 285 resource_size_t max_size; 286 u8 reg_type; 287 union { 288 struct cxl_component_reg_map component_map; 289 struct cxl_device_reg_map device_map; 290 struct cxl_pmu_reg_map pmu_map; 291 }; 292 }; 293 294 void cxl_probe_component_regs(struct device *dev, void __iomem *base, 295 struct cxl_component_reg_map *map); 296 void cxl_probe_device_regs(struct device *dev, void __iomem *base, 297 struct cxl_device_reg_map *map); 298 int cxl_map_component_regs(const struct cxl_register_map *map, 299 struct cxl_component_regs *regs, 300 unsigned long map_mask); 301 int cxl_map_device_regs(const struct cxl_register_map *map, 302 struct cxl_device_regs *regs); 303 int cxl_map_pmu_regs(struct cxl_register_map *map, struct cxl_pmu_regs *regs); 304 305 enum cxl_regloc_type; 306 int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type); 307 int cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type, 308 struct cxl_register_map *map, int index); 309 int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, 310 struct cxl_register_map *map); 311 int cxl_setup_regs(struct cxl_register_map *map); 312 struct cxl_dport; 313 resource_size_t cxl_rcd_component_reg_phys(struct device *dev, 314 struct cxl_dport *dport); 315 int cxl_dport_map_rcd_linkcap(struct pci_dev *pdev, struct cxl_dport *dport); 316 317 #define CXL_RESOURCE_NONE ((resource_size_t) -1) 318 #define CXL_TARGET_STRLEN 20 319 320 /* 321 * cxl_decoder flags that define the type of memory / devices this 322 * decoder supports as well as configuration lock status See "CXL 2.0 323 * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details. 324 * Additionally indicate whether decoder settings were autodetected, 325 * user customized. 326 */ 327 #define CXL_DECODER_F_RAM BIT(0) 328 #define CXL_DECODER_F_PMEM BIT(1) 329 #define CXL_DECODER_F_TYPE2 BIT(2) 330 #define CXL_DECODER_F_TYPE3 BIT(3) 331 #define CXL_DECODER_F_LOCK BIT(4) 332 #define CXL_DECODER_F_ENABLE BIT(5) 333 #define CXL_DECODER_F_MASK GENMASK(5, 0) 334 335 enum cxl_decoder_type { 336 CXL_DECODER_DEVMEM = 2, 337 CXL_DECODER_HOSTONLYMEM = 3, 338 }; 339 340 /* 341 * Current specification goes up to 8, double that seems a reasonable 342 * software max for the foreseeable future 343 */ 344 #define CXL_DECODER_MAX_INTERLEAVE 16 345 346 #define CXL_QOS_CLASS_INVALID -1 347 348 /** 349 * struct cxl_decoder - Common CXL HDM Decoder Attributes 350 * @dev: this decoder's device 351 * @id: kernel device name id 352 * @hpa_range: Host physical address range mapped by this decoder 353 * @interleave_ways: number of cxl_dports in this decode 354 * @interleave_granularity: data stride per dport 355 * @target_type: accelerator vs expander (type2 vs type3) selector 356 * @region: currently assigned region for this decoder 357 * @flags: memory type capabilities and locking 358 * @commit: device/decoder-type specific callback to commit settings to hw 359 * @reset: device/decoder-type specific callback to reset hw settings 360 */ 361 struct cxl_decoder { 362 struct device dev; 363 int id; 364 struct range hpa_range; 365 int interleave_ways; 366 int interleave_granularity; 367 enum cxl_decoder_type target_type; 368 struct cxl_region *region; 369 unsigned long flags; 370 int (*commit)(struct cxl_decoder *cxld); 371 void (*reset)(struct cxl_decoder *cxld); 372 }; 373 374 /* 375 * CXL_DECODER_DEAD prevents endpoints from being reattached to regions 376 * while cxld_unregister() is running 377 */ 378 enum cxl_decoder_mode { 379 CXL_DECODER_NONE, 380 CXL_DECODER_RAM, 381 CXL_DECODER_PMEM, 382 CXL_DECODER_MIXED, 383 CXL_DECODER_DEAD, 384 }; 385 386 static inline const char *cxl_decoder_mode_name(enum cxl_decoder_mode mode) 387 { 388 static const char * const names[] = { 389 [CXL_DECODER_NONE] = "none", 390 [CXL_DECODER_RAM] = "ram", 391 [CXL_DECODER_PMEM] = "pmem", 392 [CXL_DECODER_MIXED] = "mixed", 393 }; 394 395 if (mode >= CXL_DECODER_NONE && mode <= CXL_DECODER_MIXED) 396 return names[mode]; 397 return "mixed"; 398 } 399 400 /* 401 * Track whether this decoder is reserved for region autodiscovery, or 402 * free for userspace provisioning. 403 */ 404 enum cxl_decoder_state { 405 CXL_DECODER_STATE_MANUAL, 406 CXL_DECODER_STATE_AUTO, 407 }; 408 409 /** 410 * struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder 411 * @cxld: base cxl_decoder_object 412 * @dpa_res: actively claimed DPA span of this decoder 413 * @skip: offset into @dpa_res where @cxld.hpa_range maps 414 * @mode: which memory type / access-mode-partition this decoder targets 415 * @state: autodiscovery state 416 * @pos: interleave position in @cxld.region 417 */ 418 struct cxl_endpoint_decoder { 419 struct cxl_decoder cxld; 420 struct resource *dpa_res; 421 resource_size_t skip; 422 enum cxl_decoder_mode mode; 423 enum cxl_decoder_state state; 424 int pos; 425 }; 426 427 /** 428 * struct cxl_switch_decoder - Switch specific CXL HDM Decoder 429 * @cxld: base cxl_decoder object 430 * @nr_targets: number of elements in @target 431 * @target: active ordered target list in current decoder configuration 432 * 433 * The 'switch' decoder type represents the decoder instances of cxl_port's that 434 * route from the root of a CXL memory decode topology to the endpoints. They 435 * come in two flavors, root-level decoders, statically defined by platform 436 * firmware, and mid-level decoders, where interleave-granularity, 437 * interleave-width, and the target list are mutable. 438 */ 439 struct cxl_switch_decoder { 440 struct cxl_decoder cxld; 441 int nr_targets; 442 struct cxl_dport *target[]; 443 }; 444 445 struct cxl_root_decoder; 446 typedef u64 (*cxl_hpa_to_spa_fn)(struct cxl_root_decoder *cxlrd, u64 hpa); 447 448 /** 449 * struct cxl_root_decoder - Static platform CXL address decoder 450 * @res: host / parent resource for region allocations 451 * @region_id: region id for next region provisioning event 452 * @hpa_to_spa: translate CXL host-physical-address to Platform system-physical-address 453 * @platform_data: platform specific configuration data 454 * @range_lock: sync region autodiscovery by address range 455 * @qos_class: QoS performance class cookie 456 * @cxlsd: base cxl switch decoder 457 */ 458 struct cxl_root_decoder { 459 struct resource *res; 460 atomic_t region_id; 461 cxl_hpa_to_spa_fn hpa_to_spa; 462 void *platform_data; 463 struct mutex range_lock; 464 int qos_class; 465 struct cxl_switch_decoder cxlsd; 466 }; 467 468 /* 469 * enum cxl_config_state - State machine for region configuration 470 * @CXL_CONFIG_IDLE: Any sysfs attribute can be written freely 471 * @CXL_CONFIG_INTERLEAVE_ACTIVE: region size has been set, no more 472 * changes to interleave_ways or interleave_granularity 473 * @CXL_CONFIG_ACTIVE: All targets have been added the region is now 474 * active 475 * @CXL_CONFIG_RESET_PENDING: see commit_store() 476 * @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware 477 */ 478 enum cxl_config_state { 479 CXL_CONFIG_IDLE, 480 CXL_CONFIG_INTERLEAVE_ACTIVE, 481 CXL_CONFIG_ACTIVE, 482 CXL_CONFIG_RESET_PENDING, 483 CXL_CONFIG_COMMIT, 484 }; 485 486 /** 487 * struct cxl_region_params - region settings 488 * @state: allow the driver to lockdown further parameter changes 489 * @uuid: unique id for persistent regions 490 * @interleave_ways: number of endpoints in the region 491 * @interleave_granularity: capacity each endpoint contributes to a stripe 492 * @res: allocated iomem capacity for this region 493 * @targets: active ordered targets in current decoder configuration 494 * @nr_targets: number of targets 495 * 496 * State transitions are protected by the cxl_region_rwsem 497 */ 498 struct cxl_region_params { 499 enum cxl_config_state state; 500 uuid_t uuid; 501 int interleave_ways; 502 int interleave_granularity; 503 struct resource *res; 504 struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE]; 505 int nr_targets; 506 }; 507 508 /* 509 * Indicate whether this region has been assembled by autodetection or 510 * userspace assembly. Prevent endpoint decoders outside of automatic 511 * detection from being added to the region. 512 */ 513 #define CXL_REGION_F_AUTO 0 514 515 /* 516 * Require that a committed region successfully complete a teardown once 517 * any of its associated decoders have been torn down. This maintains 518 * the commit state for the region since there are committed decoders, 519 * but blocks cxl_region_probe(). 520 */ 521 #define CXL_REGION_F_NEEDS_RESET 1 522 523 /** 524 * struct cxl_region - CXL region 525 * @dev: This region's device 526 * @id: This region's id. Id is globally unique across all regions 527 * @mode: Endpoint decoder allocation / access mode 528 * @type: Endpoint decoder target type 529 * @cxl_nvb: nvdimm bridge for coordinating @cxlr_pmem setup / shutdown 530 * @cxlr_pmem: (for pmem regions) cached copy of the nvdimm bridge 531 * @flags: Region state flags 532 * @params: active + config params for the region 533 * @coord: QoS access coordinates for the region 534 * @memory_notifier: notifier for setting the access coordinates to node 535 * @adist_notifier: notifier for calculating the abstract distance of node 536 */ 537 struct cxl_region { 538 struct device dev; 539 int id; 540 enum cxl_decoder_mode mode; 541 enum cxl_decoder_type type; 542 struct cxl_nvdimm_bridge *cxl_nvb; 543 struct cxl_pmem_region *cxlr_pmem; 544 unsigned long flags; 545 struct cxl_region_params params; 546 struct access_coordinate coord[ACCESS_COORDINATE_MAX]; 547 struct notifier_block memory_notifier; 548 struct notifier_block adist_notifier; 549 }; 550 551 struct cxl_nvdimm_bridge { 552 int id; 553 struct device dev; 554 struct cxl_port *port; 555 struct nvdimm_bus *nvdimm_bus; 556 struct nvdimm_bus_descriptor nd_desc; 557 }; 558 559 #define CXL_DEV_ID_LEN 19 560 561 struct cxl_nvdimm { 562 struct device dev; 563 struct cxl_memdev *cxlmd; 564 u8 dev_id[CXL_DEV_ID_LEN]; /* for nvdimm, string of 'serial' */ 565 }; 566 567 struct cxl_pmem_region_mapping { 568 struct cxl_memdev *cxlmd; 569 struct cxl_nvdimm *cxl_nvd; 570 u64 start; 571 u64 size; 572 int position; 573 }; 574 575 struct cxl_pmem_region { 576 struct device dev; 577 struct cxl_region *cxlr; 578 struct nd_region *nd_region; 579 struct range hpa_range; 580 int nr_mappings; 581 struct cxl_pmem_region_mapping mapping[]; 582 }; 583 584 struct cxl_dax_region { 585 struct device dev; 586 struct cxl_region *cxlr; 587 struct range hpa_range; 588 }; 589 590 /** 591 * struct cxl_port - logical collection of upstream port devices and 592 * downstream port devices to construct a CXL memory 593 * decode hierarchy. 594 * @dev: this port's device 595 * @uport_dev: PCI or platform device implementing the upstream port capability 596 * @host_bridge: Shortcut to the platform attach point for this port 597 * @id: id for port device-name 598 * @dports: cxl_dport instances referenced by decoders 599 * @endpoints: cxl_ep instances, endpoints that are a descendant of this port 600 * @regions: cxl_region_ref instances, regions mapped by this port 601 * @parent_dport: dport that points to this port in the parent 602 * @decoder_ida: allocator for decoder ids 603 * @reg_map: component and ras register mapping parameters 604 * @nr_dports: number of entries in @dports 605 * @hdm_end: track last allocated HDM decoder instance for allocation ordering 606 * @commit_end: cursor to track highest committed decoder for commit ordering 607 * @dead: last ep has been removed, force port re-creation 608 * @depth: How deep this port is relative to the root. depth 0 is the root. 609 * @cdat: Cached CDAT data 610 * @cdat_available: Should a CDAT attribute be available in sysfs 611 * @pci_latency: Upstream latency in picoseconds 612 */ 613 struct cxl_port { 614 struct device dev; 615 struct device *uport_dev; 616 struct device *host_bridge; 617 int id; 618 struct xarray dports; 619 struct xarray endpoints; 620 struct xarray regions; 621 struct cxl_dport *parent_dport; 622 struct ida decoder_ida; 623 struct cxl_register_map reg_map; 624 int nr_dports; 625 int hdm_end; 626 int commit_end; 627 bool dead; 628 unsigned int depth; 629 struct cxl_cdat { 630 void *table; 631 size_t length; 632 } cdat; 633 bool cdat_available; 634 long pci_latency; 635 }; 636 637 /** 638 * struct cxl_root - logical collection of root cxl_port items 639 * 640 * @port: cxl_port member 641 * @ops: cxl root operations 642 */ 643 struct cxl_root { 644 struct cxl_port port; 645 const struct cxl_root_ops *ops; 646 }; 647 648 static inline struct cxl_root * 649 to_cxl_root(const struct cxl_port *port) 650 { 651 return container_of(port, struct cxl_root, port); 652 } 653 654 struct cxl_root_ops { 655 int (*qos_class)(struct cxl_root *cxl_root, 656 struct access_coordinate *coord, int entries, 657 int *qos_class); 658 }; 659 660 static inline struct cxl_dport * 661 cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev) 662 { 663 return xa_load(&port->dports, (unsigned long)dport_dev); 664 } 665 666 struct cxl_rcrb_info { 667 resource_size_t base; 668 u16 aer_cap; 669 }; 670 671 /** 672 * struct cxl_dport - CXL downstream port 673 * @dport_dev: PCI bridge or firmware device representing the downstream link 674 * @reg_map: component and ras register mapping parameters 675 * @port_id: unique hardware identifier for dport in decoder target list 676 * @rcrb: Data about the Root Complex Register Block layout 677 * @rch: Indicate whether this dport was enumerated in RCH or VH mode 678 * @port: reference to cxl_port that contains this downstream port 679 * @regs: Dport parsed register blocks 680 * @coord: access coordinates (bandwidth and latency performance attributes) 681 * @link_latency: calculated PCIe downstream latency 682 */ 683 struct cxl_dport { 684 struct device *dport_dev; 685 struct cxl_register_map reg_map; 686 int port_id; 687 struct cxl_rcrb_info rcrb; 688 bool rch; 689 struct cxl_port *port; 690 struct cxl_regs regs; 691 struct access_coordinate coord[ACCESS_COORDINATE_MAX]; 692 long link_latency; 693 }; 694 695 /** 696 * struct cxl_ep - track an endpoint's interest in a port 697 * @ep: device that hosts a generic CXL endpoint (expander or accelerator) 698 * @dport: which dport routes to this endpoint on @port 699 * @next: cxl switch port across the link attached to @dport NULL if 700 * attached to an endpoint 701 */ 702 struct cxl_ep { 703 struct device *ep; 704 struct cxl_dport *dport; 705 struct cxl_port *next; 706 }; 707 708 /** 709 * struct cxl_region_ref - track a region's interest in a port 710 * @port: point in topology to install this reference 711 * @decoder: decoder assigned for @region in @port 712 * @region: region for this reference 713 * @endpoints: cxl_ep references for region members beneath @port 714 * @nr_targets_set: track how many targets have been programmed during setup 715 * @nr_eps: number of endpoints beneath @port 716 * @nr_targets: number of distinct targets needed to reach @nr_eps 717 */ 718 struct cxl_region_ref { 719 struct cxl_port *port; 720 struct cxl_decoder *decoder; 721 struct cxl_region *region; 722 struct xarray endpoints; 723 int nr_targets_set; 724 int nr_eps; 725 int nr_targets; 726 }; 727 728 /* 729 * The platform firmware device hosting the root is also the top of the 730 * CXL port topology. All other CXL ports have another CXL port as their 731 * parent and their ->uport_dev / host device is out-of-line of the port 732 * ancestry. 733 */ 734 static inline bool is_cxl_root(struct cxl_port *port) 735 { 736 return port->uport_dev == port->dev.parent; 737 } 738 739 int cxl_num_decoders_committed(struct cxl_port *port); 740 bool is_cxl_port(const struct device *dev); 741 struct cxl_port *to_cxl_port(const struct device *dev); 742 void cxl_port_commit_reap(struct cxl_decoder *cxld); 743 struct pci_bus; 744 int devm_cxl_register_pci_bus(struct device *host, struct device *uport_dev, 745 struct pci_bus *bus); 746 struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port); 747 struct cxl_port *devm_cxl_add_port(struct device *host, 748 struct device *uport_dev, 749 resource_size_t component_reg_phys, 750 struct cxl_dport *parent_dport); 751 struct cxl_root *devm_cxl_add_root(struct device *host, 752 const struct cxl_root_ops *ops); 753 struct cxl_root *find_cxl_root(struct cxl_port *port); 754 void put_cxl_root(struct cxl_root *cxl_root); 755 DEFINE_FREE(put_cxl_root, struct cxl_root *, if (_T) put_cxl_root(_T)) 756 757 DEFINE_FREE(put_cxl_port, struct cxl_port *, if (!IS_ERR_OR_NULL(_T)) put_device(&_T->dev)) 758 int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); 759 void cxl_bus_rescan(void); 760 void cxl_bus_drain(void); 761 struct cxl_port *cxl_pci_find_port(struct pci_dev *pdev, 762 struct cxl_dport **dport); 763 struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd, 764 struct cxl_dport **dport); 765 bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd); 766 767 struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, 768 struct device *dport, int port_id, 769 resource_size_t component_reg_phys); 770 struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, 771 struct device *dport_dev, int port_id, 772 resource_size_t rcrb); 773 774 #ifdef CONFIG_PCIEAER_CXL 775 void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport); 776 void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host); 777 #else 778 static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport, 779 struct device *host) { } 780 #endif 781 782 struct cxl_decoder *to_cxl_decoder(struct device *dev); 783 struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev); 784 struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev); 785 struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev); 786 bool is_root_decoder(struct device *dev); 787 bool is_switch_decoder(struct device *dev); 788 bool is_endpoint_decoder(struct device *dev); 789 struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, 790 unsigned int nr_targets); 791 struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port, 792 unsigned int nr_targets); 793 int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map); 794 struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port); 795 int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map); 796 int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld); 797 static inline int cxl_root_decoder_autoremove(struct device *host, 798 struct cxl_root_decoder *cxlrd) 799 { 800 return cxl_decoder_autoremove(host, &cxlrd->cxlsd.cxld); 801 } 802 int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint); 803 804 /** 805 * struct cxl_endpoint_dvsec_info - Cached DVSEC info 806 * @mem_enabled: cached value of mem_enabled in the DVSEC at init time 807 * @ranges: Number of active HDM ranges this device uses. 808 * @port: endpoint port associated with this info instance 809 * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE 810 */ 811 struct cxl_endpoint_dvsec_info { 812 bool mem_enabled; 813 int ranges; 814 struct cxl_port *port; 815 struct range dvsec_range[2]; 816 }; 817 818 struct cxl_hdm; 819 struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port, 820 struct cxl_endpoint_dvsec_info *info); 821 int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm, 822 struct cxl_endpoint_dvsec_info *info); 823 int devm_cxl_add_passthrough_decoder(struct cxl_port *port); 824 int cxl_dvsec_rr_decode(struct device *dev, struct cxl_port *port, 825 struct cxl_endpoint_dvsec_info *info); 826 827 bool is_cxl_region(struct device *dev); 828 829 extern struct bus_type cxl_bus_type; 830 831 struct cxl_driver { 832 const char *name; 833 int (*probe)(struct device *dev); 834 void (*remove)(struct device *dev); 835 struct device_driver drv; 836 int id; 837 }; 838 839 #define to_cxl_drv(__drv) container_of_const(__drv, struct cxl_driver, drv) 840 841 int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner, 842 const char *modname); 843 #define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME) 844 void cxl_driver_unregister(struct cxl_driver *cxl_drv); 845 846 #define module_cxl_driver(__cxl_driver) \ 847 module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister) 848 849 #define CXL_DEVICE_NVDIMM_BRIDGE 1 850 #define CXL_DEVICE_NVDIMM 2 851 #define CXL_DEVICE_PORT 3 852 #define CXL_DEVICE_ROOT 4 853 #define CXL_DEVICE_MEMORY_EXPANDER 5 854 #define CXL_DEVICE_REGION 6 855 #define CXL_DEVICE_PMEM_REGION 7 856 #define CXL_DEVICE_DAX_REGION 8 857 #define CXL_DEVICE_PMU 9 858 859 #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*") 860 #define CXL_MODALIAS_FMT "cxl:t%d" 861 862 struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev); 863 struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host, 864 struct cxl_port *port); 865 struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev); 866 bool is_cxl_nvdimm(struct device *dev); 867 bool is_cxl_nvdimm_bridge(struct device *dev); 868 int devm_cxl_add_nvdimm(struct cxl_port *parent_port, struct cxl_memdev *cxlmd); 869 struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_port *port); 870 871 #ifdef CONFIG_CXL_REGION 872 bool is_cxl_pmem_region(struct device *dev); 873 struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev); 874 int cxl_add_to_region(struct cxl_port *root, 875 struct cxl_endpoint_decoder *cxled); 876 struct cxl_dax_region *to_cxl_dax_region(struct device *dev); 877 #else 878 static inline bool is_cxl_pmem_region(struct device *dev) 879 { 880 return false; 881 } 882 static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev) 883 { 884 return NULL; 885 } 886 static inline int cxl_add_to_region(struct cxl_port *root, 887 struct cxl_endpoint_decoder *cxled) 888 { 889 return 0; 890 } 891 static inline struct cxl_dax_region *to_cxl_dax_region(struct device *dev) 892 { 893 return NULL; 894 } 895 #endif 896 897 void cxl_endpoint_parse_cdat(struct cxl_port *port); 898 void cxl_switch_parse_cdat(struct cxl_port *port); 899 900 int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, 901 struct access_coordinate *coord); 902 void cxl_region_perf_data_calculate(struct cxl_region *cxlr, 903 struct cxl_endpoint_decoder *cxled); 904 void cxl_region_shared_upstream_bandwidth_update(struct cxl_region *cxlr); 905 906 void cxl_memdev_update_perf(struct cxl_memdev *cxlmd); 907 908 void cxl_coordinates_combine(struct access_coordinate *out, 909 struct access_coordinate *c1, 910 struct access_coordinate *c2); 911 912 bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port); 913 914 /* 915 * Unit test builds overrides this to __weak, find the 'strong' version 916 * of these symbols in tools/testing/cxl/. 917 */ 918 #ifndef __mock 919 #define __mock static 920 #endif 921 922 #endif /* __CXL_H__ */ 923