1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020 Intel Corporation. */ 3 4 #ifndef __CXL_H__ 5 #define __CXL_H__ 6 7 #include <linux/libnvdimm.h> 8 #include <linux/bitfield.h> 9 #include <linux/notifier.h> 10 #include <linux/bitops.h> 11 #include <linux/log2.h> 12 #include <linux/node.h> 13 #include <linux/io.h> 14 15 extern const struct nvdimm_security_ops *cxl_security_ops; 16 17 /** 18 * DOC: cxl objects 19 * 20 * The CXL core objects like ports, decoders, and regions are shared 21 * between the subsystem drivers cxl_acpi, cxl_pci, and core drivers 22 * (port-driver, region-driver, nvdimm object-drivers... etc). 23 */ 24 25 /* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */ 26 #define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K 27 28 /* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/ 29 #define CXL_CM_OFFSET 0x1000 30 #define CXL_CM_CAP_HDR_OFFSET 0x0 31 #define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0) 32 #define CM_CAP_HDR_CAP_ID 1 33 #define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16) 34 #define CM_CAP_HDR_CAP_VERSION 1 35 #define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20) 36 #define CM_CAP_HDR_CACHE_MEM_VERSION 1 37 #define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24) 38 #define CXL_CM_CAP_PTR_MASK GENMASK(31, 20) 39 40 #define CXL_CM_CAP_CAP_ID_RAS 0x2 41 #define CXL_CM_CAP_CAP_ID_HDM 0x5 42 #define CXL_CM_CAP_CAP_HDM_VERSION 1 43 44 /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */ 45 #define CXL_HDM_DECODER_CAP_OFFSET 0x0 46 #define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0) 47 #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4) 48 #define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8) 49 #define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9) 50 #define CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY BIT(11) 51 #define CXL_HDM_DECODER_INTERLEAVE_16_WAY BIT(12) 52 #define CXL_HDM_DECODER_CTRL_OFFSET 0x4 53 #define CXL_HDM_DECODER_ENABLE BIT(1) 54 #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10) 55 #define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14) 56 #define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18) 57 #define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c) 58 #define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20) 59 #define CXL_HDM_DECODER0_CTRL_IG_MASK GENMASK(3, 0) 60 #define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4) 61 #define CXL_HDM_DECODER0_CTRL_LOCK BIT(8) 62 #define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9) 63 #define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10) 64 #define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11) 65 #define CXL_HDM_DECODER0_CTRL_HOSTONLY BIT(12) 66 #define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24) 67 #define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28) 68 #define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i) 69 #define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i) 70 71 /* HDM decoder control register constants CXL 3.0 8.2.5.19.7 */ 72 #define CXL_DECODER_MIN_GRANULARITY 256 73 #define CXL_DECODER_MAX_ENCODED_IG 6 74 75 static inline int cxl_hdm_decoder_count(u32 cap_hdr) 76 { 77 int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr); 78 79 return val ? val * 2 : 1; 80 } 81 82 /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ 83 static inline int eig_to_granularity(u16 eig, unsigned int *granularity) 84 { 85 if (eig > CXL_DECODER_MAX_ENCODED_IG) 86 return -EINVAL; 87 *granularity = CXL_DECODER_MIN_GRANULARITY << eig; 88 return 0; 89 } 90 91 /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */ 92 static inline int eiw_to_ways(u8 eiw, unsigned int *ways) 93 { 94 switch (eiw) { 95 case 0 ... 4: 96 *ways = 1 << eiw; 97 break; 98 case 8 ... 10: 99 *ways = 3 << (eiw - 8); 100 break; 101 default: 102 return -EINVAL; 103 } 104 105 return 0; 106 } 107 108 static inline int granularity_to_eig(int granularity, u16 *eig) 109 { 110 if (granularity > SZ_16K || granularity < CXL_DECODER_MIN_GRANULARITY || 111 !is_power_of_2(granularity)) 112 return -EINVAL; 113 *eig = ilog2(granularity) - 8; 114 return 0; 115 } 116 117 static inline int ways_to_eiw(unsigned int ways, u8 *eiw) 118 { 119 if (ways > 16) 120 return -EINVAL; 121 if (is_power_of_2(ways)) { 122 *eiw = ilog2(ways); 123 return 0; 124 } 125 if (ways % 3) 126 return -EINVAL; 127 ways /= 3; 128 if (!is_power_of_2(ways)) 129 return -EINVAL; 130 *eiw = ilog2(ways) + 8; 131 return 0; 132 } 133 134 /* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */ 135 #define CXL_RAS_UNCORRECTABLE_STATUS_OFFSET 0x0 136 #define CXL_RAS_UNCORRECTABLE_STATUS_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 137 #define CXL_RAS_UNCORRECTABLE_MASK_OFFSET 0x4 138 #define CXL_RAS_UNCORRECTABLE_MASK_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 139 #define CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK BIT(8) 140 #define CXL_RAS_UNCORRECTABLE_SEVERITY_OFFSET 0x8 141 #define CXL_RAS_UNCORRECTABLE_SEVERITY_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 142 #define CXL_RAS_CORRECTABLE_STATUS_OFFSET 0xC 143 #define CXL_RAS_CORRECTABLE_STATUS_MASK GENMASK(6, 0) 144 #define CXL_RAS_CORRECTABLE_MASK_OFFSET 0x10 145 #define CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0) 146 #define CXL_RAS_CAP_CONTROL_OFFSET 0x14 147 #define CXL_RAS_CAP_CONTROL_FE_MASK GENMASK(5, 0) 148 #define CXL_RAS_HEADER_LOG_OFFSET 0x18 149 #define CXL_RAS_CAPABILITY_LENGTH 0x58 150 #define CXL_HEADERLOG_SIZE SZ_512 151 #define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32) 152 153 /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ 154 #define CXLDEV_CAP_ARRAY_OFFSET 0x0 155 #define CXLDEV_CAP_ARRAY_CAP_ID 0 156 #define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0) 157 #define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32) 158 /* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */ 159 #define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0) 160 /* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */ 161 #define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1 162 #define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2 163 #define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3 164 #define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000 165 166 /* CXL 3.0 8.2.8.3.1 Event Status Register */ 167 #define CXLDEV_DEV_EVENT_STATUS_OFFSET 0x00 168 #define CXLDEV_EVENT_STATUS_INFO BIT(0) 169 #define CXLDEV_EVENT_STATUS_WARN BIT(1) 170 #define CXLDEV_EVENT_STATUS_FAIL BIT(2) 171 #define CXLDEV_EVENT_STATUS_FATAL BIT(3) 172 173 #define CXLDEV_EVENT_STATUS_ALL (CXLDEV_EVENT_STATUS_INFO | \ 174 CXLDEV_EVENT_STATUS_WARN | \ 175 CXLDEV_EVENT_STATUS_FAIL | \ 176 CXLDEV_EVENT_STATUS_FATAL) 177 178 /* CXL rev 3.0 section 8.2.9.2.4; Table 8-52 */ 179 #define CXLDEV_EVENT_INT_MODE_MASK GENMASK(1, 0) 180 #define CXLDEV_EVENT_INT_MSGNUM_MASK GENMASK(7, 4) 181 182 /* CXL 2.0 8.2.8.4 Mailbox Registers */ 183 #define CXLDEV_MBOX_CAPS_OFFSET 0x00 184 #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0) 185 #define CXLDEV_MBOX_CAP_BG_CMD_IRQ BIT(6) 186 #define CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK GENMASK(10, 7) 187 #define CXLDEV_MBOX_CTRL_OFFSET 0x04 188 #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0) 189 #define CXLDEV_MBOX_CTRL_BG_CMD_IRQ BIT(2) 190 #define CXLDEV_MBOX_CMD_OFFSET 0x08 191 #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) 192 #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16) 193 #define CXLDEV_MBOX_STATUS_OFFSET 0x10 194 #define CXLDEV_MBOX_STATUS_BG_CMD BIT(0) 195 #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32) 196 #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18 197 #define CXLDEV_MBOX_BG_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) 198 #define CXLDEV_MBOX_BG_CMD_COMMAND_PCT_MASK GENMASK_ULL(22, 16) 199 #define CXLDEV_MBOX_BG_CMD_COMMAND_RC_MASK GENMASK_ULL(47, 32) 200 #define CXLDEV_MBOX_BG_CMD_COMMAND_VENDOR_MASK GENMASK_ULL(63, 48) 201 #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20 202 203 /* 204 * Using struct_group() allows for per register-block-type helper routines, 205 * without requiring block-type agnostic code to include the prefix. 206 */ 207 struct cxl_regs { 208 /* 209 * Common set of CXL Component register block base pointers 210 * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure 211 * @ras: CXL 2.0 8.2.5.9 CXL RAS Capability Structure 212 */ 213 struct_group_tagged(cxl_component_regs, component, 214 void __iomem *hdm_decoder; 215 void __iomem *ras; 216 ); 217 /* 218 * Common set of CXL Device register block base pointers 219 * @status: CXL 2.0 8.2.8.3 Device Status Registers 220 * @mbox: CXL 2.0 8.2.8.4 Mailbox Registers 221 * @memdev: CXL 2.0 8.2.8.5 Memory Device Registers 222 */ 223 struct_group_tagged(cxl_device_regs, device_regs, 224 void __iomem *status, *mbox, *memdev; 225 ); 226 227 struct_group_tagged(cxl_pmu_regs, pmu_regs, 228 void __iomem *pmu; 229 ); 230 231 /* 232 * RCH downstream port specific RAS register 233 * @aer: CXL 3.0 8.2.1.1 RCH Downstream Port RCRB 234 */ 235 struct_group_tagged(cxl_rch_regs, rch_regs, 236 void __iomem *dport_aer; 237 ); 238 }; 239 240 struct cxl_reg_map { 241 bool valid; 242 int id; 243 unsigned long offset; 244 unsigned long size; 245 }; 246 247 struct cxl_component_reg_map { 248 struct cxl_reg_map hdm_decoder; 249 struct cxl_reg_map ras; 250 }; 251 252 struct cxl_device_reg_map { 253 struct cxl_reg_map status; 254 struct cxl_reg_map mbox; 255 struct cxl_reg_map memdev; 256 }; 257 258 struct cxl_pmu_reg_map { 259 struct cxl_reg_map pmu; 260 }; 261 262 /** 263 * struct cxl_register_map - DVSEC harvested register block mapping parameters 264 * @host: device for devm operations and logging 265 * @base: virtual base of the register-block-BAR + @block_offset 266 * @resource: physical resource base of the register block 267 * @max_size: maximum mapping size to perform register search 268 * @reg_type: see enum cxl_regloc_type 269 * @component_map: cxl_reg_map for component registers 270 * @device_map: cxl_reg_maps for device registers 271 * @pmu_map: cxl_reg_maps for CXL Performance Monitoring Units 272 */ 273 struct cxl_register_map { 274 struct device *host; 275 void __iomem *base; 276 resource_size_t resource; 277 resource_size_t max_size; 278 u8 reg_type; 279 union { 280 struct cxl_component_reg_map component_map; 281 struct cxl_device_reg_map device_map; 282 struct cxl_pmu_reg_map pmu_map; 283 }; 284 }; 285 286 void cxl_probe_component_regs(struct device *dev, void __iomem *base, 287 struct cxl_component_reg_map *map); 288 void cxl_probe_device_regs(struct device *dev, void __iomem *base, 289 struct cxl_device_reg_map *map); 290 int cxl_map_component_regs(const struct cxl_register_map *map, 291 struct cxl_component_regs *regs, 292 unsigned long map_mask); 293 int cxl_map_device_regs(const struct cxl_register_map *map, 294 struct cxl_device_regs *regs); 295 int cxl_map_pmu_regs(struct cxl_register_map *map, struct cxl_pmu_regs *regs); 296 297 enum cxl_regloc_type; 298 int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type); 299 int cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type, 300 struct cxl_register_map *map, int index); 301 int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, 302 struct cxl_register_map *map); 303 int cxl_setup_regs(struct cxl_register_map *map); 304 struct cxl_dport; 305 resource_size_t cxl_rcd_component_reg_phys(struct device *dev, 306 struct cxl_dport *dport); 307 308 #define CXL_RESOURCE_NONE ((resource_size_t) -1) 309 #define CXL_TARGET_STRLEN 20 310 311 /* 312 * cxl_decoder flags that define the type of memory / devices this 313 * decoder supports as well as configuration lock status See "CXL 2.0 314 * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details. 315 * Additionally indicate whether decoder settings were autodetected, 316 * user customized. 317 */ 318 #define CXL_DECODER_F_RAM BIT(0) 319 #define CXL_DECODER_F_PMEM BIT(1) 320 #define CXL_DECODER_F_TYPE2 BIT(2) 321 #define CXL_DECODER_F_TYPE3 BIT(3) 322 #define CXL_DECODER_F_LOCK BIT(4) 323 #define CXL_DECODER_F_ENABLE BIT(5) 324 #define CXL_DECODER_F_MASK GENMASK(5, 0) 325 326 enum cxl_decoder_type { 327 CXL_DECODER_DEVMEM = 2, 328 CXL_DECODER_HOSTONLYMEM = 3, 329 }; 330 331 /* 332 * Current specification goes up to 8, double that seems a reasonable 333 * software max for the foreseeable future 334 */ 335 #define CXL_DECODER_MAX_INTERLEAVE 16 336 337 #define CXL_QOS_CLASS_INVALID -1 338 339 /** 340 * struct cxl_decoder - Common CXL HDM Decoder Attributes 341 * @dev: this decoder's device 342 * @id: kernel device name id 343 * @hpa_range: Host physical address range mapped by this decoder 344 * @interleave_ways: number of cxl_dports in this decode 345 * @interleave_granularity: data stride per dport 346 * @target_type: accelerator vs expander (type2 vs type3) selector 347 * @region: currently assigned region for this decoder 348 * @flags: memory type capabilities and locking 349 * @commit: device/decoder-type specific callback to commit settings to hw 350 * @reset: device/decoder-type specific callback to reset hw settings 351 */ 352 struct cxl_decoder { 353 struct device dev; 354 int id; 355 struct range hpa_range; 356 int interleave_ways; 357 int interleave_granularity; 358 enum cxl_decoder_type target_type; 359 struct cxl_region *region; 360 unsigned long flags; 361 int (*commit)(struct cxl_decoder *cxld); 362 int (*reset)(struct cxl_decoder *cxld); 363 }; 364 365 /* 366 * CXL_DECODER_DEAD prevents endpoints from being reattached to regions 367 * while cxld_unregister() is running 368 */ 369 enum cxl_decoder_mode { 370 CXL_DECODER_NONE, 371 CXL_DECODER_RAM, 372 CXL_DECODER_PMEM, 373 CXL_DECODER_MIXED, 374 CXL_DECODER_DEAD, 375 }; 376 377 static inline const char *cxl_decoder_mode_name(enum cxl_decoder_mode mode) 378 { 379 static const char * const names[] = { 380 [CXL_DECODER_NONE] = "none", 381 [CXL_DECODER_RAM] = "ram", 382 [CXL_DECODER_PMEM] = "pmem", 383 [CXL_DECODER_MIXED] = "mixed", 384 }; 385 386 if (mode >= CXL_DECODER_NONE && mode <= CXL_DECODER_MIXED) 387 return names[mode]; 388 return "mixed"; 389 } 390 391 /* 392 * Track whether this decoder is reserved for region autodiscovery, or 393 * free for userspace provisioning. 394 */ 395 enum cxl_decoder_state { 396 CXL_DECODER_STATE_MANUAL, 397 CXL_DECODER_STATE_AUTO, 398 }; 399 400 /** 401 * struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder 402 * @cxld: base cxl_decoder_object 403 * @dpa_res: actively claimed DPA span of this decoder 404 * @skip: offset into @dpa_res where @cxld.hpa_range maps 405 * @mode: which memory type / access-mode-partition this decoder targets 406 * @state: autodiscovery state 407 * @pos: interleave position in @cxld.region 408 */ 409 struct cxl_endpoint_decoder { 410 struct cxl_decoder cxld; 411 struct resource *dpa_res; 412 resource_size_t skip; 413 enum cxl_decoder_mode mode; 414 enum cxl_decoder_state state; 415 int pos; 416 }; 417 418 /** 419 * struct cxl_switch_decoder - Switch specific CXL HDM Decoder 420 * @cxld: base cxl_decoder object 421 * @nr_targets: number of elements in @target 422 * @target: active ordered target list in current decoder configuration 423 * 424 * The 'switch' decoder type represents the decoder instances of cxl_port's that 425 * route from the root of a CXL memory decode topology to the endpoints. They 426 * come in two flavors, root-level decoders, statically defined by platform 427 * firmware, and mid-level decoders, where interleave-granularity, 428 * interleave-width, and the target list are mutable. 429 */ 430 struct cxl_switch_decoder { 431 struct cxl_decoder cxld; 432 int nr_targets; 433 struct cxl_dport *target[]; 434 }; 435 436 struct cxl_root_decoder; 437 typedef u64 (*cxl_hpa_to_spa_fn)(struct cxl_root_decoder *cxlrd, u64 hpa); 438 439 /** 440 * struct cxl_root_decoder - Static platform CXL address decoder 441 * @res: host / parent resource for region allocations 442 * @region_id: region id for next region provisioning event 443 * @hpa_to_spa: translate CXL host-physical-address to Platform system-physical-address 444 * @platform_data: platform specific configuration data 445 * @range_lock: sync region autodiscovery by address range 446 * @qos_class: QoS performance class cookie 447 * @cxlsd: base cxl switch decoder 448 */ 449 struct cxl_root_decoder { 450 struct resource *res; 451 atomic_t region_id; 452 cxl_hpa_to_spa_fn hpa_to_spa; 453 void *platform_data; 454 struct mutex range_lock; 455 int qos_class; 456 struct cxl_switch_decoder cxlsd; 457 }; 458 459 /* 460 * enum cxl_config_state - State machine for region configuration 461 * @CXL_CONFIG_IDLE: Any sysfs attribute can be written freely 462 * @CXL_CONFIG_INTERLEAVE_ACTIVE: region size has been set, no more 463 * changes to interleave_ways or interleave_granularity 464 * @CXL_CONFIG_ACTIVE: All targets have been added the region is now 465 * active 466 * @CXL_CONFIG_RESET_PENDING: see commit_store() 467 * @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware 468 */ 469 enum cxl_config_state { 470 CXL_CONFIG_IDLE, 471 CXL_CONFIG_INTERLEAVE_ACTIVE, 472 CXL_CONFIG_ACTIVE, 473 CXL_CONFIG_RESET_PENDING, 474 CXL_CONFIG_COMMIT, 475 }; 476 477 /** 478 * struct cxl_region_params - region settings 479 * @state: allow the driver to lockdown further parameter changes 480 * @uuid: unique id for persistent regions 481 * @interleave_ways: number of endpoints in the region 482 * @interleave_granularity: capacity each endpoint contributes to a stripe 483 * @res: allocated iomem capacity for this region 484 * @targets: active ordered targets in current decoder configuration 485 * @nr_targets: number of targets 486 * 487 * State transitions are protected by the cxl_region_rwsem 488 */ 489 struct cxl_region_params { 490 enum cxl_config_state state; 491 uuid_t uuid; 492 int interleave_ways; 493 int interleave_granularity; 494 struct resource *res; 495 struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE]; 496 int nr_targets; 497 }; 498 499 /* 500 * Indicate whether this region has been assembled by autodetection or 501 * userspace assembly. Prevent endpoint decoders outside of automatic 502 * detection from being added to the region. 503 */ 504 #define CXL_REGION_F_AUTO 0 505 506 /* 507 * Require that a committed region successfully complete a teardown once 508 * any of its associated decoders have been torn down. This maintains 509 * the commit state for the region since there are committed decoders, 510 * but blocks cxl_region_probe(). 511 */ 512 #define CXL_REGION_F_NEEDS_RESET 1 513 514 /** 515 * struct cxl_region - CXL region 516 * @dev: This region's device 517 * @id: This region's id. Id is globally unique across all regions 518 * @mode: Endpoint decoder allocation / access mode 519 * @type: Endpoint decoder target type 520 * @cxl_nvb: nvdimm bridge for coordinating @cxlr_pmem setup / shutdown 521 * @cxlr_pmem: (for pmem regions) cached copy of the nvdimm bridge 522 * @flags: Region state flags 523 * @params: active + config params for the region 524 * @coord: QoS access coordinates for the region 525 * @memory_notifier: notifier for setting the access coordinates to node 526 * @adist_notifier: notifier for calculating the abstract distance of node 527 */ 528 struct cxl_region { 529 struct device dev; 530 int id; 531 enum cxl_decoder_mode mode; 532 enum cxl_decoder_type type; 533 struct cxl_nvdimm_bridge *cxl_nvb; 534 struct cxl_pmem_region *cxlr_pmem; 535 unsigned long flags; 536 struct cxl_region_params params; 537 struct access_coordinate coord[ACCESS_COORDINATE_MAX]; 538 struct notifier_block memory_notifier; 539 struct notifier_block adist_notifier; 540 }; 541 542 struct cxl_nvdimm_bridge { 543 int id; 544 struct device dev; 545 struct cxl_port *port; 546 struct nvdimm_bus *nvdimm_bus; 547 struct nvdimm_bus_descriptor nd_desc; 548 }; 549 550 #define CXL_DEV_ID_LEN 19 551 552 struct cxl_nvdimm { 553 struct device dev; 554 struct cxl_memdev *cxlmd; 555 u8 dev_id[CXL_DEV_ID_LEN]; /* for nvdimm, string of 'serial' */ 556 }; 557 558 struct cxl_pmem_region_mapping { 559 struct cxl_memdev *cxlmd; 560 struct cxl_nvdimm *cxl_nvd; 561 u64 start; 562 u64 size; 563 int position; 564 }; 565 566 struct cxl_pmem_region { 567 struct device dev; 568 struct cxl_region *cxlr; 569 struct nd_region *nd_region; 570 struct range hpa_range; 571 int nr_mappings; 572 struct cxl_pmem_region_mapping mapping[]; 573 }; 574 575 struct cxl_dax_region { 576 struct device dev; 577 struct cxl_region *cxlr; 578 struct range hpa_range; 579 }; 580 581 /** 582 * struct cxl_port - logical collection of upstream port devices and 583 * downstream port devices to construct a CXL memory 584 * decode hierarchy. 585 * @dev: this port's device 586 * @uport_dev: PCI or platform device implementing the upstream port capability 587 * @host_bridge: Shortcut to the platform attach point for this port 588 * @id: id for port device-name 589 * @dports: cxl_dport instances referenced by decoders 590 * @endpoints: cxl_ep instances, endpoints that are a descendant of this port 591 * @regions: cxl_region_ref instances, regions mapped by this port 592 * @parent_dport: dport that points to this port in the parent 593 * @decoder_ida: allocator for decoder ids 594 * @reg_map: component and ras register mapping parameters 595 * @nr_dports: number of entries in @dports 596 * @hdm_end: track last allocated HDM decoder instance for allocation ordering 597 * @commit_end: cursor to track highest committed decoder for commit ordering 598 * @dead: last ep has been removed, force port re-creation 599 * @depth: How deep this port is relative to the root. depth 0 is the root. 600 * @cdat: Cached CDAT data 601 * @cdat_available: Should a CDAT attribute be available in sysfs 602 * @pci_latency: Upstream latency in picoseconds 603 */ 604 struct cxl_port { 605 struct device dev; 606 struct device *uport_dev; 607 struct device *host_bridge; 608 int id; 609 struct xarray dports; 610 struct xarray endpoints; 611 struct xarray regions; 612 struct cxl_dport *parent_dport; 613 struct ida decoder_ida; 614 struct cxl_register_map reg_map; 615 int nr_dports; 616 int hdm_end; 617 int commit_end; 618 bool dead; 619 unsigned int depth; 620 struct cxl_cdat { 621 void *table; 622 size_t length; 623 } cdat; 624 bool cdat_available; 625 long pci_latency; 626 }; 627 628 /** 629 * struct cxl_root - logical collection of root cxl_port items 630 * 631 * @port: cxl_port member 632 * @ops: cxl root operations 633 */ 634 struct cxl_root { 635 struct cxl_port port; 636 const struct cxl_root_ops *ops; 637 }; 638 639 static inline struct cxl_root * 640 to_cxl_root(const struct cxl_port *port) 641 { 642 return container_of(port, struct cxl_root, port); 643 } 644 645 struct cxl_root_ops { 646 int (*qos_class)(struct cxl_root *cxl_root, 647 struct access_coordinate *coord, int entries, 648 int *qos_class); 649 }; 650 651 static inline struct cxl_dport * 652 cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev) 653 { 654 return xa_load(&port->dports, (unsigned long)dport_dev); 655 } 656 657 struct cxl_rcrb_info { 658 resource_size_t base; 659 u16 aer_cap; 660 }; 661 662 /** 663 * struct cxl_dport - CXL downstream port 664 * @dport_dev: PCI bridge or firmware device representing the downstream link 665 * @reg_map: component and ras register mapping parameters 666 * @port_id: unique hardware identifier for dport in decoder target list 667 * @rcrb: Data about the Root Complex Register Block layout 668 * @rch: Indicate whether this dport was enumerated in RCH or VH mode 669 * @port: reference to cxl_port that contains this downstream port 670 * @regs: Dport parsed register blocks 671 * @coord: access coordinates (bandwidth and latency performance attributes) 672 * @link_latency: calculated PCIe downstream latency 673 */ 674 struct cxl_dport { 675 struct device *dport_dev; 676 struct cxl_register_map reg_map; 677 int port_id; 678 struct cxl_rcrb_info rcrb; 679 bool rch; 680 struct cxl_port *port; 681 struct cxl_regs regs; 682 struct access_coordinate coord[ACCESS_COORDINATE_MAX]; 683 long link_latency; 684 }; 685 686 /** 687 * struct cxl_ep - track an endpoint's interest in a port 688 * @ep: device that hosts a generic CXL endpoint (expander or accelerator) 689 * @dport: which dport routes to this endpoint on @port 690 * @next: cxl switch port across the link attached to @dport NULL if 691 * attached to an endpoint 692 */ 693 struct cxl_ep { 694 struct device *ep; 695 struct cxl_dport *dport; 696 struct cxl_port *next; 697 }; 698 699 /** 700 * struct cxl_region_ref - track a region's interest in a port 701 * @port: point in topology to install this reference 702 * @decoder: decoder assigned for @region in @port 703 * @region: region for this reference 704 * @endpoints: cxl_ep references for region members beneath @port 705 * @nr_targets_set: track how many targets have been programmed during setup 706 * @nr_eps: number of endpoints beneath @port 707 * @nr_targets: number of distinct targets needed to reach @nr_eps 708 */ 709 struct cxl_region_ref { 710 struct cxl_port *port; 711 struct cxl_decoder *decoder; 712 struct cxl_region *region; 713 struct xarray endpoints; 714 int nr_targets_set; 715 int nr_eps; 716 int nr_targets; 717 }; 718 719 /* 720 * The platform firmware device hosting the root is also the top of the 721 * CXL port topology. All other CXL ports have another CXL port as their 722 * parent and their ->uport_dev / host device is out-of-line of the port 723 * ancestry. 724 */ 725 static inline bool is_cxl_root(struct cxl_port *port) 726 { 727 return port->uport_dev == port->dev.parent; 728 } 729 730 int cxl_num_decoders_committed(struct cxl_port *port); 731 bool is_cxl_port(const struct device *dev); 732 struct cxl_port *to_cxl_port(const struct device *dev); 733 struct pci_bus; 734 int devm_cxl_register_pci_bus(struct device *host, struct device *uport_dev, 735 struct pci_bus *bus); 736 struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port); 737 struct cxl_port *devm_cxl_add_port(struct device *host, 738 struct device *uport_dev, 739 resource_size_t component_reg_phys, 740 struct cxl_dport *parent_dport); 741 struct cxl_root *devm_cxl_add_root(struct device *host, 742 const struct cxl_root_ops *ops); 743 struct cxl_root *find_cxl_root(struct cxl_port *port); 744 void put_cxl_root(struct cxl_root *cxl_root); 745 DEFINE_FREE(put_cxl_root, struct cxl_root *, if (_T) put_cxl_root(_T)) 746 747 int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); 748 void cxl_bus_rescan(void); 749 void cxl_bus_drain(void); 750 struct cxl_port *cxl_pci_find_port(struct pci_dev *pdev, 751 struct cxl_dport **dport); 752 struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd, 753 struct cxl_dport **dport); 754 bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd); 755 756 struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, 757 struct device *dport, int port_id, 758 resource_size_t component_reg_phys); 759 struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, 760 struct device *dport_dev, int port_id, 761 resource_size_t rcrb); 762 763 #ifdef CONFIG_PCIEAER_CXL 764 void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport); 765 #else 766 static inline void cxl_setup_parent_dport(struct device *host, 767 struct cxl_dport *dport) { } 768 #endif 769 770 struct cxl_decoder *to_cxl_decoder(struct device *dev); 771 struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev); 772 struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev); 773 struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev); 774 bool is_root_decoder(struct device *dev); 775 bool is_switch_decoder(struct device *dev); 776 bool is_endpoint_decoder(struct device *dev); 777 struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, 778 unsigned int nr_targets); 779 struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port, 780 unsigned int nr_targets); 781 int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map); 782 struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port); 783 int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map); 784 int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld); 785 static inline int cxl_root_decoder_autoremove(struct device *host, 786 struct cxl_root_decoder *cxlrd) 787 { 788 return cxl_decoder_autoremove(host, &cxlrd->cxlsd.cxld); 789 } 790 int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint); 791 792 /** 793 * struct cxl_endpoint_dvsec_info - Cached DVSEC info 794 * @mem_enabled: cached value of mem_enabled in the DVSEC at init time 795 * @ranges: Number of active HDM ranges this device uses. 796 * @port: endpoint port associated with this info instance 797 * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE 798 */ 799 struct cxl_endpoint_dvsec_info { 800 bool mem_enabled; 801 int ranges; 802 struct cxl_port *port; 803 struct range dvsec_range[2]; 804 }; 805 806 struct cxl_hdm; 807 struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port, 808 struct cxl_endpoint_dvsec_info *info); 809 int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm, 810 struct cxl_endpoint_dvsec_info *info); 811 int devm_cxl_add_passthrough_decoder(struct cxl_port *port); 812 int cxl_dvsec_rr_decode(struct device *dev, int dvsec, 813 struct cxl_endpoint_dvsec_info *info); 814 815 bool is_cxl_region(struct device *dev); 816 817 extern struct bus_type cxl_bus_type; 818 819 struct cxl_driver { 820 const char *name; 821 int (*probe)(struct device *dev); 822 void (*remove)(struct device *dev); 823 struct device_driver drv; 824 int id; 825 }; 826 827 #define to_cxl_drv(__drv) container_of_const(__drv, struct cxl_driver, drv) 828 829 int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner, 830 const char *modname); 831 #define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME) 832 void cxl_driver_unregister(struct cxl_driver *cxl_drv); 833 834 #define module_cxl_driver(__cxl_driver) \ 835 module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister) 836 837 #define CXL_DEVICE_NVDIMM_BRIDGE 1 838 #define CXL_DEVICE_NVDIMM 2 839 #define CXL_DEVICE_PORT 3 840 #define CXL_DEVICE_ROOT 4 841 #define CXL_DEVICE_MEMORY_EXPANDER 5 842 #define CXL_DEVICE_REGION 6 843 #define CXL_DEVICE_PMEM_REGION 7 844 #define CXL_DEVICE_DAX_REGION 8 845 #define CXL_DEVICE_PMU 9 846 847 #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*") 848 #define CXL_MODALIAS_FMT "cxl:t%d" 849 850 struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev); 851 struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host, 852 struct cxl_port *port); 853 struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev); 854 bool is_cxl_nvdimm(struct device *dev); 855 bool is_cxl_nvdimm_bridge(struct device *dev); 856 int devm_cxl_add_nvdimm(struct cxl_port *parent_port, struct cxl_memdev *cxlmd); 857 struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_port *port); 858 859 #ifdef CONFIG_CXL_REGION 860 bool is_cxl_pmem_region(struct device *dev); 861 struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev); 862 int cxl_add_to_region(struct cxl_port *root, 863 struct cxl_endpoint_decoder *cxled); 864 struct cxl_dax_region *to_cxl_dax_region(struct device *dev); 865 #else 866 static inline bool is_cxl_pmem_region(struct device *dev) 867 { 868 return false; 869 } 870 static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev) 871 { 872 return NULL; 873 } 874 static inline int cxl_add_to_region(struct cxl_port *root, 875 struct cxl_endpoint_decoder *cxled) 876 { 877 return 0; 878 } 879 static inline struct cxl_dax_region *to_cxl_dax_region(struct device *dev) 880 { 881 return NULL; 882 } 883 #endif 884 885 void cxl_endpoint_parse_cdat(struct cxl_port *port); 886 void cxl_switch_parse_cdat(struct cxl_port *port); 887 888 int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, 889 struct access_coordinate *coord); 890 void cxl_region_perf_data_calculate(struct cxl_region *cxlr, 891 struct cxl_endpoint_decoder *cxled); 892 893 void cxl_memdev_update_perf(struct cxl_memdev *cxlmd); 894 895 void cxl_coordinates_combine(struct access_coordinate *out, 896 struct access_coordinate *c1, 897 struct access_coordinate *c2); 898 899 bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port); 900 901 /* 902 * Unit test builds overrides this to __weak, find the 'strong' version 903 * of these symbols in tools/testing/cxl/. 904 */ 905 #ifndef __mock 906 #define __mock static 907 #endif 908 909 #endif /* __CXL_H__ */ 910