1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020 Intel Corporation. */ 3 4 #ifndef __CXL_H__ 5 #define __CXL_H__ 6 7 #include <linux/libnvdimm.h> 8 #include <linux/bitfield.h> 9 #include <linux/bitops.h> 10 #include <linux/log2.h> 11 #include <linux/node.h> 12 #include <linux/io.h> 13 14 /** 15 * DOC: cxl objects 16 * 17 * The CXL core objects like ports, decoders, and regions are shared 18 * between the subsystem drivers cxl_acpi, cxl_pci, and core drivers 19 * (port-driver, region-driver, nvdimm object-drivers... etc). 20 */ 21 22 /* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */ 23 #define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K 24 25 /* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/ 26 #define CXL_CM_OFFSET 0x1000 27 #define CXL_CM_CAP_HDR_OFFSET 0x0 28 #define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0) 29 #define CM_CAP_HDR_CAP_ID 1 30 #define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16) 31 #define CM_CAP_HDR_CAP_VERSION 1 32 #define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20) 33 #define CM_CAP_HDR_CACHE_MEM_VERSION 1 34 #define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24) 35 #define CXL_CM_CAP_PTR_MASK GENMASK(31, 20) 36 37 #define CXL_CM_CAP_CAP_ID_RAS 0x2 38 #define CXL_CM_CAP_CAP_ID_HDM 0x5 39 #define CXL_CM_CAP_CAP_HDM_VERSION 1 40 41 /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */ 42 #define CXL_HDM_DECODER_CAP_OFFSET 0x0 43 #define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0) 44 #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4) 45 #define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8) 46 #define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9) 47 #define CXL_HDM_DECODER_CTRL_OFFSET 0x4 48 #define CXL_HDM_DECODER_ENABLE BIT(1) 49 #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10) 50 #define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14) 51 #define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18) 52 #define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c) 53 #define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20) 54 #define CXL_HDM_DECODER0_CTRL_IG_MASK GENMASK(3, 0) 55 #define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4) 56 #define CXL_HDM_DECODER0_CTRL_LOCK BIT(8) 57 #define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9) 58 #define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10) 59 #define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11) 60 #define CXL_HDM_DECODER0_CTRL_HOSTONLY BIT(12) 61 #define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24) 62 #define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28) 63 #define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i) 64 #define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i) 65 66 /* HDM decoder control register constants CXL 3.0 8.2.5.19.7 */ 67 #define CXL_DECODER_MIN_GRANULARITY 256 68 #define CXL_DECODER_MAX_ENCODED_IG 6 69 70 static inline int cxl_hdm_decoder_count(u32 cap_hdr) 71 { 72 int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr); 73 74 return val ? val * 2 : 1; 75 } 76 77 /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ 78 static inline int eig_to_granularity(u16 eig, unsigned int *granularity) 79 { 80 if (eig > CXL_DECODER_MAX_ENCODED_IG) 81 return -EINVAL; 82 *granularity = CXL_DECODER_MIN_GRANULARITY << eig; 83 return 0; 84 } 85 86 /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */ 87 static inline int eiw_to_ways(u8 eiw, unsigned int *ways) 88 { 89 switch (eiw) { 90 case 0 ... 4: 91 *ways = 1 << eiw; 92 break; 93 case 8 ... 10: 94 *ways = 3 << (eiw - 8); 95 break; 96 default: 97 return -EINVAL; 98 } 99 100 return 0; 101 } 102 103 static inline int granularity_to_eig(int granularity, u16 *eig) 104 { 105 if (granularity > SZ_16K || granularity < CXL_DECODER_MIN_GRANULARITY || 106 !is_power_of_2(granularity)) 107 return -EINVAL; 108 *eig = ilog2(granularity) - 8; 109 return 0; 110 } 111 112 static inline int ways_to_eiw(unsigned int ways, u8 *eiw) 113 { 114 if (ways > 16) 115 return -EINVAL; 116 if (is_power_of_2(ways)) { 117 *eiw = ilog2(ways); 118 return 0; 119 } 120 if (ways % 3) 121 return -EINVAL; 122 ways /= 3; 123 if (!is_power_of_2(ways)) 124 return -EINVAL; 125 *eiw = ilog2(ways) + 8; 126 return 0; 127 } 128 129 /* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */ 130 #define CXL_RAS_UNCORRECTABLE_STATUS_OFFSET 0x0 131 #define CXL_RAS_UNCORRECTABLE_STATUS_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 132 #define CXL_RAS_UNCORRECTABLE_MASK_OFFSET 0x4 133 #define CXL_RAS_UNCORRECTABLE_MASK_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 134 #define CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK BIT(8) 135 #define CXL_RAS_UNCORRECTABLE_SEVERITY_OFFSET 0x8 136 #define CXL_RAS_UNCORRECTABLE_SEVERITY_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 137 #define CXL_RAS_CORRECTABLE_STATUS_OFFSET 0xC 138 #define CXL_RAS_CORRECTABLE_STATUS_MASK GENMASK(6, 0) 139 #define CXL_RAS_CORRECTABLE_MASK_OFFSET 0x10 140 #define CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0) 141 #define CXL_RAS_CAP_CONTROL_OFFSET 0x14 142 #define CXL_RAS_CAP_CONTROL_FE_MASK GENMASK(5, 0) 143 #define CXL_RAS_HEADER_LOG_OFFSET 0x18 144 #define CXL_RAS_CAPABILITY_LENGTH 0x58 145 #define CXL_HEADERLOG_SIZE SZ_512 146 #define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32) 147 148 /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ 149 #define CXLDEV_CAP_ARRAY_OFFSET 0x0 150 #define CXLDEV_CAP_ARRAY_CAP_ID 0 151 #define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0) 152 #define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32) 153 /* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */ 154 #define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0) 155 /* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */ 156 #define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1 157 #define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2 158 #define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3 159 #define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000 160 161 /* CXL 3.0 8.2.8.3.1 Event Status Register */ 162 #define CXLDEV_DEV_EVENT_STATUS_OFFSET 0x00 163 #define CXLDEV_EVENT_STATUS_INFO BIT(0) 164 #define CXLDEV_EVENT_STATUS_WARN BIT(1) 165 #define CXLDEV_EVENT_STATUS_FAIL BIT(2) 166 #define CXLDEV_EVENT_STATUS_FATAL BIT(3) 167 168 #define CXLDEV_EVENT_STATUS_ALL (CXLDEV_EVENT_STATUS_INFO | \ 169 CXLDEV_EVENT_STATUS_WARN | \ 170 CXLDEV_EVENT_STATUS_FAIL | \ 171 CXLDEV_EVENT_STATUS_FATAL) 172 173 /* CXL rev 3.0 section 8.2.9.2.4; Table 8-52 */ 174 #define CXLDEV_EVENT_INT_MODE_MASK GENMASK(1, 0) 175 #define CXLDEV_EVENT_INT_MSGNUM_MASK GENMASK(7, 4) 176 177 /* CXL 2.0 8.2.8.4 Mailbox Registers */ 178 #define CXLDEV_MBOX_CAPS_OFFSET 0x00 179 #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0) 180 #define CXLDEV_MBOX_CAP_BG_CMD_IRQ BIT(6) 181 #define CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK GENMASK(10, 7) 182 #define CXLDEV_MBOX_CTRL_OFFSET 0x04 183 #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0) 184 #define CXLDEV_MBOX_CTRL_BG_CMD_IRQ BIT(2) 185 #define CXLDEV_MBOX_CMD_OFFSET 0x08 186 #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) 187 #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16) 188 #define CXLDEV_MBOX_STATUS_OFFSET 0x10 189 #define CXLDEV_MBOX_STATUS_BG_CMD BIT(0) 190 #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32) 191 #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18 192 #define CXLDEV_MBOX_BG_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) 193 #define CXLDEV_MBOX_BG_CMD_COMMAND_PCT_MASK GENMASK_ULL(22, 16) 194 #define CXLDEV_MBOX_BG_CMD_COMMAND_RC_MASK GENMASK_ULL(47, 32) 195 #define CXLDEV_MBOX_BG_CMD_COMMAND_VENDOR_MASK GENMASK_ULL(63, 48) 196 #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20 197 198 /* 199 * Using struct_group() allows for per register-block-type helper routines, 200 * without requiring block-type agnostic code to include the prefix. 201 */ 202 struct cxl_regs { 203 /* 204 * Common set of CXL Component register block base pointers 205 * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure 206 * @ras: CXL 2.0 8.2.5.9 CXL RAS Capability Structure 207 */ 208 struct_group_tagged(cxl_component_regs, component, 209 void __iomem *hdm_decoder; 210 void __iomem *ras; 211 ); 212 /* 213 * Common set of CXL Device register block base pointers 214 * @status: CXL 2.0 8.2.8.3 Device Status Registers 215 * @mbox: CXL 2.0 8.2.8.4 Mailbox Registers 216 * @memdev: CXL 2.0 8.2.8.5 Memory Device Registers 217 */ 218 struct_group_tagged(cxl_device_regs, device_regs, 219 void __iomem *status, *mbox, *memdev; 220 ); 221 222 struct_group_tagged(cxl_pmu_regs, pmu_regs, 223 void __iomem *pmu; 224 ); 225 226 /* 227 * RCH downstream port specific RAS register 228 * @aer: CXL 3.0 8.2.1.1 RCH Downstream Port RCRB 229 */ 230 struct_group_tagged(cxl_rch_regs, rch_regs, 231 void __iomem *dport_aer; 232 ); 233 }; 234 235 struct cxl_reg_map { 236 bool valid; 237 int id; 238 unsigned long offset; 239 unsigned long size; 240 }; 241 242 struct cxl_component_reg_map { 243 struct cxl_reg_map hdm_decoder; 244 struct cxl_reg_map ras; 245 }; 246 247 struct cxl_device_reg_map { 248 struct cxl_reg_map status; 249 struct cxl_reg_map mbox; 250 struct cxl_reg_map memdev; 251 }; 252 253 struct cxl_pmu_reg_map { 254 struct cxl_reg_map pmu; 255 }; 256 257 /** 258 * struct cxl_register_map - DVSEC harvested register block mapping parameters 259 * @host: device for devm operations and logging 260 * @base: virtual base of the register-block-BAR + @block_offset 261 * @resource: physical resource base of the register block 262 * @max_size: maximum mapping size to perform register search 263 * @reg_type: see enum cxl_regloc_type 264 * @component_map: cxl_reg_map for component registers 265 * @device_map: cxl_reg_maps for device registers 266 * @pmu_map: cxl_reg_maps for CXL Performance Monitoring Units 267 */ 268 struct cxl_register_map { 269 struct device *host; 270 void __iomem *base; 271 resource_size_t resource; 272 resource_size_t max_size; 273 u8 reg_type; 274 union { 275 struct cxl_component_reg_map component_map; 276 struct cxl_device_reg_map device_map; 277 struct cxl_pmu_reg_map pmu_map; 278 }; 279 }; 280 281 void cxl_probe_component_regs(struct device *dev, void __iomem *base, 282 struct cxl_component_reg_map *map); 283 void cxl_probe_device_regs(struct device *dev, void __iomem *base, 284 struct cxl_device_reg_map *map); 285 int cxl_map_component_regs(const struct cxl_register_map *map, 286 struct cxl_component_regs *regs, 287 unsigned long map_mask); 288 int cxl_map_device_regs(const struct cxl_register_map *map, 289 struct cxl_device_regs *regs); 290 int cxl_map_pmu_regs(struct cxl_register_map *map, struct cxl_pmu_regs *regs); 291 292 enum cxl_regloc_type; 293 int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type); 294 int cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type, 295 struct cxl_register_map *map, int index); 296 int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, 297 struct cxl_register_map *map); 298 int cxl_setup_regs(struct cxl_register_map *map); 299 struct cxl_dport; 300 resource_size_t cxl_rcd_component_reg_phys(struct device *dev, 301 struct cxl_dport *dport); 302 303 #define CXL_RESOURCE_NONE ((resource_size_t) -1) 304 #define CXL_TARGET_STRLEN 20 305 306 /* 307 * cxl_decoder flags that define the type of memory / devices this 308 * decoder supports as well as configuration lock status See "CXL 2.0 309 * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details. 310 * Additionally indicate whether decoder settings were autodetected, 311 * user customized. 312 */ 313 #define CXL_DECODER_F_RAM BIT(0) 314 #define CXL_DECODER_F_PMEM BIT(1) 315 #define CXL_DECODER_F_TYPE2 BIT(2) 316 #define CXL_DECODER_F_TYPE3 BIT(3) 317 #define CXL_DECODER_F_LOCK BIT(4) 318 #define CXL_DECODER_F_ENABLE BIT(5) 319 #define CXL_DECODER_F_MASK GENMASK(5, 0) 320 321 enum cxl_decoder_type { 322 CXL_DECODER_DEVMEM = 2, 323 CXL_DECODER_HOSTONLYMEM = 3, 324 }; 325 326 /* 327 * Current specification goes up to 8, double that seems a reasonable 328 * software max for the foreseeable future 329 */ 330 #define CXL_DECODER_MAX_INTERLEAVE 16 331 332 #define CXL_QOS_CLASS_INVALID -1 333 334 /** 335 * struct cxl_decoder - Common CXL HDM Decoder Attributes 336 * @dev: this decoder's device 337 * @id: kernel device name id 338 * @hpa_range: Host physical address range mapped by this decoder 339 * @interleave_ways: number of cxl_dports in this decode 340 * @interleave_granularity: data stride per dport 341 * @target_type: accelerator vs expander (type2 vs type3) selector 342 * @region: currently assigned region for this decoder 343 * @flags: memory type capabilities and locking 344 * @commit: device/decoder-type specific callback to commit settings to hw 345 * @reset: device/decoder-type specific callback to reset hw settings 346 */ 347 struct cxl_decoder { 348 struct device dev; 349 int id; 350 struct range hpa_range; 351 int interleave_ways; 352 int interleave_granularity; 353 enum cxl_decoder_type target_type; 354 struct cxl_region *region; 355 unsigned long flags; 356 int (*commit)(struct cxl_decoder *cxld); 357 int (*reset)(struct cxl_decoder *cxld); 358 }; 359 360 /* 361 * CXL_DECODER_DEAD prevents endpoints from being reattached to regions 362 * while cxld_unregister() is running 363 */ 364 enum cxl_decoder_mode { 365 CXL_DECODER_NONE, 366 CXL_DECODER_RAM, 367 CXL_DECODER_PMEM, 368 CXL_DECODER_MIXED, 369 CXL_DECODER_DEAD, 370 }; 371 372 static inline const char *cxl_decoder_mode_name(enum cxl_decoder_mode mode) 373 { 374 static const char * const names[] = { 375 [CXL_DECODER_NONE] = "none", 376 [CXL_DECODER_RAM] = "ram", 377 [CXL_DECODER_PMEM] = "pmem", 378 [CXL_DECODER_MIXED] = "mixed", 379 }; 380 381 if (mode >= CXL_DECODER_NONE && mode <= CXL_DECODER_MIXED) 382 return names[mode]; 383 return "mixed"; 384 } 385 386 /* 387 * Track whether this decoder is reserved for region autodiscovery, or 388 * free for userspace provisioning. 389 */ 390 enum cxl_decoder_state { 391 CXL_DECODER_STATE_MANUAL, 392 CXL_DECODER_STATE_AUTO, 393 }; 394 395 /** 396 * struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder 397 * @cxld: base cxl_decoder_object 398 * @dpa_res: actively claimed DPA span of this decoder 399 * @skip: offset into @dpa_res where @cxld.hpa_range maps 400 * @mode: which memory type / access-mode-partition this decoder targets 401 * @state: autodiscovery state 402 * @pos: interleave position in @cxld.region 403 */ 404 struct cxl_endpoint_decoder { 405 struct cxl_decoder cxld; 406 struct resource *dpa_res; 407 resource_size_t skip; 408 enum cxl_decoder_mode mode; 409 enum cxl_decoder_state state; 410 int pos; 411 }; 412 413 /** 414 * struct cxl_switch_decoder - Switch specific CXL HDM Decoder 415 * @cxld: base cxl_decoder object 416 * @nr_targets: number of elements in @target 417 * @target: active ordered target list in current decoder configuration 418 * 419 * The 'switch' decoder type represents the decoder instances of cxl_port's that 420 * route from the root of a CXL memory decode topology to the endpoints. They 421 * come in two flavors, root-level decoders, statically defined by platform 422 * firmware, and mid-level decoders, where interleave-granularity, 423 * interleave-width, and the target list are mutable. 424 */ 425 struct cxl_switch_decoder { 426 struct cxl_decoder cxld; 427 int nr_targets; 428 struct cxl_dport *target[]; 429 }; 430 431 struct cxl_root_decoder; 432 typedef struct cxl_dport *(*cxl_calc_hb_fn)(struct cxl_root_decoder *cxlrd, 433 int pos); 434 435 /** 436 * struct cxl_root_decoder - Static platform CXL address decoder 437 * @res: host / parent resource for region allocations 438 * @region_id: region id for next region provisioning event 439 * @calc_hb: which host bridge covers the n'th position by granularity 440 * @platform_data: platform specific configuration data 441 * @range_lock: sync region autodiscovery by address range 442 * @qos_class: QoS performance class cookie 443 * @cxlsd: base cxl switch decoder 444 */ 445 struct cxl_root_decoder { 446 struct resource *res; 447 atomic_t region_id; 448 cxl_calc_hb_fn calc_hb; 449 void *platform_data; 450 struct mutex range_lock; 451 int qos_class; 452 struct cxl_switch_decoder cxlsd; 453 }; 454 455 /* 456 * enum cxl_config_state - State machine for region configuration 457 * @CXL_CONFIG_IDLE: Any sysfs attribute can be written freely 458 * @CXL_CONFIG_INTERLEAVE_ACTIVE: region size has been set, no more 459 * changes to interleave_ways or interleave_granularity 460 * @CXL_CONFIG_ACTIVE: All targets have been added the region is now 461 * active 462 * @CXL_CONFIG_RESET_PENDING: see commit_store() 463 * @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware 464 */ 465 enum cxl_config_state { 466 CXL_CONFIG_IDLE, 467 CXL_CONFIG_INTERLEAVE_ACTIVE, 468 CXL_CONFIG_ACTIVE, 469 CXL_CONFIG_RESET_PENDING, 470 CXL_CONFIG_COMMIT, 471 }; 472 473 /** 474 * struct cxl_region_params - region settings 475 * @state: allow the driver to lockdown further parameter changes 476 * @uuid: unique id for persistent regions 477 * @interleave_ways: number of endpoints in the region 478 * @interleave_granularity: capacity each endpoint contributes to a stripe 479 * @res: allocated iomem capacity for this region 480 * @targets: active ordered targets in current decoder configuration 481 * @nr_targets: number of targets 482 * 483 * State transitions are protected by the cxl_region_rwsem 484 */ 485 struct cxl_region_params { 486 enum cxl_config_state state; 487 uuid_t uuid; 488 int interleave_ways; 489 int interleave_granularity; 490 struct resource *res; 491 struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE]; 492 int nr_targets; 493 }; 494 495 /* 496 * Indicate whether this region has been assembled by autodetection or 497 * userspace assembly. Prevent endpoint decoders outside of automatic 498 * detection from being added to the region. 499 */ 500 #define CXL_REGION_F_AUTO 0 501 502 /* 503 * Require that a committed region successfully complete a teardown once 504 * any of its associated decoders have been torn down. This maintains 505 * the commit state for the region since there are committed decoders, 506 * but blocks cxl_region_probe(). 507 */ 508 #define CXL_REGION_F_NEEDS_RESET 1 509 510 /** 511 * struct cxl_region - CXL region 512 * @dev: This region's device 513 * @id: This region's id. Id is globally unique across all regions 514 * @mode: Endpoint decoder allocation / access mode 515 * @type: Endpoint decoder target type 516 * @cxl_nvb: nvdimm bridge for coordinating @cxlr_pmem setup / shutdown 517 * @cxlr_pmem: (for pmem regions) cached copy of the nvdimm bridge 518 * @flags: Region state flags 519 * @params: active + config params for the region 520 * @coord: QoS access coordinates for the region 521 */ 522 struct cxl_region { 523 struct device dev; 524 int id; 525 enum cxl_decoder_mode mode; 526 enum cxl_decoder_type type; 527 struct cxl_nvdimm_bridge *cxl_nvb; 528 struct cxl_pmem_region *cxlr_pmem; 529 unsigned long flags; 530 struct cxl_region_params params; 531 struct access_coordinate coord[ACCESS_COORDINATE_MAX]; 532 }; 533 534 struct cxl_nvdimm_bridge { 535 int id; 536 struct device dev; 537 struct cxl_port *port; 538 struct nvdimm_bus *nvdimm_bus; 539 struct nvdimm_bus_descriptor nd_desc; 540 }; 541 542 #define CXL_DEV_ID_LEN 19 543 544 struct cxl_nvdimm { 545 struct device dev; 546 struct cxl_memdev *cxlmd; 547 u8 dev_id[CXL_DEV_ID_LEN]; /* for nvdimm, string of 'serial' */ 548 }; 549 550 struct cxl_pmem_region_mapping { 551 struct cxl_memdev *cxlmd; 552 struct cxl_nvdimm *cxl_nvd; 553 u64 start; 554 u64 size; 555 int position; 556 }; 557 558 struct cxl_pmem_region { 559 struct device dev; 560 struct cxl_region *cxlr; 561 struct nd_region *nd_region; 562 struct range hpa_range; 563 int nr_mappings; 564 struct cxl_pmem_region_mapping mapping[]; 565 }; 566 567 struct cxl_dax_region { 568 struct device dev; 569 struct cxl_region *cxlr; 570 struct range hpa_range; 571 }; 572 573 /** 574 * struct cxl_port - logical collection of upstream port devices and 575 * downstream port devices to construct a CXL memory 576 * decode hierarchy. 577 * @dev: this port's device 578 * @uport_dev: PCI or platform device implementing the upstream port capability 579 * @host_bridge: Shortcut to the platform attach point for this port 580 * @id: id for port device-name 581 * @dports: cxl_dport instances referenced by decoders 582 * @endpoints: cxl_ep instances, endpoints that are a descendant of this port 583 * @regions: cxl_region_ref instances, regions mapped by this port 584 * @parent_dport: dport that points to this port in the parent 585 * @decoder_ida: allocator for decoder ids 586 * @reg_map: component and ras register mapping parameters 587 * @nr_dports: number of entries in @dports 588 * @hdm_end: track last allocated HDM decoder instance for allocation ordering 589 * @commit_end: cursor to track highest committed decoder for commit ordering 590 * @dead: last ep has been removed, force port re-creation 591 * @depth: How deep this port is relative to the root. depth 0 is the root. 592 * @cdat: Cached CDAT data 593 * @cdat_available: Should a CDAT attribute be available in sysfs 594 * @pci_latency: Upstream latency in picoseconds 595 */ 596 struct cxl_port { 597 struct device dev; 598 struct device *uport_dev; 599 struct device *host_bridge; 600 int id; 601 struct xarray dports; 602 struct xarray endpoints; 603 struct xarray regions; 604 struct cxl_dport *parent_dport; 605 struct ida decoder_ida; 606 struct cxl_register_map reg_map; 607 int nr_dports; 608 int hdm_end; 609 int commit_end; 610 bool dead; 611 unsigned int depth; 612 struct cxl_cdat { 613 void *table; 614 size_t length; 615 } cdat; 616 bool cdat_available; 617 long pci_latency; 618 }; 619 620 /** 621 * struct cxl_root - logical collection of root cxl_port items 622 * 623 * @port: cxl_port member 624 * @ops: cxl root operations 625 */ 626 struct cxl_root { 627 struct cxl_port port; 628 const struct cxl_root_ops *ops; 629 }; 630 631 static inline struct cxl_root * 632 to_cxl_root(const struct cxl_port *port) 633 { 634 return container_of(port, struct cxl_root, port); 635 } 636 637 struct cxl_root_ops { 638 int (*qos_class)(struct cxl_root *cxl_root, 639 struct access_coordinate *coord, int entries, 640 int *qos_class); 641 }; 642 643 static inline struct cxl_dport * 644 cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev) 645 { 646 return xa_load(&port->dports, (unsigned long)dport_dev); 647 } 648 649 struct cxl_rcrb_info { 650 resource_size_t base; 651 u16 aer_cap; 652 }; 653 654 /** 655 * struct cxl_dport - CXL downstream port 656 * @dport_dev: PCI bridge or firmware device representing the downstream link 657 * @reg_map: component and ras register mapping parameters 658 * @port_id: unique hardware identifier for dport in decoder target list 659 * @rcrb: Data about the Root Complex Register Block layout 660 * @rch: Indicate whether this dport was enumerated in RCH or VH mode 661 * @port: reference to cxl_port that contains this downstream port 662 * @regs: Dport parsed register blocks 663 * @sw_coord: access coordinates (performance) for switch from CDAT 664 * @hb_coord: access coordinates (performance) from ACPI generic port (host bridge) 665 * @link_latency: calculated PCIe downstream latency 666 */ 667 struct cxl_dport { 668 struct device *dport_dev; 669 struct cxl_register_map reg_map; 670 int port_id; 671 struct cxl_rcrb_info rcrb; 672 bool rch; 673 struct cxl_port *port; 674 struct cxl_regs regs; 675 struct access_coordinate sw_coord; 676 struct access_coordinate hb_coord[ACCESS_COORDINATE_MAX]; 677 long link_latency; 678 }; 679 680 /** 681 * struct cxl_ep - track an endpoint's interest in a port 682 * @ep: device that hosts a generic CXL endpoint (expander or accelerator) 683 * @dport: which dport routes to this endpoint on @port 684 * @next: cxl switch port across the link attached to @dport NULL if 685 * attached to an endpoint 686 */ 687 struct cxl_ep { 688 struct device *ep; 689 struct cxl_dport *dport; 690 struct cxl_port *next; 691 }; 692 693 /** 694 * struct cxl_region_ref - track a region's interest in a port 695 * @port: point in topology to install this reference 696 * @decoder: decoder assigned for @region in @port 697 * @region: region for this reference 698 * @endpoints: cxl_ep references for region members beneath @port 699 * @nr_targets_set: track how many targets have been programmed during setup 700 * @nr_eps: number of endpoints beneath @port 701 * @nr_targets: number of distinct targets needed to reach @nr_eps 702 */ 703 struct cxl_region_ref { 704 struct cxl_port *port; 705 struct cxl_decoder *decoder; 706 struct cxl_region *region; 707 struct xarray endpoints; 708 int nr_targets_set; 709 int nr_eps; 710 int nr_targets; 711 }; 712 713 /* 714 * The platform firmware device hosting the root is also the top of the 715 * CXL port topology. All other CXL ports have another CXL port as their 716 * parent and their ->uport_dev / host device is out-of-line of the port 717 * ancestry. 718 */ 719 static inline bool is_cxl_root(struct cxl_port *port) 720 { 721 return port->uport_dev == port->dev.parent; 722 } 723 724 int cxl_num_decoders_committed(struct cxl_port *port); 725 bool is_cxl_port(const struct device *dev); 726 struct cxl_port *to_cxl_port(const struct device *dev); 727 struct pci_bus; 728 int devm_cxl_register_pci_bus(struct device *host, struct device *uport_dev, 729 struct pci_bus *bus); 730 struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port); 731 struct cxl_port *devm_cxl_add_port(struct device *host, 732 struct device *uport_dev, 733 resource_size_t component_reg_phys, 734 struct cxl_dport *parent_dport); 735 struct cxl_root *devm_cxl_add_root(struct device *host, 736 const struct cxl_root_ops *ops); 737 struct cxl_root *find_cxl_root(struct cxl_port *port); 738 void put_cxl_root(struct cxl_root *cxl_root); 739 DEFINE_FREE(put_cxl_root, struct cxl_root *, if (_T) put_cxl_root(_T)) 740 741 int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); 742 void cxl_bus_rescan(void); 743 void cxl_bus_drain(void); 744 struct cxl_port *cxl_pci_find_port(struct pci_dev *pdev, 745 struct cxl_dport **dport); 746 struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd, 747 struct cxl_dport **dport); 748 bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd); 749 750 struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, 751 struct device *dport, int port_id, 752 resource_size_t component_reg_phys); 753 struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, 754 struct device *dport_dev, int port_id, 755 resource_size_t rcrb); 756 757 #ifdef CONFIG_PCIEAER_CXL 758 void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport); 759 #else 760 static inline void cxl_setup_parent_dport(struct device *host, 761 struct cxl_dport *dport) { } 762 #endif 763 764 struct cxl_decoder *to_cxl_decoder(struct device *dev); 765 struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev); 766 struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev); 767 struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev); 768 bool is_root_decoder(struct device *dev); 769 bool is_switch_decoder(struct device *dev); 770 bool is_endpoint_decoder(struct device *dev); 771 struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, 772 unsigned int nr_targets, 773 cxl_calc_hb_fn calc_hb); 774 struct cxl_dport *cxl_hb_modulo(struct cxl_root_decoder *cxlrd, int pos); 775 struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port, 776 unsigned int nr_targets); 777 int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map); 778 struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port); 779 int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map); 780 int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld); 781 int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint); 782 783 /** 784 * struct cxl_endpoint_dvsec_info - Cached DVSEC info 785 * @mem_enabled: cached value of mem_enabled in the DVSEC at init time 786 * @ranges: Number of active HDM ranges this device uses. 787 * @port: endpoint port associated with this info instance 788 * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE 789 */ 790 struct cxl_endpoint_dvsec_info { 791 bool mem_enabled; 792 int ranges; 793 struct cxl_port *port; 794 struct range dvsec_range[2]; 795 }; 796 797 struct cxl_hdm; 798 struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port, 799 struct cxl_endpoint_dvsec_info *info); 800 int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm, 801 struct cxl_endpoint_dvsec_info *info); 802 int devm_cxl_add_passthrough_decoder(struct cxl_port *port); 803 int cxl_dvsec_rr_decode(struct device *dev, int dvsec, 804 struct cxl_endpoint_dvsec_info *info); 805 806 bool is_cxl_region(struct device *dev); 807 808 extern struct bus_type cxl_bus_type; 809 810 struct cxl_driver { 811 const char *name; 812 int (*probe)(struct device *dev); 813 void (*remove)(struct device *dev); 814 struct device_driver drv; 815 int id; 816 }; 817 818 static inline struct cxl_driver *to_cxl_drv(struct device_driver *drv) 819 { 820 return container_of(drv, struct cxl_driver, drv); 821 } 822 823 int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner, 824 const char *modname); 825 #define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME) 826 void cxl_driver_unregister(struct cxl_driver *cxl_drv); 827 828 #define module_cxl_driver(__cxl_driver) \ 829 module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister) 830 831 #define CXL_DEVICE_NVDIMM_BRIDGE 1 832 #define CXL_DEVICE_NVDIMM 2 833 #define CXL_DEVICE_PORT 3 834 #define CXL_DEVICE_ROOT 4 835 #define CXL_DEVICE_MEMORY_EXPANDER 5 836 #define CXL_DEVICE_REGION 6 837 #define CXL_DEVICE_PMEM_REGION 7 838 #define CXL_DEVICE_DAX_REGION 8 839 #define CXL_DEVICE_PMU 9 840 841 #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*") 842 #define CXL_MODALIAS_FMT "cxl:t%d" 843 844 struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev); 845 struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host, 846 struct cxl_port *port); 847 struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev); 848 bool is_cxl_nvdimm(struct device *dev); 849 bool is_cxl_nvdimm_bridge(struct device *dev); 850 int devm_cxl_add_nvdimm(struct cxl_memdev *cxlmd); 851 struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd); 852 853 #ifdef CONFIG_CXL_REGION 854 bool is_cxl_pmem_region(struct device *dev); 855 struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev); 856 int cxl_add_to_region(struct cxl_port *root, 857 struct cxl_endpoint_decoder *cxled); 858 struct cxl_dax_region *to_cxl_dax_region(struct device *dev); 859 #else 860 static inline bool is_cxl_pmem_region(struct device *dev) 861 { 862 return false; 863 } 864 static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev) 865 { 866 return NULL; 867 } 868 static inline int cxl_add_to_region(struct cxl_port *root, 869 struct cxl_endpoint_decoder *cxled) 870 { 871 return 0; 872 } 873 static inline struct cxl_dax_region *to_cxl_dax_region(struct device *dev) 874 { 875 return NULL; 876 } 877 #endif 878 879 void cxl_endpoint_parse_cdat(struct cxl_port *port); 880 void cxl_switch_parse_cdat(struct cxl_port *port); 881 882 int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, 883 struct access_coordinate *coord); 884 int cxl_hb_get_perf_coordinates(struct cxl_port *port, 885 struct access_coordinate *coord); 886 void cxl_region_perf_data_calculate(struct cxl_region *cxlr, 887 struct cxl_endpoint_decoder *cxled); 888 889 void cxl_memdev_update_perf(struct cxl_memdev *cxlmd); 890 891 void cxl_coordinates_combine(struct access_coordinate *out, 892 struct access_coordinate *c1, 893 struct access_coordinate *c2); 894 895 /* 896 * Unit test builds overrides this to __weak, find the 'strong' version 897 * of these symbols in tools/testing/cxl/. 898 */ 899 #ifndef __mock 900 #define __mock static 901 #endif 902 903 #endif /* __CXL_H__ */ 904