1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020 Intel Corporation. */ 3 4 #ifndef __CXL_H__ 5 #define __CXL_H__ 6 7 #include <linux/libnvdimm.h> 8 #include <linux/bitfield.h> 9 #include <linux/bitops.h> 10 #include <linux/log2.h> 11 #include <linux/io.h> 12 13 /** 14 * DOC: cxl objects 15 * 16 * The CXL core objects like ports, decoders, and regions are shared 17 * between the subsystem drivers cxl_acpi, cxl_pci, and core drivers 18 * (port-driver, region-driver, nvdimm object-drivers... etc). 19 */ 20 21 /* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */ 22 #define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K 23 24 /* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/ 25 #define CXL_CM_OFFSET 0x1000 26 #define CXL_CM_CAP_HDR_OFFSET 0x0 27 #define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0) 28 #define CM_CAP_HDR_CAP_ID 1 29 #define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16) 30 #define CM_CAP_HDR_CAP_VERSION 1 31 #define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20) 32 #define CM_CAP_HDR_CACHE_MEM_VERSION 1 33 #define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24) 34 #define CXL_CM_CAP_PTR_MASK GENMASK(31, 20) 35 36 #define CXL_CM_CAP_CAP_ID_RAS 0x2 37 #define CXL_CM_CAP_CAP_ID_HDM 0x5 38 #define CXL_CM_CAP_CAP_HDM_VERSION 1 39 40 /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */ 41 #define CXL_HDM_DECODER_CAP_OFFSET 0x0 42 #define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0) 43 #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4) 44 #define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8) 45 #define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9) 46 #define CXL_HDM_DECODER_CTRL_OFFSET 0x4 47 #define CXL_HDM_DECODER_ENABLE BIT(1) 48 #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10) 49 #define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14) 50 #define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18) 51 #define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c) 52 #define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20) 53 #define CXL_HDM_DECODER0_CTRL_IG_MASK GENMASK(3, 0) 54 #define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4) 55 #define CXL_HDM_DECODER0_CTRL_LOCK BIT(8) 56 #define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9) 57 #define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10) 58 #define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11) 59 #define CXL_HDM_DECODER0_CTRL_TYPE BIT(12) 60 #define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24) 61 #define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28) 62 #define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i) 63 #define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i) 64 65 /* HDM decoder control register constants CXL 3.0 8.2.5.19.7 */ 66 #define CXL_DECODER_MIN_GRANULARITY 256 67 #define CXL_DECODER_MAX_ENCODED_IG 6 68 69 static inline int cxl_hdm_decoder_count(u32 cap_hdr) 70 { 71 int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr); 72 73 return val ? val * 2 : 1; 74 } 75 76 /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ 77 static inline int eig_to_granularity(u16 eig, unsigned int *granularity) 78 { 79 if (eig > CXL_DECODER_MAX_ENCODED_IG) 80 return -EINVAL; 81 *granularity = CXL_DECODER_MIN_GRANULARITY << eig; 82 return 0; 83 } 84 85 /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */ 86 static inline int eiw_to_ways(u8 eiw, unsigned int *ways) 87 { 88 switch (eiw) { 89 case 0 ... 4: 90 *ways = 1 << eiw; 91 break; 92 case 8 ... 10: 93 *ways = 3 << (eiw - 8); 94 break; 95 default: 96 return -EINVAL; 97 } 98 99 return 0; 100 } 101 102 static inline int granularity_to_eig(int granularity, u16 *eig) 103 { 104 if (granularity > SZ_16K || granularity < CXL_DECODER_MIN_GRANULARITY || 105 !is_power_of_2(granularity)) 106 return -EINVAL; 107 *eig = ilog2(granularity) - 8; 108 return 0; 109 } 110 111 static inline int ways_to_eiw(unsigned int ways, u8 *eiw) 112 { 113 if (ways > 16) 114 return -EINVAL; 115 if (is_power_of_2(ways)) { 116 *eiw = ilog2(ways); 117 return 0; 118 } 119 if (ways % 3) 120 return -EINVAL; 121 ways /= 3; 122 if (!is_power_of_2(ways)) 123 return -EINVAL; 124 *eiw = ilog2(ways) + 8; 125 return 0; 126 } 127 128 /* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */ 129 #define CXL_RAS_UNCORRECTABLE_STATUS_OFFSET 0x0 130 #define CXL_RAS_UNCORRECTABLE_STATUS_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 131 #define CXL_RAS_UNCORRECTABLE_MASK_OFFSET 0x4 132 #define CXL_RAS_UNCORRECTABLE_MASK_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 133 #define CXL_RAS_UNCORRECTABLE_SEVERITY_OFFSET 0x8 134 #define CXL_RAS_UNCORRECTABLE_SEVERITY_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 135 #define CXL_RAS_CORRECTABLE_STATUS_OFFSET 0xC 136 #define CXL_RAS_CORRECTABLE_STATUS_MASK GENMASK(6, 0) 137 #define CXL_RAS_CORRECTABLE_MASK_OFFSET 0x10 138 #define CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0) 139 #define CXL_RAS_CAP_CONTROL_OFFSET 0x14 140 #define CXL_RAS_CAP_CONTROL_FE_MASK GENMASK(5, 0) 141 #define CXL_RAS_HEADER_LOG_OFFSET 0x18 142 #define CXL_RAS_CAPABILITY_LENGTH 0x58 143 144 /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ 145 #define CXLDEV_CAP_ARRAY_OFFSET 0x0 146 #define CXLDEV_CAP_ARRAY_CAP_ID 0 147 #define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0) 148 #define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32) 149 /* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */ 150 #define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0) 151 /* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */ 152 #define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1 153 #define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2 154 #define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3 155 #define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000 156 157 /* CXL 2.0 8.2.8.4 Mailbox Registers */ 158 #define CXLDEV_MBOX_CAPS_OFFSET 0x00 159 #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0) 160 #define CXLDEV_MBOX_CTRL_OFFSET 0x04 161 #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0) 162 #define CXLDEV_MBOX_CMD_OFFSET 0x08 163 #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) 164 #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16) 165 #define CXLDEV_MBOX_STATUS_OFFSET 0x10 166 #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32) 167 #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18 168 #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20 169 170 /* 171 * Using struct_group() allows for per register-block-type helper routines, 172 * without requiring block-type agnostic code to include the prefix. 173 */ 174 struct cxl_regs { 175 /* 176 * Common set of CXL Component register block base pointers 177 * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure 178 * @ras: CXL 2.0 8.2.5.9 CXL RAS Capability Structure 179 */ 180 struct_group_tagged(cxl_component_regs, component, 181 void __iomem *hdm_decoder; 182 void __iomem *ras; 183 ); 184 /* 185 * Common set of CXL Device register block base pointers 186 * @status: CXL 2.0 8.2.8.3 Device Status Registers 187 * @mbox: CXL 2.0 8.2.8.4 Mailbox Registers 188 * @memdev: CXL 2.0 8.2.8.5 Memory Device Registers 189 */ 190 struct_group_tagged(cxl_device_regs, device_regs, 191 void __iomem *status, *mbox, *memdev; 192 ); 193 }; 194 195 struct cxl_reg_map { 196 bool valid; 197 int id; 198 unsigned long offset; 199 unsigned long size; 200 }; 201 202 struct cxl_component_reg_map { 203 struct cxl_reg_map hdm_decoder; 204 struct cxl_reg_map ras; 205 }; 206 207 struct cxl_device_reg_map { 208 struct cxl_reg_map status; 209 struct cxl_reg_map mbox; 210 struct cxl_reg_map memdev; 211 }; 212 213 /** 214 * struct cxl_register_map - DVSEC harvested register block mapping parameters 215 * @base: virtual base of the register-block-BAR + @block_offset 216 * @resource: physical resource base of the register block 217 * @max_size: maximum mapping size to perform register search 218 * @reg_type: see enum cxl_regloc_type 219 * @component_map: cxl_reg_map for component registers 220 * @device_map: cxl_reg_maps for device registers 221 */ 222 struct cxl_register_map { 223 void __iomem *base; 224 resource_size_t resource; 225 resource_size_t max_size; 226 u8 reg_type; 227 union { 228 struct cxl_component_reg_map component_map; 229 struct cxl_device_reg_map device_map; 230 }; 231 }; 232 233 void cxl_probe_component_regs(struct device *dev, void __iomem *base, 234 struct cxl_component_reg_map *map); 235 void cxl_probe_device_regs(struct device *dev, void __iomem *base, 236 struct cxl_device_reg_map *map); 237 int cxl_map_component_regs(struct device *dev, struct cxl_component_regs *regs, 238 struct cxl_register_map *map, 239 unsigned long map_mask); 240 int cxl_map_device_regs(struct device *dev, struct cxl_device_regs *regs, 241 struct cxl_register_map *map); 242 243 enum cxl_regloc_type; 244 int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, 245 struct cxl_register_map *map); 246 247 enum cxl_rcrb { 248 CXL_RCRB_DOWNSTREAM, 249 CXL_RCRB_UPSTREAM, 250 }; 251 resource_size_t cxl_rcrb_to_component(struct device *dev, 252 resource_size_t rcrb, 253 enum cxl_rcrb which); 254 255 #define CXL_RESOURCE_NONE ((resource_size_t) -1) 256 #define CXL_TARGET_STRLEN 20 257 258 /* 259 * cxl_decoder flags that define the type of memory / devices this 260 * decoder supports as well as configuration lock status See "CXL 2.0 261 * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details. 262 */ 263 #define CXL_DECODER_F_RAM BIT(0) 264 #define CXL_DECODER_F_PMEM BIT(1) 265 #define CXL_DECODER_F_TYPE2 BIT(2) 266 #define CXL_DECODER_F_TYPE3 BIT(3) 267 #define CXL_DECODER_F_LOCK BIT(4) 268 #define CXL_DECODER_F_ENABLE BIT(5) 269 #define CXL_DECODER_F_MASK GENMASK(5, 0) 270 271 enum cxl_decoder_type { 272 CXL_DECODER_ACCELERATOR = 2, 273 CXL_DECODER_EXPANDER = 3, 274 }; 275 276 /* 277 * Current specification goes up to 8, double that seems a reasonable 278 * software max for the foreseeable future 279 */ 280 #define CXL_DECODER_MAX_INTERLEAVE 16 281 282 283 /** 284 * struct cxl_decoder - Common CXL HDM Decoder Attributes 285 * @dev: this decoder's device 286 * @id: kernel device name id 287 * @hpa_range: Host physical address range mapped by this decoder 288 * @interleave_ways: number of cxl_dports in this decode 289 * @interleave_granularity: data stride per dport 290 * @target_type: accelerator vs expander (type2 vs type3) selector 291 * @region: currently assigned region for this decoder 292 * @flags: memory type capabilities and locking 293 * @commit: device/decoder-type specific callback to commit settings to hw 294 * @reset: device/decoder-type specific callback to reset hw settings 295 */ 296 struct cxl_decoder { 297 struct device dev; 298 int id; 299 struct range hpa_range; 300 int interleave_ways; 301 int interleave_granularity; 302 enum cxl_decoder_type target_type; 303 struct cxl_region *region; 304 unsigned long flags; 305 int (*commit)(struct cxl_decoder *cxld); 306 int (*reset)(struct cxl_decoder *cxld); 307 }; 308 309 /* 310 * CXL_DECODER_DEAD prevents endpoints from being reattached to regions 311 * while cxld_unregister() is running 312 */ 313 enum cxl_decoder_mode { 314 CXL_DECODER_NONE, 315 CXL_DECODER_RAM, 316 CXL_DECODER_PMEM, 317 CXL_DECODER_MIXED, 318 CXL_DECODER_DEAD, 319 }; 320 321 /** 322 * struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder 323 * @cxld: base cxl_decoder_object 324 * @dpa_res: actively claimed DPA span of this decoder 325 * @skip: offset into @dpa_res where @cxld.hpa_range maps 326 * @mode: which memory type / access-mode-partition this decoder targets 327 * @pos: interleave position in @cxld.region 328 */ 329 struct cxl_endpoint_decoder { 330 struct cxl_decoder cxld; 331 struct resource *dpa_res; 332 resource_size_t skip; 333 enum cxl_decoder_mode mode; 334 int pos; 335 }; 336 337 /** 338 * struct cxl_switch_decoder - Switch specific CXL HDM Decoder 339 * @cxld: base cxl_decoder object 340 * @target_lock: coordinate coherent reads of the target list 341 * @nr_targets: number of elements in @target 342 * @target: active ordered target list in current decoder configuration 343 * 344 * The 'switch' decoder type represents the decoder instances of cxl_port's that 345 * route from the root of a CXL memory decode topology to the endpoints. They 346 * come in two flavors, root-level decoders, statically defined by platform 347 * firmware, and mid-level decoders, where interleave-granularity, 348 * interleave-width, and the target list are mutable. 349 */ 350 struct cxl_switch_decoder { 351 struct cxl_decoder cxld; 352 seqlock_t target_lock; 353 int nr_targets; 354 struct cxl_dport *target[]; 355 }; 356 357 struct cxl_root_decoder; 358 typedef struct cxl_dport *(*cxl_calc_hb_fn)(struct cxl_root_decoder *cxlrd, 359 int pos); 360 361 /** 362 * struct cxl_root_decoder - Static platform CXL address decoder 363 * @res: host / parent resource for region allocations 364 * @region_id: region id for next region provisioning event 365 * @calc_hb: which host bridge covers the n'th position by granularity 366 * @platform_data: platform specific configuration data 367 * @cxlsd: base cxl switch decoder 368 */ 369 struct cxl_root_decoder { 370 struct resource *res; 371 atomic_t region_id; 372 cxl_calc_hb_fn calc_hb; 373 void *platform_data; 374 struct cxl_switch_decoder cxlsd; 375 }; 376 377 /* 378 * enum cxl_config_state - State machine for region configuration 379 * @CXL_CONFIG_IDLE: Any sysfs attribute can be written freely 380 * @CXL_CONFIG_INTERLEAVE_ACTIVE: region size has been set, no more 381 * changes to interleave_ways or interleave_granularity 382 * @CXL_CONFIG_ACTIVE: All targets have been added the region is now 383 * active 384 * @CXL_CONFIG_RESET_PENDING: see commit_store() 385 * @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware 386 */ 387 enum cxl_config_state { 388 CXL_CONFIG_IDLE, 389 CXL_CONFIG_INTERLEAVE_ACTIVE, 390 CXL_CONFIG_ACTIVE, 391 CXL_CONFIG_RESET_PENDING, 392 CXL_CONFIG_COMMIT, 393 }; 394 395 /** 396 * struct cxl_region_params - region settings 397 * @state: allow the driver to lockdown further parameter changes 398 * @uuid: unique id for persistent regions 399 * @interleave_ways: number of endpoints in the region 400 * @interleave_granularity: capacity each endpoint contributes to a stripe 401 * @res: allocated iomem capacity for this region 402 * @targets: active ordered targets in current decoder configuration 403 * @nr_targets: number of targets 404 * 405 * State transitions are protected by the cxl_region_rwsem 406 */ 407 struct cxl_region_params { 408 enum cxl_config_state state; 409 uuid_t uuid; 410 int interleave_ways; 411 int interleave_granularity; 412 struct resource *res; 413 struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE]; 414 int nr_targets; 415 }; 416 417 /* 418 * Flag whether this region needs to have its HPA span synchronized with 419 * CPU cache state at region activation time. 420 */ 421 #define CXL_REGION_F_INCOHERENT 0 422 423 /** 424 * struct cxl_region - CXL region 425 * @dev: This region's device 426 * @id: This region's id. Id is globally unique across all regions 427 * @mode: Endpoint decoder allocation / access mode 428 * @type: Endpoint decoder target type 429 * @cxl_nvb: nvdimm bridge for coordinating @cxlr_pmem setup / shutdown 430 * @cxlr_pmem: (for pmem regions) cached copy of the nvdimm bridge 431 * @flags: Region state flags 432 * @params: active + config params for the region 433 */ 434 struct cxl_region { 435 struct device dev; 436 int id; 437 enum cxl_decoder_mode mode; 438 enum cxl_decoder_type type; 439 struct cxl_nvdimm_bridge *cxl_nvb; 440 struct cxl_pmem_region *cxlr_pmem; 441 unsigned long flags; 442 struct cxl_region_params params; 443 }; 444 445 struct cxl_nvdimm_bridge { 446 int id; 447 struct device dev; 448 struct cxl_port *port; 449 struct nvdimm_bus *nvdimm_bus; 450 struct nvdimm_bus_descriptor nd_desc; 451 }; 452 453 #define CXL_DEV_ID_LEN 19 454 455 struct cxl_nvdimm { 456 struct device dev; 457 struct cxl_memdev *cxlmd; 458 u8 dev_id[CXL_DEV_ID_LEN]; /* for nvdimm, string of 'serial' */ 459 }; 460 461 struct cxl_pmem_region_mapping { 462 struct cxl_memdev *cxlmd; 463 struct cxl_nvdimm *cxl_nvd; 464 u64 start; 465 u64 size; 466 int position; 467 }; 468 469 struct cxl_pmem_region { 470 struct device dev; 471 struct cxl_region *cxlr; 472 struct nd_region *nd_region; 473 struct range hpa_range; 474 int nr_mappings; 475 struct cxl_pmem_region_mapping mapping[]; 476 }; 477 478 /** 479 * struct cxl_port - logical collection of upstream port devices and 480 * downstream port devices to construct a CXL memory 481 * decode hierarchy. 482 * @dev: this port's device 483 * @uport: PCI or platform device implementing the upstream port capability 484 * @host_bridge: Shortcut to the platform attach point for this port 485 * @id: id for port device-name 486 * @dports: cxl_dport instances referenced by decoders 487 * @endpoints: cxl_ep instances, endpoints that are a descendant of this port 488 * @regions: cxl_region_ref instances, regions mapped by this port 489 * @parent_dport: dport that points to this port in the parent 490 * @decoder_ida: allocator for decoder ids 491 * @nr_dports: number of entries in @dports 492 * @hdm_end: track last allocated HDM decoder instance for allocation ordering 493 * @commit_end: cursor to track highest committed decoder for commit ordering 494 * @component_reg_phys: component register capability base address (optional) 495 * @dead: last ep has been removed, force port re-creation 496 * @depth: How deep this port is relative to the root. depth 0 is the root. 497 * @cdat: Cached CDAT data 498 * @cdat_available: Should a CDAT attribute be available in sysfs 499 */ 500 struct cxl_port { 501 struct device dev; 502 struct device *uport; 503 struct device *host_bridge; 504 int id; 505 struct xarray dports; 506 struct xarray endpoints; 507 struct xarray regions; 508 struct cxl_dport *parent_dport; 509 struct ida decoder_ida; 510 int nr_dports; 511 int hdm_end; 512 int commit_end; 513 resource_size_t component_reg_phys; 514 bool dead; 515 unsigned int depth; 516 struct cxl_cdat { 517 void *table; 518 size_t length; 519 } cdat; 520 bool cdat_available; 521 }; 522 523 static inline struct cxl_dport * 524 cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev) 525 { 526 return xa_load(&port->dports, (unsigned long)dport_dev); 527 } 528 529 /** 530 * struct cxl_dport - CXL downstream port 531 * @dport: PCI bridge or firmware device representing the downstream link 532 * @port_id: unique hardware identifier for dport in decoder target list 533 * @component_reg_phys: downstream port component registers 534 * @rcrb: base address for the Root Complex Register Block 535 * @rch: Indicate whether this dport was enumerated in RCH or VH mode 536 * @port: reference to cxl_port that contains this downstream port 537 */ 538 struct cxl_dport { 539 struct device *dport; 540 int port_id; 541 resource_size_t component_reg_phys; 542 resource_size_t rcrb; 543 bool rch; 544 struct cxl_port *port; 545 }; 546 547 /** 548 * struct cxl_ep - track an endpoint's interest in a port 549 * @ep: device that hosts a generic CXL endpoint (expander or accelerator) 550 * @dport: which dport routes to this endpoint on @port 551 * @next: cxl switch port across the link attached to @dport NULL if 552 * attached to an endpoint 553 */ 554 struct cxl_ep { 555 struct device *ep; 556 struct cxl_dport *dport; 557 struct cxl_port *next; 558 }; 559 560 /** 561 * struct cxl_region_ref - track a region's interest in a port 562 * @port: point in topology to install this reference 563 * @decoder: decoder assigned for @region in @port 564 * @region: region for this reference 565 * @endpoints: cxl_ep references for region members beneath @port 566 * @nr_targets_set: track how many targets have been programmed during setup 567 * @nr_eps: number of endpoints beneath @port 568 * @nr_targets: number of distinct targets needed to reach @nr_eps 569 */ 570 struct cxl_region_ref { 571 struct cxl_port *port; 572 struct cxl_decoder *decoder; 573 struct cxl_region *region; 574 struct xarray endpoints; 575 int nr_targets_set; 576 int nr_eps; 577 int nr_targets; 578 }; 579 580 /* 581 * The platform firmware device hosting the root is also the top of the 582 * CXL port topology. All other CXL ports have another CXL port as their 583 * parent and their ->uport / host device is out-of-line of the port 584 * ancestry. 585 */ 586 static inline bool is_cxl_root(struct cxl_port *port) 587 { 588 return port->uport == port->dev.parent; 589 } 590 591 bool is_cxl_port(struct device *dev); 592 struct cxl_port *to_cxl_port(struct device *dev); 593 struct pci_bus; 594 int devm_cxl_register_pci_bus(struct device *host, struct device *uport, 595 struct pci_bus *bus); 596 struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port); 597 struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport, 598 resource_size_t component_reg_phys, 599 struct cxl_dport *parent_dport); 600 struct cxl_port *find_cxl_root(struct device *dev); 601 int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); 602 void cxl_bus_rescan(void); 603 void cxl_bus_drain(void); 604 struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd, 605 struct cxl_dport **dport); 606 bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd); 607 608 struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, 609 struct device *dport, int port_id, 610 resource_size_t component_reg_phys); 611 struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, 612 struct device *dport_dev, int port_id, 613 resource_size_t component_reg_phys, 614 resource_size_t rcrb); 615 616 struct cxl_decoder *to_cxl_decoder(struct device *dev); 617 struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev); 618 struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev); 619 bool is_root_decoder(struct device *dev); 620 bool is_endpoint_decoder(struct device *dev); 621 struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, 622 unsigned int nr_targets, 623 cxl_calc_hb_fn calc_hb); 624 struct cxl_dport *cxl_hb_modulo(struct cxl_root_decoder *cxlrd, int pos); 625 struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port, 626 unsigned int nr_targets); 627 int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map); 628 struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port); 629 int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map); 630 int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld); 631 int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint); 632 633 struct cxl_hdm; 634 struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port); 635 int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm); 636 int devm_cxl_add_passthrough_decoder(struct cxl_port *port); 637 638 bool is_cxl_region(struct device *dev); 639 640 extern struct bus_type cxl_bus_type; 641 642 struct cxl_driver { 643 const char *name; 644 int (*probe)(struct device *dev); 645 void (*remove)(struct device *dev); 646 struct device_driver drv; 647 int id; 648 }; 649 650 static inline struct cxl_driver *to_cxl_drv(struct device_driver *drv) 651 { 652 return container_of(drv, struct cxl_driver, drv); 653 } 654 655 int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner, 656 const char *modname); 657 #define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME) 658 void cxl_driver_unregister(struct cxl_driver *cxl_drv); 659 660 #define module_cxl_driver(__cxl_driver) \ 661 module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister) 662 663 #define CXL_DEVICE_NVDIMM_BRIDGE 1 664 #define CXL_DEVICE_NVDIMM 2 665 #define CXL_DEVICE_PORT 3 666 #define CXL_DEVICE_ROOT 4 667 #define CXL_DEVICE_MEMORY_EXPANDER 5 668 #define CXL_DEVICE_REGION 6 669 #define CXL_DEVICE_PMEM_REGION 7 670 671 #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*") 672 #define CXL_MODALIAS_FMT "cxl:t%d" 673 674 struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev); 675 struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host, 676 struct cxl_port *port); 677 struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev); 678 bool is_cxl_nvdimm(struct device *dev); 679 bool is_cxl_nvdimm_bridge(struct device *dev); 680 int devm_cxl_add_nvdimm(struct cxl_memdev *cxlmd); 681 struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct device *dev); 682 683 #ifdef CONFIG_CXL_REGION 684 bool is_cxl_pmem_region(struct device *dev); 685 struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev); 686 #else 687 static inline bool is_cxl_pmem_region(struct device *dev) 688 { 689 return false; 690 } 691 static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev) 692 { 693 return NULL; 694 } 695 #endif 696 697 /* 698 * Unit test builds overrides this to __weak, find the 'strong' version 699 * of these symbols in tools/testing/cxl/. 700 */ 701 #ifndef __mock 702 #define __mock static 703 #endif 704 705 #endif /* __CXL_H__ */ 706