1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2022 Intel Corporation. All rights reserved. */ 3 #undef TRACE_SYSTEM 4 #define TRACE_SYSTEM cxl 5 6 #if !defined(_CXL_EVENTS_H) || defined(TRACE_HEADER_MULTI_READ) 7 #define _CXL_EVENTS_H 8 9 #include <cxl.h> 10 #include <linux/tracepoint.h> 11 12 #define CXL_RAS_UC_CACHE_DATA_PARITY BIT(0) 13 #define CXL_RAS_UC_CACHE_ADDR_PARITY BIT(1) 14 #define CXL_RAS_UC_CACHE_BE_PARITY BIT(2) 15 #define CXL_RAS_UC_CACHE_DATA_ECC BIT(3) 16 #define CXL_RAS_UC_MEM_DATA_PARITY BIT(4) 17 #define CXL_RAS_UC_MEM_ADDR_PARITY BIT(5) 18 #define CXL_RAS_UC_MEM_BE_PARITY BIT(6) 19 #define CXL_RAS_UC_MEM_DATA_ECC BIT(7) 20 #define CXL_RAS_UC_REINIT_THRESH BIT(8) 21 #define CXL_RAS_UC_RSVD_ENCODE BIT(9) 22 #define CXL_RAS_UC_POISON BIT(10) 23 #define CXL_RAS_UC_RECV_OVERFLOW BIT(11) 24 #define CXL_RAS_UC_INTERNAL_ERR BIT(14) 25 #define CXL_RAS_UC_IDE_TX_ERR BIT(15) 26 #define CXL_RAS_UC_IDE_RX_ERR BIT(16) 27 28 #define show_uc_errs(status) __print_flags(status, " | ", \ 29 { CXL_RAS_UC_CACHE_DATA_PARITY, "Cache Data Parity Error" }, \ 30 { CXL_RAS_UC_CACHE_ADDR_PARITY, "Cache Address Parity Error" }, \ 31 { CXL_RAS_UC_CACHE_BE_PARITY, "Cache Byte Enable Parity Error" }, \ 32 { CXL_RAS_UC_CACHE_DATA_ECC, "Cache Data ECC Error" }, \ 33 { CXL_RAS_UC_MEM_DATA_PARITY, "Memory Data Parity Error" }, \ 34 { CXL_RAS_UC_MEM_ADDR_PARITY, "Memory Address Parity Error" }, \ 35 { CXL_RAS_UC_MEM_BE_PARITY, "Memory Byte Enable Parity Error" }, \ 36 { CXL_RAS_UC_MEM_DATA_ECC, "Memory Data ECC Error" }, \ 37 { CXL_RAS_UC_REINIT_THRESH, "REINIT Threshold Hit" }, \ 38 { CXL_RAS_UC_RSVD_ENCODE, "Received Unrecognized Encoding" }, \ 39 { CXL_RAS_UC_POISON, "Received Poison From Peer" }, \ 40 { CXL_RAS_UC_RECV_OVERFLOW, "Receiver Overflow" }, \ 41 { CXL_RAS_UC_INTERNAL_ERR, "Component Specific Error" }, \ 42 { CXL_RAS_UC_IDE_TX_ERR, "IDE Tx Error" }, \ 43 { CXL_RAS_UC_IDE_RX_ERR, "IDE Rx Error" } \ 44 ) 45 46 TRACE_EVENT(cxl_aer_uncorrectable_error, 47 TP_PROTO(const struct device *dev, u32 status, u32 fe, u32 *hl), 48 TP_ARGS(dev, status, fe, hl), 49 TP_STRUCT__entry( 50 __string(dev_name, dev_name(dev)) 51 __field(u32, status) 52 __field(u32, first_error) 53 __array(u32, header_log, CXL_HEADERLOG_SIZE_U32) 54 ), 55 TP_fast_assign( 56 __assign_str(dev_name, dev_name(dev)); 57 __entry->status = status; 58 __entry->first_error = fe; 59 /* 60 * Embed the 512B headerlog data for user app retrieval and 61 * parsing, but no need to print this in the trace buffer. 62 */ 63 memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE); 64 ), 65 TP_printk("%s: status: '%s' first_error: '%s'", 66 __get_str(dev_name), 67 show_uc_errs(__entry->status), 68 show_uc_errs(__entry->first_error) 69 ) 70 ); 71 72 #define CXL_RAS_CE_CACHE_DATA_ECC BIT(0) 73 #define CXL_RAS_CE_MEM_DATA_ECC BIT(1) 74 #define CXL_RAS_CE_CRC_THRESH BIT(2) 75 #define CLX_RAS_CE_RETRY_THRESH BIT(3) 76 #define CXL_RAS_CE_CACHE_POISON BIT(4) 77 #define CXL_RAS_CE_MEM_POISON BIT(5) 78 #define CXL_RAS_CE_PHYS_LAYER_ERR BIT(6) 79 80 #define show_ce_errs(status) __print_flags(status, " | ", \ 81 { CXL_RAS_CE_CACHE_DATA_ECC, "Cache Data ECC Error" }, \ 82 { CXL_RAS_CE_MEM_DATA_ECC, "Memory Data ECC Error" }, \ 83 { CXL_RAS_CE_CRC_THRESH, "CRC Threshold Hit" }, \ 84 { CLX_RAS_CE_RETRY_THRESH, "Retry Threshold" }, \ 85 { CXL_RAS_CE_CACHE_POISON, "Received Cache Poison From Peer" }, \ 86 { CXL_RAS_CE_MEM_POISON, "Received Memory Poison From Peer" }, \ 87 { CXL_RAS_CE_PHYS_LAYER_ERR, "Received Error From Physical Layer" } \ 88 ) 89 90 TRACE_EVENT(cxl_aer_correctable_error, 91 TP_PROTO(const struct device *dev, u32 status), 92 TP_ARGS(dev, status), 93 TP_STRUCT__entry( 94 __string(dev_name, dev_name(dev)) 95 __field(u32, status) 96 ), 97 TP_fast_assign( 98 __assign_str(dev_name, dev_name(dev)); 99 __entry->status = status; 100 ), 101 TP_printk("%s: status: '%s'", 102 __get_str(dev_name), show_ce_errs(__entry->status) 103 ) 104 ); 105 106 #endif /* _CXL_EVENTS_H */ 107 108 #define TRACE_INCLUDE_FILE trace 109 #include <trace/define_trace.h> 110