1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2022 Intel Corporation. All rights reserved. */ 3 #undef TRACE_SYSTEM 4 #define TRACE_SYSTEM cxl 5 6 #if !defined(_CXL_EVENTS_H) || defined(TRACE_HEADER_MULTI_READ) 7 #define _CXL_EVENTS_H 8 9 #include <linux/tracepoint.h> 10 #include <linux/pci.h> 11 #include <linux/unaligned.h> 12 13 #include <cxl.h> 14 #include <cxlmem.h> 15 #include "core.h" 16 17 #define CXL_RAS_UC_CACHE_DATA_PARITY BIT(0) 18 #define CXL_RAS_UC_CACHE_ADDR_PARITY BIT(1) 19 #define CXL_RAS_UC_CACHE_BE_PARITY BIT(2) 20 #define CXL_RAS_UC_CACHE_DATA_ECC BIT(3) 21 #define CXL_RAS_UC_MEM_DATA_PARITY BIT(4) 22 #define CXL_RAS_UC_MEM_ADDR_PARITY BIT(5) 23 #define CXL_RAS_UC_MEM_BE_PARITY BIT(6) 24 #define CXL_RAS_UC_MEM_DATA_ECC BIT(7) 25 #define CXL_RAS_UC_REINIT_THRESH BIT(8) 26 #define CXL_RAS_UC_RSVD_ENCODE BIT(9) 27 #define CXL_RAS_UC_POISON BIT(10) 28 #define CXL_RAS_UC_RECV_OVERFLOW BIT(11) 29 #define CXL_RAS_UC_INTERNAL_ERR BIT(14) 30 #define CXL_RAS_UC_IDE_TX_ERR BIT(15) 31 #define CXL_RAS_UC_IDE_RX_ERR BIT(16) 32 33 #define show_uc_errs(status) __print_flags(status, " | ", \ 34 { CXL_RAS_UC_CACHE_DATA_PARITY, "Cache Data Parity Error" }, \ 35 { CXL_RAS_UC_CACHE_ADDR_PARITY, "Cache Address Parity Error" }, \ 36 { CXL_RAS_UC_CACHE_BE_PARITY, "Cache Byte Enable Parity Error" }, \ 37 { CXL_RAS_UC_CACHE_DATA_ECC, "Cache Data ECC Error" }, \ 38 { CXL_RAS_UC_MEM_DATA_PARITY, "Memory Data Parity Error" }, \ 39 { CXL_RAS_UC_MEM_ADDR_PARITY, "Memory Address Parity Error" }, \ 40 { CXL_RAS_UC_MEM_BE_PARITY, "Memory Byte Enable Parity Error" }, \ 41 { CXL_RAS_UC_MEM_DATA_ECC, "Memory Data ECC Error" }, \ 42 { CXL_RAS_UC_REINIT_THRESH, "REINIT Threshold Hit" }, \ 43 { CXL_RAS_UC_RSVD_ENCODE, "Received Unrecognized Encoding" }, \ 44 { CXL_RAS_UC_POISON, "Received Poison From Peer" }, \ 45 { CXL_RAS_UC_RECV_OVERFLOW, "Receiver Overflow" }, \ 46 { CXL_RAS_UC_INTERNAL_ERR, "Component Specific Error" }, \ 47 { CXL_RAS_UC_IDE_TX_ERR, "IDE Tx Error" }, \ 48 { CXL_RAS_UC_IDE_RX_ERR, "IDE Rx Error" } \ 49 ) 50 51 TRACE_EVENT(cxl_port_aer_uncorrectable_error, 52 TP_PROTO(struct device *dev, u32 status, u32 fe, u32 *hl), 53 TP_ARGS(dev, status, fe, hl), 54 TP_STRUCT__entry( 55 __string(device, dev_name(dev)) 56 __string(host, dev_name(dev->parent)) 57 __field(u32, status) 58 __field(u32, first_error) 59 __array(u32, header_log, CXL_HEADERLOG_TRACE_SIZE_U32) 60 ), 61 TP_fast_assign( 62 __assign_str(device); 63 __assign_str(host); 64 __entry->status = status; 65 __entry->first_error = fe; 66 /* 67 * Embed headerlog data for user app retrieval and parsing, 68 * but no need to print in the trace buffer. Only 69 * CXL_HEADERLOG_SIZE_U32 (16) dwords are hardware data; 70 * the remaining entries preserve the 512-byte ABI layout 71 * rasdaemon depends on and are zero-filled by the caller. 72 */ 73 memcpy(__entry->header_log, hl, 74 CXL_HEADERLOG_TRACE_SIZE_U32 * sizeof(u32)); 75 ), 76 TP_printk("device=%s host=%s status: '%s' first_error: '%s'", 77 __get_str(device), __get_str(host), 78 show_uc_errs(__entry->status), 79 show_uc_errs(__entry->first_error) 80 ) 81 ); 82 83 TRACE_EVENT(cxl_aer_uncorrectable_error, 84 TP_PROTO(const struct cxl_memdev *cxlmd, u32 status, u32 fe, u32 *hl), 85 TP_ARGS(cxlmd, status, fe, hl), 86 TP_STRUCT__entry( 87 __string(memdev, dev_name(&cxlmd->dev)) 88 __string(host, dev_name(cxlmd->dev.parent)) 89 __field(u64, serial) 90 __field(u32, status) 91 __field(u32, first_error) 92 __array(u32, header_log, CXL_HEADERLOG_TRACE_SIZE_U32) 93 ), 94 TP_fast_assign( 95 __assign_str(memdev); 96 __assign_str(host); 97 __entry->serial = cxlmd->cxlds->serial; 98 __entry->status = status; 99 __entry->first_error = fe; 100 /* 101 * Embed headerlog data for user app retrieval and parsing, 102 * but no need to print in the trace buffer. Only 103 * CXL_HEADERLOG_SIZE_U32 (16) dwords are hardware data; 104 * the remaining entries preserve the 512-byte ABI layout 105 * rasdaemon depends on and are zero-filled by the caller. 106 */ 107 memcpy(__entry->header_log, hl, 108 CXL_HEADERLOG_TRACE_SIZE_U32 * sizeof(u32)); 109 ), 110 TP_printk("memdev=%s host=%s serial=%lld: status: '%s' first_error: '%s'", 111 __get_str(memdev), __get_str(host), __entry->serial, 112 show_uc_errs(__entry->status), 113 show_uc_errs(__entry->first_error) 114 ) 115 ); 116 117 #define CXL_RAS_CE_CACHE_DATA_ECC BIT(0) 118 #define CXL_RAS_CE_MEM_DATA_ECC BIT(1) 119 #define CXL_RAS_CE_CRC_THRESH BIT(2) 120 #define CLX_RAS_CE_RETRY_THRESH BIT(3) 121 #define CXL_RAS_CE_CACHE_POISON BIT(4) 122 #define CXL_RAS_CE_MEM_POISON BIT(5) 123 #define CXL_RAS_CE_PHYS_LAYER_ERR BIT(6) 124 125 #define show_ce_errs(status) __print_flags(status, " | ", \ 126 { CXL_RAS_CE_CACHE_DATA_ECC, "Cache Data ECC Error" }, \ 127 { CXL_RAS_CE_MEM_DATA_ECC, "Memory Data ECC Error" }, \ 128 { CXL_RAS_CE_CRC_THRESH, "CRC Threshold Hit" }, \ 129 { CLX_RAS_CE_RETRY_THRESH, "Retry Threshold" }, \ 130 { CXL_RAS_CE_CACHE_POISON, "Received Cache Poison From Peer" }, \ 131 { CXL_RAS_CE_MEM_POISON, "Received Memory Poison From Peer" }, \ 132 { CXL_RAS_CE_PHYS_LAYER_ERR, "Received Error From Physical Layer" } \ 133 ) 134 135 TRACE_EVENT(cxl_port_aer_correctable_error, 136 TP_PROTO(struct device *dev, u32 status), 137 TP_ARGS(dev, status), 138 TP_STRUCT__entry( 139 __string(device, dev_name(dev)) 140 __string(host, dev_name(dev->parent)) 141 __field(u32, status) 142 ), 143 TP_fast_assign( 144 __assign_str(device); 145 __assign_str(host); 146 __entry->status = status; 147 ), 148 TP_printk("device=%s host=%s status='%s'", 149 __get_str(device), __get_str(host), 150 show_ce_errs(__entry->status) 151 ) 152 ); 153 154 TRACE_EVENT(cxl_aer_correctable_error, 155 TP_PROTO(const struct cxl_memdev *cxlmd, u32 status), 156 TP_ARGS(cxlmd, status), 157 TP_STRUCT__entry( 158 __string(memdev, dev_name(&cxlmd->dev)) 159 __string(host, dev_name(cxlmd->dev.parent)) 160 __field(u64, serial) 161 __field(u32, status) 162 ), 163 TP_fast_assign( 164 __assign_str(memdev); 165 __assign_str(host); 166 __entry->serial = cxlmd->cxlds->serial; 167 __entry->status = status; 168 ), 169 TP_printk("memdev=%s host=%s serial=%lld: status: '%s'", 170 __get_str(memdev), __get_str(host), __entry->serial, 171 show_ce_errs(__entry->status) 172 ) 173 ); 174 175 #define cxl_event_log_type_str(type) \ 176 __print_symbolic(type, \ 177 { CXL_EVENT_TYPE_INFO, "Informational" }, \ 178 { CXL_EVENT_TYPE_WARN, "Warning" }, \ 179 { CXL_EVENT_TYPE_FAIL, "Failure" }, \ 180 { CXL_EVENT_TYPE_FATAL, "Fatal" }) 181 182 TRACE_EVENT(cxl_overflow, 183 184 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, 185 struct cxl_get_event_payload *payload), 186 187 TP_ARGS(cxlmd, log, payload), 188 189 TP_STRUCT__entry( 190 __string(memdev, dev_name(&cxlmd->dev)) 191 __string(host, dev_name(cxlmd->dev.parent)) 192 __field(int, log) 193 __field(u64, serial) 194 __field(u64, first_ts) 195 __field(u64, last_ts) 196 __field(u16, count) 197 ), 198 199 TP_fast_assign( 200 __assign_str(memdev); 201 __assign_str(host); 202 __entry->serial = cxlmd->cxlds->serial; 203 __entry->log = log; 204 __entry->count = le16_to_cpu(payload->overflow_err_count); 205 __entry->first_ts = le64_to_cpu(payload->first_overflow_timestamp); 206 __entry->last_ts = le64_to_cpu(payload->last_overflow_timestamp); 207 ), 208 209 TP_printk("memdev=%s host=%s serial=%lld: log=%s : %u records from %llu to %llu", 210 __get_str(memdev), __get_str(host), __entry->serial, 211 cxl_event_log_type_str(__entry->log), __entry->count, 212 __entry->first_ts, __entry->last_ts) 213 214 ); 215 216 /* 217 * Common Event Record Format 218 * CXL 3.0 section 8.2.9.2.1; Table 8-42 219 */ 220 #define CXL_EVENT_RECORD_FLAG_PERMANENT BIT(2) 221 #define CXL_EVENT_RECORD_FLAG_MAINT_NEEDED BIT(3) 222 #define CXL_EVENT_RECORD_FLAG_PERF_DEGRADED BIT(4) 223 #define CXL_EVENT_RECORD_FLAG_HW_REPLACE BIT(5) 224 #define CXL_EVENT_RECORD_FLAG_MAINT_OP_SUB_CLASS_VALID BIT(6) 225 #define CXL_EVENT_RECORD_FLAG_LD_ID_VALID BIT(7) 226 #define CXL_EVENT_RECORD_FLAG_HEAD_ID_VALID BIT(8) 227 #define show_hdr_flags(flags) __print_flags(flags, " | ", \ 228 { CXL_EVENT_RECORD_FLAG_PERMANENT, "PERMANENT_CONDITION" }, \ 229 { CXL_EVENT_RECORD_FLAG_MAINT_NEEDED, "MAINTENANCE_NEEDED" }, \ 230 { CXL_EVENT_RECORD_FLAG_PERF_DEGRADED, "PERFORMANCE_DEGRADED" }, \ 231 { CXL_EVENT_RECORD_FLAG_HW_REPLACE, "HARDWARE_REPLACEMENT_NEEDED" }, \ 232 { CXL_EVENT_RECORD_FLAG_MAINT_OP_SUB_CLASS_VALID, "MAINT_OP_SUB_CLASS_VALID" }, \ 233 { CXL_EVENT_RECORD_FLAG_LD_ID_VALID, "LD_ID_VALID" }, \ 234 { CXL_EVENT_RECORD_FLAG_HEAD_ID_VALID, "HEAD_ID_VALID" } \ 235 ) 236 237 /* 238 * Define macros for the common header of each CXL event. 239 * 240 * Tracepoints using these macros must do 3 things: 241 * 242 * 1) Add CXL_EVT_TP_entry to TP_STRUCT__entry 243 * 2) Use CXL_EVT_TP_fast_assign within TP_fast_assign; 244 * pass the dev, log, and CXL event header 245 * NOTE: The uuid must be assigned by the specific trace event 246 * 3) Use CXL_EVT_TP_printk() instead of TP_printk() 247 * 248 * See the generic_event tracepoint as an example. 249 */ 250 #define CXL_EVT_TP_entry \ 251 __string(memdev, dev_name(&cxlmd->dev)) \ 252 __string(host, dev_name(cxlmd->dev.parent)) \ 253 __field(int, log) \ 254 __field_struct(uuid_t, hdr_uuid) \ 255 __field(u64, serial) \ 256 __field(u32, hdr_flags) \ 257 __field(u16, hdr_handle) \ 258 __field(u16, hdr_related_handle) \ 259 __field(u64, hdr_timestamp) \ 260 __field(u8, hdr_length) \ 261 __field(u8, hdr_maint_op_class) \ 262 __field(u8, hdr_maint_op_sub_class) \ 263 __field(u16, hdr_ld_id) \ 264 __field(u8, hdr_head_id) 265 266 #define CXL_EVT_TP_fast_assign(cxlmd, l, hdr) \ 267 __assign_str(memdev); \ 268 __assign_str(host); \ 269 __entry->log = (l); \ 270 __entry->serial = (cxlmd)->cxlds->serial; \ 271 __entry->hdr_length = (hdr).length; \ 272 __entry->hdr_flags = get_unaligned_le24((hdr).flags); \ 273 __entry->hdr_handle = le16_to_cpu((hdr).handle); \ 274 __entry->hdr_related_handle = le16_to_cpu((hdr).related_handle); \ 275 __entry->hdr_timestamp = le64_to_cpu((hdr).timestamp); \ 276 __entry->hdr_maint_op_class = (hdr).maint_op_class; \ 277 __entry->hdr_maint_op_sub_class = (hdr).maint_op_sub_class; \ 278 __entry->hdr_ld_id = le16_to_cpu((hdr).ld_id); \ 279 __entry->hdr_head_id = (hdr).head_id 280 281 #define CXL_EVT_TP_printk(fmt, ...) \ 282 TP_printk("memdev=%s host=%s serial=%lld log=%s : time=%llu uuid=%pUb " \ 283 "len=%d flags='%s' handle=%x related_handle=%x " \ 284 "maint_op_class=%u maint_op_sub_class=%u " \ 285 "ld_id=%x head_id=%x : " fmt, \ 286 __get_str(memdev), __get_str(host), __entry->serial, \ 287 cxl_event_log_type_str(__entry->log), \ 288 __entry->hdr_timestamp, &__entry->hdr_uuid, __entry->hdr_length,\ 289 show_hdr_flags(__entry->hdr_flags), __entry->hdr_handle, \ 290 __entry->hdr_related_handle, __entry->hdr_maint_op_class, \ 291 __entry->hdr_maint_op_sub_class, \ 292 __entry->hdr_ld_id, __entry->hdr_head_id, \ 293 ##__VA_ARGS__) 294 295 TRACE_EVENT(cxl_generic_event, 296 297 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, 298 const uuid_t *uuid, struct cxl_event_generic *gen_rec), 299 300 TP_ARGS(cxlmd, log, uuid, gen_rec), 301 302 TP_STRUCT__entry( 303 CXL_EVT_TP_entry 304 __array(u8, data, CXL_EVENT_RECORD_DATA_LENGTH) 305 ), 306 307 TP_fast_assign( 308 CXL_EVT_TP_fast_assign(cxlmd, log, gen_rec->hdr); 309 memcpy(&__entry->hdr_uuid, uuid, sizeof(uuid_t)); 310 memcpy(__entry->data, gen_rec->data, CXL_EVENT_RECORD_DATA_LENGTH); 311 ), 312 313 CXL_EVT_TP_printk("%s", 314 __print_hex(__entry->data, CXL_EVENT_RECORD_DATA_LENGTH)) 315 ); 316 317 /* 318 * Physical Address field masks 319 * 320 * General Media Event Record 321 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43 322 * 323 * DRAM Event Record 324 * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44 325 */ 326 #define CXL_DPA_FLAGS_MASK GENMASK(1, 0) 327 #define CXL_DPA_MASK GENMASK_ULL(63, 6) 328 329 #define CXL_DPA_VOLATILE BIT(0) 330 #define CXL_DPA_NOT_REPAIRABLE BIT(1) 331 #define show_dpa_flags(flags) __print_flags(flags, "|", \ 332 { CXL_DPA_VOLATILE, "VOLATILE" }, \ 333 { CXL_DPA_NOT_REPAIRABLE, "NOT_REPAIRABLE" } \ 334 ) 335 336 /* 337 * Component ID Format 338 * CXL 3.1 section 8.2.9.2.1; Table 8-44 339 */ 340 #define CXL_PLDM_COMPONENT_ID_ENTITY_VALID BIT(0) 341 #define CXL_PLDM_COMPONENT_ID_RES_VALID BIT(1) 342 343 #define show_comp_id_pldm_flags(flags) __print_flags(flags, " | ", \ 344 { CXL_PLDM_COMPONENT_ID_ENTITY_VALID, "PLDM Entity ID" }, \ 345 { CXL_PLDM_COMPONENT_ID_RES_VALID, "Resource ID" } \ 346 ) 347 348 #define show_pldm_entity_id(flags, valid_comp_id, valid_id_format, comp_id) \ 349 (flags & valid_comp_id && flags & valid_id_format) ? \ 350 (comp_id[0] & CXL_PLDM_COMPONENT_ID_ENTITY_VALID) ? \ 351 __print_hex(&comp_id[1], 6) : "0x00" : "0x00" 352 353 #define show_pldm_resource_id(flags, valid_comp_id, valid_id_format, comp_id) \ 354 (flags & valid_comp_id && flags & valid_id_format) ? \ 355 (comp_id[0] & CXL_PLDM_COMPONENT_ID_RES_VALID) ? \ 356 __print_hex(&comp_id[7], 4) : "0x00" : "0x00" 357 358 /* 359 * General Media Event Record - GMER 360 * CXL rev 3.1 Section 8.2.9.2.1.1; Table 8-45 361 */ 362 #define CXL_GMER_EVT_DESC_UNCORECTABLE_EVENT BIT(0) 363 #define CXL_GMER_EVT_DESC_THRESHOLD_EVENT BIT(1) 364 #define CXL_GMER_EVT_DESC_POISON_LIST_OVERFLOW BIT(2) 365 #define show_event_desc_flags(flags) __print_flags(flags, "|", \ 366 { CXL_GMER_EVT_DESC_UNCORECTABLE_EVENT, "UNCORRECTABLE_EVENT" }, \ 367 { CXL_GMER_EVT_DESC_THRESHOLD_EVENT, "THRESHOLD_EVENT" }, \ 368 { CXL_GMER_EVT_DESC_POISON_LIST_OVERFLOW, "POISON_LIST_OVERFLOW" } \ 369 ) 370 371 #define CXL_GMER_MEM_EVT_TYPE_ECC_ERROR 0x00 372 #define CXL_GMER_MEM_EVT_TYPE_INV_ADDR 0x01 373 #define CXL_GMER_MEM_EVT_TYPE_DATA_PATH_ERROR 0x02 374 #define CXL_GMER_MEM_EVT_TYPE_TE_STATE_VIOLATION 0x03 375 #define CXL_GMER_MEM_EVT_TYPE_SCRUB_MEDIA_ECC_ERROR 0x04 376 #define CXL_GMER_MEM_EVT_TYPE_AP_CME_COUNTER_EXPIRE 0x05 377 #define CXL_GMER_MEM_EVT_TYPE_CKID_VIOLATION 0x06 378 #define show_gmer_mem_event_type(type) __print_symbolic(type, \ 379 { CXL_GMER_MEM_EVT_TYPE_ECC_ERROR, "ECC Error" }, \ 380 { CXL_GMER_MEM_EVT_TYPE_INV_ADDR, "Invalid Address" }, \ 381 { CXL_GMER_MEM_EVT_TYPE_DATA_PATH_ERROR, "Data Path Error" }, \ 382 { CXL_GMER_MEM_EVT_TYPE_TE_STATE_VIOLATION, "TE State Violation" }, \ 383 { CXL_GMER_MEM_EVT_TYPE_SCRUB_MEDIA_ECC_ERROR, "Scrub Media ECC Error" }, \ 384 { CXL_GMER_MEM_EVT_TYPE_AP_CME_COUNTER_EXPIRE, "Adv Prog CME Counter Expiration" }, \ 385 { CXL_GMER_MEM_EVT_TYPE_CKID_VIOLATION, "CKID Violation" } \ 386 ) 387 388 #define CXL_GMER_TRANS_UNKNOWN 0x00 389 #define CXL_GMER_TRANS_HOST_READ 0x01 390 #define CXL_GMER_TRANS_HOST_WRITE 0x02 391 #define CXL_GMER_TRANS_HOST_SCAN_MEDIA 0x03 392 #define CXL_GMER_TRANS_HOST_INJECT_POISON 0x04 393 #define CXL_GMER_TRANS_INTERNAL_MEDIA_SCRUB 0x05 394 #define CXL_GMER_TRANS_INTERNAL_MEDIA_MANAGEMENT 0x06 395 #define CXL_GMER_TRANS_INTERNAL_MEDIA_ECS 0x07 396 #define CXL_GMER_TRANS_MEDIA_INITIALIZATION 0x08 397 #define show_trans_type(type) __print_symbolic(type, \ 398 { CXL_GMER_TRANS_UNKNOWN, "Unknown" }, \ 399 { CXL_GMER_TRANS_HOST_READ, "Host Read" }, \ 400 { CXL_GMER_TRANS_HOST_WRITE, "Host Write" }, \ 401 { CXL_GMER_TRANS_HOST_SCAN_MEDIA, "Host Scan Media" }, \ 402 { CXL_GMER_TRANS_HOST_INJECT_POISON, "Host Inject Poison" }, \ 403 { CXL_GMER_TRANS_INTERNAL_MEDIA_SCRUB, "Internal Media Scrub" }, \ 404 { CXL_GMER_TRANS_INTERNAL_MEDIA_MANAGEMENT, "Internal Media Management" }, \ 405 { CXL_GMER_TRANS_INTERNAL_MEDIA_ECS, "Internal Media Error Check Scrub" }, \ 406 { CXL_GMER_TRANS_MEDIA_INITIALIZATION, "Media Initialization" } \ 407 ) 408 409 #define CXL_GMER_VALID_CHANNEL BIT(0) 410 #define CXL_GMER_VALID_RANK BIT(1) 411 #define CXL_GMER_VALID_DEVICE BIT(2) 412 #define CXL_GMER_VALID_COMPONENT BIT(3) 413 #define CXL_GMER_VALID_COMPONENT_ID_FORMAT BIT(4) 414 #define show_valid_flags(flags) __print_flags(flags, "|", \ 415 { CXL_GMER_VALID_CHANNEL, "CHANNEL" }, \ 416 { CXL_GMER_VALID_RANK, "RANK" }, \ 417 { CXL_GMER_VALID_DEVICE, "DEVICE" }, \ 418 { CXL_GMER_VALID_COMPONENT, "COMPONENT" }, \ 419 { CXL_GMER_VALID_COMPONENT_ID_FORMAT, "COMPONENT PLDM FORMAT" } \ 420 ) 421 422 #define CXL_GMER_CME_EV_FLAG_CME_MULTIPLE_MEDIA BIT(0) 423 #define CXL_GMER_CME_EV_FLAG_THRESHOLD_EXCEEDED BIT(1) 424 #define show_cme_threshold_ev_flags(flags) __print_flags(flags, "|", \ 425 { \ 426 CXL_GMER_CME_EV_FLAG_CME_MULTIPLE_MEDIA, \ 427 "Corrected Memory Errors in Multiple Media Components" \ 428 }, { \ 429 CXL_GMER_CME_EV_FLAG_THRESHOLD_EXCEEDED, \ 430 "Exceeded Programmable Threshold" \ 431 } \ 432 ) 433 434 #define CXL_GMER_MEM_EVT_SUB_TYPE_NOT_REPORTED 0x00 435 #define CXL_GMER_MEM_EVT_SUB_TYPE_INTERNAL_DATAPATH_ERROR 0x01 436 #define CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_COMMAND_TRAINING_ERROR 0x02 437 #define CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_CONTROL_TRAINING_ERROR 0x03 438 #define CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_DATA_TRAINING_ERROR 0x04 439 #define CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_CRC_ERROR 0x05 440 #define show_mem_event_sub_type(sub_type) __print_symbolic(sub_type, \ 441 { CXL_GMER_MEM_EVT_SUB_TYPE_NOT_REPORTED, "Not Reported" }, \ 442 { CXL_GMER_MEM_EVT_SUB_TYPE_INTERNAL_DATAPATH_ERROR, "Internal Datapath Error" }, \ 443 { \ 444 CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_COMMAND_TRAINING_ERROR, \ 445 "Media Link Command Training Error" \ 446 }, { \ 447 CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_CONTROL_TRAINING_ERROR, \ 448 "Media Link Control Training Error" \ 449 }, { \ 450 CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_DATA_TRAINING_ERROR, \ 451 "Media Link Data Training Error" \ 452 }, { \ 453 CXL_GMER_MEM_EVT_SUB_TYPE_MEDIA_LINK_CRC_ERROR, "Media Link CRC Error" \ 454 } \ 455 ) 456 457 TRACE_EVENT(cxl_general_media, 458 459 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, 460 struct cxl_region *cxlr, u64 hpa, u64 hpa_alias0, 461 struct cxl_event_gen_media *rec), 462 463 TP_ARGS(cxlmd, log, cxlr, hpa, hpa_alias0, rec), 464 465 TP_STRUCT__entry( 466 CXL_EVT_TP_entry 467 /* General Media */ 468 __field(u64, dpa) 469 __field(u8, descriptor) 470 __field(u8, type) 471 __field(u8, transaction_type) 472 __field(u8, channel) 473 __field(u32, device) 474 __array(u8, comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE) 475 /* Following are out of order to pack trace record */ 476 __field(u64, hpa) 477 __field(u64, hpa_alias0) 478 __field_struct(uuid_t, region_uuid) 479 __field(u16, validity_flags) 480 __field(u8, rank) 481 __field(u8, dpa_flags) 482 __field(u32, cme_count) 483 __field(u8, sub_type) 484 __field(u8, cme_threshold_ev_flags) 485 __string(region_name, cxlr ? dev_name(&cxlr->dev) : "") 486 ), 487 488 TP_fast_assign( 489 CXL_EVT_TP_fast_assign(cxlmd, log, rec->media_hdr.hdr); 490 __entry->hdr_uuid = CXL_EVENT_GEN_MEDIA_UUID; 491 492 /* General Media */ 493 __entry->dpa = le64_to_cpu(rec->media_hdr.phys_addr); 494 __entry->dpa_flags = __entry->dpa & CXL_DPA_FLAGS_MASK; 495 /* Mask after flags have been parsed */ 496 __entry->dpa &= CXL_DPA_MASK; 497 __entry->descriptor = rec->media_hdr.descriptor; 498 __entry->type = rec->media_hdr.type; 499 __entry->sub_type = rec->sub_type; 500 __entry->transaction_type = rec->media_hdr.transaction_type; 501 __entry->channel = rec->media_hdr.channel; 502 __entry->rank = rec->media_hdr.rank; 503 __entry->device = get_unaligned_le24(rec->device); 504 memcpy(__entry->comp_id, &rec->component_id, 505 CXL_EVENT_GEN_MED_COMP_ID_SIZE); 506 __entry->validity_flags = get_unaligned_le16(&rec->media_hdr.validity_flags); 507 __entry->hpa = hpa; 508 __entry->hpa_alias0 = hpa_alias0; 509 if (cxlr) { 510 __assign_str(region_name); 511 uuid_copy(&__entry->region_uuid, &cxlr->params.uuid); 512 } else { 513 __assign_str(region_name); 514 uuid_copy(&__entry->region_uuid, &uuid_null); 515 } 516 __entry->cme_threshold_ev_flags = rec->cme_threshold_ev_flags; 517 if (rec->media_hdr.descriptor & CXL_GMER_EVT_DESC_THRESHOLD_EVENT) 518 __entry->cme_count = get_unaligned_le24(rec->cme_count); 519 else 520 __entry->cme_count = 0; 521 ), 522 523 CXL_EVT_TP_printk("dpa=%llx dpa_flags='%s' " \ 524 "descriptor='%s' type='%s' sub_type='%s' " \ 525 "transaction_type='%s' channel=%u rank=%u " \ 526 "device=%x validity_flags='%s' " \ 527 "comp_id=%s comp_id_pldm_valid_flags='%s' " \ 528 "pldm_entity_id=%s pldm_resource_id=%s " \ 529 "hpa=%llx hpa_alias0=%llx region=%s region_uuid=%pUb " \ 530 "cme_threshold_ev_flags='%s' cme_count=%u", 531 __entry->dpa, show_dpa_flags(__entry->dpa_flags), 532 show_event_desc_flags(__entry->descriptor), 533 show_gmer_mem_event_type(__entry->type), 534 show_mem_event_sub_type(__entry->sub_type), 535 show_trans_type(__entry->transaction_type), 536 __entry->channel, __entry->rank, __entry->device, 537 show_valid_flags(__entry->validity_flags), 538 __print_hex(__entry->comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE), 539 show_comp_id_pldm_flags(__entry->comp_id[0]), 540 show_pldm_entity_id(__entry->validity_flags, CXL_GMER_VALID_COMPONENT, 541 CXL_GMER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id), 542 show_pldm_resource_id(__entry->validity_flags, CXL_GMER_VALID_COMPONENT, 543 CXL_GMER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id), 544 __entry->hpa, __entry->hpa_alias0, __get_str(region_name), &__entry->region_uuid, 545 show_cme_threshold_ev_flags(__entry->cme_threshold_ev_flags), __entry->cme_count 546 ) 547 ); 548 549 /* 550 * DRAM Event Record - DER 551 * 552 * CXL rev 3.1 section 8.2.9.2.1.2; Table 8-46 553 */ 554 /* 555 * DRAM Event Record defines many fields the same as the General Media Event 556 * Record. Reuse those definitions as appropriate. 557 */ 558 #define CXL_DER_MEM_EVT_TYPE_ECC_ERROR 0x00 559 #define CXL_DER_MEM_EVT_TYPE_SCRUB_MEDIA_ECC_ERROR 0x01 560 #define CXL_DER_MEM_EVT_TYPE_INV_ADDR 0x02 561 #define CXL_DER_MEM_EVT_TYPE_DATA_PATH_ERROR 0x03 562 #define CXL_DER_MEM_EVT_TYPE_TE_STATE_VIOLATION 0x04 563 #define CXL_DER_MEM_EVT_TYPE_AP_CME_COUNTER_EXPIRE 0x05 564 #define CXL_DER_MEM_EVT_TYPE_CKID_VIOLATION 0x06 565 #define show_dram_mem_event_type(type) __print_symbolic(type, \ 566 { CXL_DER_MEM_EVT_TYPE_ECC_ERROR, "ECC Error" }, \ 567 { CXL_DER_MEM_EVT_TYPE_SCRUB_MEDIA_ECC_ERROR, "Scrub Media ECC Error" }, \ 568 { CXL_DER_MEM_EVT_TYPE_INV_ADDR, "Invalid Address" }, \ 569 { CXL_DER_MEM_EVT_TYPE_DATA_PATH_ERROR, "Data Path Error" }, \ 570 { CXL_DER_MEM_EVT_TYPE_TE_STATE_VIOLATION, "TE State Violation" }, \ 571 { CXL_DER_MEM_EVT_TYPE_AP_CME_COUNTER_EXPIRE, "Adv Prog CME Counter Expiration" }, \ 572 { CXL_DER_MEM_EVT_TYPE_CKID_VIOLATION, "CKID Violation" } \ 573 ) 574 575 #define CXL_DER_VALID_CHANNEL BIT(0) 576 #define CXL_DER_VALID_RANK BIT(1) 577 #define CXL_DER_VALID_NIBBLE BIT(2) 578 #define CXL_DER_VALID_BANK_GROUP BIT(3) 579 #define CXL_DER_VALID_BANK BIT(4) 580 #define CXL_DER_VALID_ROW BIT(5) 581 #define CXL_DER_VALID_COLUMN BIT(6) 582 #define CXL_DER_VALID_CORRECTION_MASK BIT(7) 583 #define CXL_DER_VALID_COMPONENT BIT(8) 584 #define CXL_DER_VALID_COMPONENT_ID_FORMAT BIT(9) 585 #define CXL_DER_VALID_SUB_CHANNEL BIT(10) 586 #define show_dram_valid_flags(flags) __print_flags(flags, "|", \ 587 { CXL_DER_VALID_CHANNEL, "CHANNEL" }, \ 588 { CXL_DER_VALID_RANK, "RANK" }, \ 589 { CXL_DER_VALID_NIBBLE, "NIBBLE" }, \ 590 { CXL_DER_VALID_BANK_GROUP, "BANK GROUP" }, \ 591 { CXL_DER_VALID_BANK, "BANK" }, \ 592 { CXL_DER_VALID_ROW, "ROW" }, \ 593 { CXL_DER_VALID_COLUMN, "COLUMN" }, \ 594 { CXL_DER_VALID_CORRECTION_MASK, "CORRECTION MASK" }, \ 595 { CXL_DER_VALID_COMPONENT, "COMPONENT" }, \ 596 { CXL_DER_VALID_COMPONENT_ID_FORMAT, "COMPONENT PLDM FORMAT" }, \ 597 { CXL_DER_VALID_SUB_CHANNEL, "SUB CHANNEL" } \ 598 ) 599 600 TRACE_EVENT(cxl_dram, 601 602 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, 603 struct cxl_region *cxlr, u64 hpa, u64 hpa_alias0, 604 struct cxl_event_dram *rec), 605 606 TP_ARGS(cxlmd, log, cxlr, hpa, hpa_alias0, rec), 607 608 TP_STRUCT__entry( 609 CXL_EVT_TP_entry 610 /* DRAM */ 611 __field(u64, dpa) 612 __field(u8, descriptor) 613 __field(u8, type) 614 __field(u8, transaction_type) 615 __field(u8, channel) 616 __field(u16, validity_flags) 617 __field(u16, column) /* Out of order to pack trace record */ 618 __field(u32, nibble_mask) 619 __field(u32, row) 620 __array(u8, cor_mask, CXL_EVENT_DER_CORRECTION_MASK_SIZE) 621 __field(u64, hpa) 622 __field(u64, hpa_alias0) 623 __field_struct(uuid_t, region_uuid) 624 __field(u8, rank) /* Out of order to pack trace record */ 625 __field(u8, bank_group) /* Out of order to pack trace record */ 626 __field(u8, bank) /* Out of order to pack trace record */ 627 __field(u8, dpa_flags) /* Out of order to pack trace record */ 628 /* Following are out of order to pack trace record */ 629 __array(u8, comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE) 630 __field(u32, cvme_count) 631 __field(u8, sub_type) 632 __field(u8, sub_channel) 633 __field(u8, cme_threshold_ev_flags) 634 __string(region_name, cxlr ? dev_name(&cxlr->dev) : "") 635 ), 636 637 TP_fast_assign( 638 CXL_EVT_TP_fast_assign(cxlmd, log, rec->media_hdr.hdr); 639 __entry->hdr_uuid = CXL_EVENT_DRAM_UUID; 640 641 /* DRAM */ 642 __entry->dpa = le64_to_cpu(rec->media_hdr.phys_addr); 643 __entry->dpa_flags = __entry->dpa & CXL_DPA_FLAGS_MASK; 644 __entry->dpa &= CXL_DPA_MASK; 645 __entry->descriptor = rec->media_hdr.descriptor; 646 __entry->type = rec->media_hdr.type; 647 __entry->sub_type = rec->sub_type; 648 __entry->transaction_type = rec->media_hdr.transaction_type; 649 __entry->validity_flags = get_unaligned_le16(rec->media_hdr.validity_flags); 650 __entry->channel = rec->media_hdr.channel; 651 __entry->rank = rec->media_hdr.rank; 652 __entry->nibble_mask = get_unaligned_le24(rec->nibble_mask); 653 __entry->bank_group = rec->bank_group; 654 __entry->bank = rec->bank; 655 __entry->row = get_unaligned_le24(rec->row); 656 __entry->column = get_unaligned_le16(rec->column); 657 memcpy(__entry->cor_mask, &rec->correction_mask, 658 CXL_EVENT_DER_CORRECTION_MASK_SIZE); 659 __entry->hpa = hpa; 660 __entry->hpa_alias0 = hpa_alias0; 661 if (cxlr) { 662 __assign_str(region_name); 663 uuid_copy(&__entry->region_uuid, &cxlr->params.uuid); 664 } else { 665 __assign_str(region_name); 666 uuid_copy(&__entry->region_uuid, &uuid_null); 667 } 668 memcpy(__entry->comp_id, &rec->component_id, 669 CXL_EVENT_GEN_MED_COMP_ID_SIZE); 670 __entry->sub_channel = rec->sub_channel; 671 __entry->cme_threshold_ev_flags = rec->cme_threshold_ev_flags; 672 if (rec->media_hdr.descriptor & CXL_GMER_EVT_DESC_THRESHOLD_EVENT) 673 __entry->cvme_count = get_unaligned_le24(rec->cvme_count); 674 else 675 __entry->cvme_count = 0; 676 ), 677 678 CXL_EVT_TP_printk("dpa=%llx dpa_flags='%s' descriptor='%s' type='%s' sub_type='%s' " \ 679 "transaction_type='%s' channel=%u rank=%u nibble_mask=%x " \ 680 "bank_group=%u bank=%u row=%u column=%u cor_mask=%s " \ 681 "validity_flags='%s' " \ 682 "comp_id=%s comp_id_pldm_valid_flags='%s' " \ 683 "pldm_entity_id=%s pldm_resource_id=%s " \ 684 "hpa=%llx hpa_alias0=%llx region=%s region_uuid=%pUb " \ 685 "sub_channel=%u cme_threshold_ev_flags='%s' cvme_count=%u", 686 __entry->dpa, show_dpa_flags(__entry->dpa_flags), 687 show_event_desc_flags(__entry->descriptor), 688 show_dram_mem_event_type(__entry->type), 689 show_mem_event_sub_type(__entry->sub_type), 690 show_trans_type(__entry->transaction_type), 691 __entry->channel, __entry->rank, __entry->nibble_mask, 692 __entry->bank_group, __entry->bank, 693 __entry->row, __entry->column, 694 __print_hex(__entry->cor_mask, CXL_EVENT_DER_CORRECTION_MASK_SIZE), 695 show_dram_valid_flags(__entry->validity_flags), 696 __print_hex(__entry->comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE), 697 show_comp_id_pldm_flags(__entry->comp_id[0]), 698 show_pldm_entity_id(__entry->validity_flags, CXL_DER_VALID_COMPONENT, 699 CXL_DER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id), 700 show_pldm_resource_id(__entry->validity_flags, CXL_DER_VALID_COMPONENT, 701 CXL_DER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id), 702 __entry->hpa, __entry->hpa_alias0, __get_str(region_name), &__entry->region_uuid, 703 __entry->sub_channel, show_cme_threshold_ev_flags(__entry->cme_threshold_ev_flags), 704 __entry->cvme_count 705 ) 706 ); 707 708 /* 709 * Memory Module Event Record - MMER 710 * 711 * CXL res 3.1 section 8.2.9.2.1.3; Table 8-47 712 */ 713 #define CXL_MMER_HEALTH_STATUS_CHANGE 0x00 714 #define CXL_MMER_MEDIA_STATUS_CHANGE 0x01 715 #define CXL_MMER_LIFE_USED_CHANGE 0x02 716 #define CXL_MMER_TEMP_CHANGE 0x03 717 #define CXL_MMER_DATA_PATH_ERROR 0x04 718 #define CXL_MMER_LSA_ERROR 0x05 719 #define CXL_MMER_UNRECOV_SIDEBAND_BUS_ERROR 0x06 720 #define CXL_MMER_MEMORY_MEDIA_FRU_ERROR 0x07 721 #define CXL_MMER_POWER_MANAGEMENT_FAULT 0x08 722 #define show_dev_evt_type(type) __print_symbolic(type, \ 723 { CXL_MMER_HEALTH_STATUS_CHANGE, "Health Status Change" }, \ 724 { CXL_MMER_MEDIA_STATUS_CHANGE, "Media Status Change" }, \ 725 { CXL_MMER_LIFE_USED_CHANGE, "Life Used Change" }, \ 726 { CXL_MMER_TEMP_CHANGE, "Temperature Change" }, \ 727 { CXL_MMER_DATA_PATH_ERROR, "Data Path Error" }, \ 728 { CXL_MMER_LSA_ERROR, "LSA Error" }, \ 729 { CXL_MMER_UNRECOV_SIDEBAND_BUS_ERROR, "Unrecoverable Internal Sideband Bus Error" }, \ 730 { CXL_MMER_MEMORY_MEDIA_FRU_ERROR, "Memory Media FRU Error" }, \ 731 { CXL_MMER_POWER_MANAGEMENT_FAULT, "Power Management Fault" } \ 732 ) 733 734 /* 735 * Device Health Information - DHI 736 * 737 * CXL res 3.1 section 8.2.9.9.3.1; Table 8-133 738 */ 739 #define CXL_DHI_HS_MAINTENANCE_NEEDED BIT(0) 740 #define CXL_DHI_HS_PERFORMANCE_DEGRADED BIT(1) 741 #define CXL_DHI_HS_HW_REPLACEMENT_NEEDED BIT(2) 742 #define CXL_DHI_HS_MEM_CAPACITY_DEGRADED BIT(3) 743 #define show_health_status_flags(flags) __print_flags(flags, "|", \ 744 { CXL_DHI_HS_MAINTENANCE_NEEDED, "MAINTENANCE_NEEDED" }, \ 745 { CXL_DHI_HS_PERFORMANCE_DEGRADED, "PERFORMANCE_DEGRADED" }, \ 746 { CXL_DHI_HS_HW_REPLACEMENT_NEEDED, "REPLACEMENT_NEEDED" }, \ 747 { CXL_DHI_HS_MEM_CAPACITY_DEGRADED, "MEM_CAPACITY_DEGRADED" } \ 748 ) 749 750 #define CXL_DHI_MS_NORMAL 0x00 751 #define CXL_DHI_MS_NOT_READY 0x01 752 #define CXL_DHI_MS_WRITE_PERSISTENCY_LOST 0x02 753 #define CXL_DHI_MS_ALL_DATA_LOST 0x03 754 #define CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_EVENT_POWER_LOSS 0x04 755 #define CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_EVENT_SHUTDOWN 0x05 756 #define CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_IMMINENT 0x06 757 #define CXL_DHI_MS_WRITE_ALL_DATA_LOSS_EVENT_POWER_LOSS 0x07 758 #define CXL_DHI_MS_WRITE_ALL_DATA_LOSS_EVENT_SHUTDOWN 0x08 759 #define CXL_DHI_MS_WRITE_ALL_DATA_LOSS_IMMINENT 0x09 760 #define show_media_status(ms) __print_symbolic(ms, \ 761 { CXL_DHI_MS_NORMAL, \ 762 "Normal" }, \ 763 { CXL_DHI_MS_NOT_READY, \ 764 "Not Ready" }, \ 765 { CXL_DHI_MS_WRITE_PERSISTENCY_LOST, \ 766 "Write Persistency Lost" }, \ 767 { CXL_DHI_MS_ALL_DATA_LOST, \ 768 "All Data Lost" }, \ 769 { CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_EVENT_POWER_LOSS, \ 770 "Write Persistency Loss in the Event of Power Loss" }, \ 771 { CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_EVENT_SHUTDOWN, \ 772 "Write Persistency Loss in Event of Shutdown" }, \ 773 { CXL_DHI_MS_WRITE_PERSISTENCY_LOSS_IMMINENT, \ 774 "Write Persistency Loss Imminent" }, \ 775 { CXL_DHI_MS_WRITE_ALL_DATA_LOSS_EVENT_POWER_LOSS, \ 776 "All Data Loss in Event of Power Loss" }, \ 777 { CXL_DHI_MS_WRITE_ALL_DATA_LOSS_EVENT_SHUTDOWN, \ 778 "All Data loss in the Event of Shutdown" }, \ 779 { CXL_DHI_MS_WRITE_ALL_DATA_LOSS_IMMINENT, \ 780 "All Data Loss Imminent" } \ 781 ) 782 783 #define CXL_DHI_AS_NORMAL 0x0 784 #define CXL_DHI_AS_WARNING 0x1 785 #define CXL_DHI_AS_CRITICAL 0x2 786 #define show_two_bit_status(as) __print_symbolic(as, \ 787 { CXL_DHI_AS_NORMAL, "Normal" }, \ 788 { CXL_DHI_AS_WARNING, "Warning" }, \ 789 { CXL_DHI_AS_CRITICAL, "Critical" } \ 790 ) 791 #define show_one_bit_status(as) __print_symbolic(as, \ 792 { CXL_DHI_AS_NORMAL, "Normal" }, \ 793 { CXL_DHI_AS_WARNING, "Warning" } \ 794 ) 795 796 #define CXL_DHI_AS_LIFE_USED(as) (as & 0x3) 797 #define CXL_DHI_AS_DEV_TEMP(as) ((as & 0xC) >> 2) 798 #define CXL_DHI_AS_COR_VOL_ERR_CNT(as) ((as & 0x10) >> 4) 799 #define CXL_DHI_AS_COR_PER_ERR_CNT(as) ((as & 0x20) >> 5) 800 801 #define CXL_MMER_VALID_COMPONENT BIT(0) 802 #define CXL_MMER_VALID_COMPONENT_ID_FORMAT BIT(1) 803 #define show_mem_module_valid_flags(flags) __print_flags(flags, "|", \ 804 { CXL_MMER_VALID_COMPONENT, "COMPONENT" }, \ 805 { CXL_MMER_VALID_COMPONENT_ID_FORMAT, "COMPONENT PLDM FORMAT" } \ 806 ) 807 #define CXL_MMER_DEV_EVT_SUB_TYPE_NOT_REPORTED 0x00 808 #define CXL_MMER_DEV_EVT_SUB_TYPE_INVALID_CONFIG_DATA 0x01 809 #define CXL_MMER_DEV_EVT_SUB_TYPE_UNSUPP_CONFIG_DATA 0x02 810 #define CXL_MMER_DEV_EVT_SUB_TYPE_UNSUPP_MEM_MEDIA_FRU 0x03 811 #define show_dev_event_sub_type(sub_type) __print_symbolic(sub_type, \ 812 { CXL_MMER_DEV_EVT_SUB_TYPE_NOT_REPORTED, "Not Reported" }, \ 813 { CXL_MMER_DEV_EVT_SUB_TYPE_INVALID_CONFIG_DATA, "Invalid Config Data" }, \ 814 { CXL_MMER_DEV_EVT_SUB_TYPE_UNSUPP_CONFIG_DATA, "Unsupported Config Data" }, \ 815 { \ 816 CXL_MMER_DEV_EVT_SUB_TYPE_UNSUPP_MEM_MEDIA_FRU, \ 817 "Unsupported Memory Media FRU" \ 818 } \ 819 ) 820 821 TRACE_EVENT(cxl_memory_module, 822 823 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, 824 struct cxl_event_mem_module *rec), 825 826 TP_ARGS(cxlmd, log, rec), 827 828 TP_STRUCT__entry( 829 CXL_EVT_TP_entry 830 831 /* Memory Module Event */ 832 __field(u8, event_type) 833 834 /* Device Health Info */ 835 __field(u8, health_status) 836 __field(u8, media_status) 837 __field(u8, life_used) 838 __field(u32, dirty_shutdown_cnt) 839 __field(u32, cor_vol_err_cnt) 840 __field(u32, cor_per_err_cnt) 841 __field(s16, device_temp) 842 __field(u8, add_status) 843 __field(u8, event_sub_type) 844 __array(u8, comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE) 845 __field(u16, validity_flags) 846 ), 847 848 TP_fast_assign( 849 CXL_EVT_TP_fast_assign(cxlmd, log, rec->hdr); 850 __entry->hdr_uuid = CXL_EVENT_MEM_MODULE_UUID; 851 852 /* Memory Module Event */ 853 __entry->event_type = rec->event_type; 854 __entry->event_sub_type = rec->event_sub_type; 855 856 /* Device Health Info */ 857 __entry->health_status = rec->info.health_status; 858 __entry->media_status = rec->info.media_status; 859 __entry->life_used = rec->info.life_used; 860 __entry->dirty_shutdown_cnt = get_unaligned_le32(rec->info.dirty_shutdown_cnt); 861 __entry->cor_vol_err_cnt = get_unaligned_le32(rec->info.cor_vol_err_cnt); 862 __entry->cor_per_err_cnt = get_unaligned_le32(rec->info.cor_per_err_cnt); 863 __entry->device_temp = get_unaligned_le16(rec->info.device_temp); 864 __entry->add_status = rec->info.add_status; 865 __entry->validity_flags = get_unaligned_le16(rec->validity_flags); 866 memcpy(__entry->comp_id, &rec->component_id, 867 CXL_EVENT_GEN_MED_COMP_ID_SIZE); 868 ), 869 870 CXL_EVT_TP_printk("event_type='%s' event_sub_type='%s' health_status='%s' " \ 871 "media_status='%s' as_life_used=%s as_dev_temp=%s as_cor_vol_err_cnt=%s " \ 872 "as_cor_per_err_cnt=%s life_used=%u device_temp=%d " \ 873 "dirty_shutdown_cnt=%u cor_vol_err_cnt=%u cor_per_err_cnt=%u " \ 874 "validity_flags='%s' " \ 875 "comp_id=%s comp_id_pldm_valid_flags='%s' " \ 876 "pldm_entity_id=%s pldm_resource_id=%s", 877 show_dev_evt_type(__entry->event_type), 878 show_dev_event_sub_type(__entry->event_sub_type), 879 show_health_status_flags(__entry->health_status), 880 show_media_status(__entry->media_status), 881 show_two_bit_status(CXL_DHI_AS_LIFE_USED(__entry->add_status)), 882 show_two_bit_status(CXL_DHI_AS_DEV_TEMP(__entry->add_status)), 883 show_one_bit_status(CXL_DHI_AS_COR_VOL_ERR_CNT(__entry->add_status)), 884 show_one_bit_status(CXL_DHI_AS_COR_PER_ERR_CNT(__entry->add_status)), 885 __entry->life_used, __entry->device_temp, 886 __entry->dirty_shutdown_cnt, __entry->cor_vol_err_cnt, 887 __entry->cor_per_err_cnt, 888 show_mem_module_valid_flags(__entry->validity_flags), 889 __print_hex(__entry->comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE), 890 show_comp_id_pldm_flags(__entry->comp_id[0]), 891 show_pldm_entity_id(__entry->validity_flags, CXL_MMER_VALID_COMPONENT, 892 CXL_MMER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id), 893 show_pldm_resource_id(__entry->validity_flags, CXL_MMER_VALID_COMPONENT, 894 CXL_MMER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id) 895 ) 896 ); 897 898 /* 899 * Memory Sparing Event Record - MSER 900 * 901 * CXL rev 3.2 section 8.2.10.2.1.4; Table 8-60 902 */ 903 #define CXL_MSER_QUERY_RESOURCE_FLAG BIT(0) 904 #define CXL_MSER_HARD_SPARING_FLAG BIT(1) 905 #define CXL_MSER_DEV_INITED_FLAG BIT(2) 906 #define show_mem_sparing_flags(flags) __print_flags(flags, "|", \ 907 { CXL_MSER_QUERY_RESOURCE_FLAG, "Query Resources" }, \ 908 { CXL_MSER_HARD_SPARING_FLAG, "Hard Sparing" }, \ 909 { CXL_MSER_DEV_INITED_FLAG, "Device Initiated Sparing" } \ 910 ) 911 912 #define CXL_MSER_VALID_CHANNEL BIT(0) 913 #define CXL_MSER_VALID_RANK BIT(1) 914 #define CXL_MSER_VALID_NIBBLE BIT(2) 915 #define CXL_MSER_VALID_BANK_GROUP BIT(3) 916 #define CXL_MSER_VALID_BANK BIT(4) 917 #define CXL_MSER_VALID_ROW BIT(5) 918 #define CXL_MSER_VALID_COLUMN BIT(6) 919 #define CXL_MSER_VALID_COMPONENT_ID BIT(7) 920 #define CXL_MSER_VALID_COMPONENT_ID_FORMAT BIT(8) 921 #define CXL_MSER_VALID_SUB_CHANNEL BIT(9) 922 #define show_mem_sparing_valid_flags(flags) __print_flags(flags, "|", \ 923 { CXL_MSER_VALID_CHANNEL, "CHANNEL" }, \ 924 { CXL_MSER_VALID_RANK, "RANK" }, \ 925 { CXL_MSER_VALID_NIBBLE, "NIBBLE" }, \ 926 { CXL_MSER_VALID_BANK_GROUP, "BANK GROUP" }, \ 927 { CXL_MSER_VALID_BANK, "BANK" }, \ 928 { CXL_MSER_VALID_ROW, "ROW" }, \ 929 { CXL_MSER_VALID_COLUMN, "COLUMN" }, \ 930 { CXL_MSER_VALID_COMPONENT_ID, "COMPONENT ID" }, \ 931 { CXL_MSER_VALID_COMPONENT_ID_FORMAT, "COMPONENT ID PLDM FORMAT" }, \ 932 { CXL_MSER_VALID_SUB_CHANNEL, "SUB CHANNEL" } \ 933 ) 934 935 TRACE_EVENT(cxl_memory_sparing, 936 937 TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, 938 struct cxl_event_mem_sparing *rec), 939 940 TP_ARGS(cxlmd, log, rec), 941 942 TP_STRUCT__entry( 943 CXL_EVT_TP_entry 944 945 /* Memory Sparing Event */ 946 __field(u8, flags) 947 __field(u8, result) 948 __field(u16, validity_flags) 949 __field(u16, res_avail) 950 __field(u8, channel) 951 __field(u8, rank) 952 __field(u32, nibble_mask) 953 __field(u8, bank_group) 954 __field(u8, bank) 955 __field(u32, row) 956 __field(u16, column) 957 __field(u8, sub_channel) 958 __array(u8, comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE) 959 ), 960 961 TP_fast_assign( 962 CXL_EVT_TP_fast_assign(cxlmd, log, rec->hdr); 963 __entry->hdr_uuid = CXL_EVENT_MEM_SPARING_UUID; 964 965 /* Memory Sparing Event */ 966 __entry->flags = rec->flags; 967 __entry->result = rec->result; 968 __entry->validity_flags = le16_to_cpu(rec->validity_flags); 969 __entry->res_avail = le16_to_cpu(rec->res_avail); 970 __entry->channel = rec->channel; 971 __entry->rank = rec->rank; 972 __entry->nibble_mask = get_unaligned_le24(rec->nibble_mask); 973 __entry->bank_group = rec->bank_group; 974 __entry->bank = rec->bank; 975 __entry->row = get_unaligned_le24(rec->row); 976 __entry->column = le16_to_cpu(rec->column); 977 __entry->sub_channel = rec->sub_channel; 978 memcpy(__entry->comp_id, &rec->component_id, 979 CXL_EVENT_GEN_MED_COMP_ID_SIZE); 980 ), 981 982 CXL_EVT_TP_printk("flags='%s' result=%u validity_flags='%s' " \ 983 "spare resource avail=%u channel=%u rank=%u " \ 984 "nibble_mask=%x bank_group=%u bank=%u " \ 985 "row=%u column=%u sub_channel=%u " \ 986 "comp_id=%s comp_id_pldm_valid_flags='%s' " \ 987 "pldm_entity_id=%s pldm_resource_id=%s", 988 show_mem_sparing_flags(__entry->flags), 989 __entry->result, 990 show_mem_sparing_valid_flags(__entry->validity_flags), 991 __entry->res_avail, __entry->channel, __entry->rank, 992 __entry->nibble_mask, __entry->bank_group, __entry->bank, 993 __entry->row, __entry->column, __entry->sub_channel, 994 __print_hex(__entry->comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE), 995 show_comp_id_pldm_flags(__entry->comp_id[0]), 996 show_pldm_entity_id(__entry->validity_flags, CXL_MSER_VALID_COMPONENT_ID, 997 CXL_MSER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id), 998 show_pldm_resource_id(__entry->validity_flags, CXL_MSER_VALID_COMPONENT_ID, 999 CXL_MSER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id) 1000 ) 1001 ); 1002 1003 #define show_poison_trace_type(type) \ 1004 __print_symbolic(type, \ 1005 { CXL_POISON_TRACE_LIST, "List" }, \ 1006 { CXL_POISON_TRACE_INJECT, "Inject" }, \ 1007 { CXL_POISON_TRACE_CLEAR, "Clear" }) 1008 1009 #define __show_poison_source(source) \ 1010 __print_symbolic(source, \ 1011 { CXL_POISON_SOURCE_UNKNOWN, "Unknown" }, \ 1012 { CXL_POISON_SOURCE_EXTERNAL, "External" }, \ 1013 { CXL_POISON_SOURCE_INTERNAL, "Internal" }, \ 1014 { CXL_POISON_SOURCE_INJECTED, "Injected" }, \ 1015 { CXL_POISON_SOURCE_VENDOR, "Vendor" }) 1016 1017 #define show_poison_source(source) \ 1018 (((source > CXL_POISON_SOURCE_INJECTED) && \ 1019 (source != CXL_POISON_SOURCE_VENDOR)) ? "Reserved" \ 1020 : __show_poison_source(source)) 1021 1022 #define show_poison_flags(flags) \ 1023 __print_flags(flags, "|", \ 1024 { CXL_POISON_FLAG_MORE, "More" }, \ 1025 { CXL_POISON_FLAG_OVERFLOW, "Overflow" }, \ 1026 { CXL_POISON_FLAG_SCANNING, "Scanning" }) 1027 1028 #define __cxl_poison_addr(record) \ 1029 (le64_to_cpu(record->address)) 1030 #define cxl_poison_record_dpa(record) \ 1031 (__cxl_poison_addr(record) & CXL_POISON_START_MASK) 1032 #define cxl_poison_record_source(record) \ 1033 (__cxl_poison_addr(record) & CXL_POISON_SOURCE_MASK) 1034 #define cxl_poison_record_dpa_length(record) \ 1035 (le32_to_cpu(record->length) * CXL_POISON_LEN_MULT) 1036 #define cxl_poison_overflow(flags, time) \ 1037 (flags & CXL_POISON_FLAG_OVERFLOW ? le64_to_cpu(time) : 0) 1038 1039 TRACE_EVENT(cxl_poison, 1040 1041 TP_PROTO(struct cxl_memdev *cxlmd, struct cxl_region *cxlr, 1042 const struct cxl_poison_record *record, u8 flags, 1043 __le64 overflow_ts, enum cxl_poison_trace_type trace_type), 1044 1045 TP_ARGS(cxlmd, cxlr, record, flags, overflow_ts, trace_type), 1046 1047 TP_STRUCT__entry( 1048 __string(memdev, dev_name(&cxlmd->dev)) 1049 __string(host, dev_name(cxlmd->dev.parent)) 1050 __field(u64, serial) 1051 __field(u8, trace_type) 1052 __string(region, cxlr ? dev_name(&cxlr->dev) : "") 1053 __field(u64, overflow_ts) 1054 __field(u64, hpa) 1055 __field(u64, hpa_alias0) 1056 __field(u64, dpa) 1057 __field(u32, dpa_length) 1058 __array(char, uuid, 16) 1059 __field(u8, source) 1060 __field(u8, flags) 1061 ), 1062 1063 TP_fast_assign( 1064 __assign_str(memdev); 1065 __assign_str(host); 1066 __entry->serial = cxlmd->cxlds->serial; 1067 __entry->overflow_ts = cxl_poison_overflow(flags, overflow_ts); 1068 __entry->dpa = cxl_poison_record_dpa(record); 1069 __entry->dpa_length = cxl_poison_record_dpa_length(record); 1070 __entry->source = cxl_poison_record_source(record); 1071 __entry->trace_type = trace_type; 1072 __entry->flags = flags; 1073 if (cxlr) { 1074 __assign_str(region); 1075 memcpy(__entry->uuid, &cxlr->params.uuid, 16); 1076 __entry->hpa = cxl_dpa_to_hpa(cxlr, cxlmd, 1077 __entry->dpa); 1078 if (__entry->hpa != ULLONG_MAX && cxlr->params.cache_size) 1079 __entry->hpa_alias0 = __entry->hpa - 1080 cxlr->params.cache_size; 1081 else 1082 __entry->hpa_alias0 = ULLONG_MAX; 1083 } else { 1084 __assign_str(region); 1085 memset(__entry->uuid, 0, 16); 1086 __entry->hpa = ULLONG_MAX; 1087 __entry->hpa_alias0 = ULLONG_MAX; 1088 } 1089 ), 1090 1091 TP_printk("memdev=%s host=%s serial=%lld trace_type=%s region=%s " \ 1092 "region_uuid=%pU hpa=0x%llx hpa_alias0=0x%llx dpa=0x%llx " \ 1093 "dpa_length=0x%x source=%s flags=%s overflow_time=%llu", 1094 __get_str(memdev), 1095 __get_str(host), 1096 __entry->serial, 1097 show_poison_trace_type(__entry->trace_type), 1098 __get_str(region), 1099 __entry->uuid, 1100 __entry->hpa, 1101 __entry->hpa_alias0, 1102 __entry->dpa, 1103 __entry->dpa_length, 1104 show_poison_source(__entry->source), 1105 show_poison_flags(__entry->flags), 1106 __entry->overflow_ts 1107 ) 1108 ); 1109 1110 #endif /* _CXL_EVENTS_H */ 1111 1112 #define TRACE_INCLUDE_FILE trace 1113 #include <trace/define_trace.h> 1114