1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright(c) 2020 Intel Corporation. */ 3 #include <linux/io-64-nonatomic-lo-hi.h> 4 #include <linux/device.h> 5 #include <linux/slab.h> 6 #include <linux/pci.h> 7 #include <cxlmem.h> 8 #include <cxlpci.h> 9 10 /** 11 * DOC: cxl registers 12 * 13 * CXL device capabilities are enumerated by PCI DVSEC (Designated 14 * Vendor-specific) and / or descriptors provided by platform firmware. 15 * They can be defined as a set like the device and component registers 16 * mandated by CXL Section 8.1.12.2 Memory Device PCIe Capabilities and 17 * Extended Capabilities, or they can be individual capabilities 18 * appended to bridged and endpoint devices. 19 * 20 * Provide common infrastructure for enumerating and mapping these 21 * discrete capabilities. 22 */ 23 24 /** 25 * cxl_probe_component_regs() - Detect CXL Component register blocks 26 * @dev: Host device of the @base mapping 27 * @base: Mapping containing the HDM Decoder Capability Header 28 * @map: Map object describing the register block information found 29 * 30 * See CXL 2.0 8.2.4 Component Register Layout and Definition 31 * See CXL 2.0 8.2.5.5 CXL Device Register Interface 32 * 33 * Probe for component register information and return it in map object. 34 */ 35 void cxl_probe_component_regs(struct device *dev, void __iomem *base, 36 struct cxl_component_reg_map *map) 37 { 38 int cap, cap_count; 39 u32 cap_array; 40 41 *map = (struct cxl_component_reg_map) { 0 }; 42 43 /* 44 * CXL.cache and CXL.mem registers are at offset 0x1000 as defined in 45 * CXL 2.0 8.2.4 Table 141. 46 */ 47 base += CXL_CM_OFFSET; 48 49 cap_array = readl(base + CXL_CM_CAP_HDR_OFFSET); 50 51 if (FIELD_GET(CXL_CM_CAP_HDR_ID_MASK, cap_array) != CM_CAP_HDR_CAP_ID) { 52 dev_err(dev, 53 "Couldn't locate the CXL.cache and CXL.mem capability array header.\n"); 54 return; 55 } 56 57 /* It's assumed that future versions will be backward compatible */ 58 cap_count = FIELD_GET(CXL_CM_CAP_HDR_ARRAY_SIZE_MASK, cap_array); 59 60 for (cap = 1; cap <= cap_count; cap++) { 61 void __iomem *register_block; 62 u32 hdr; 63 int decoder_cnt; 64 u16 cap_id, offset; 65 u32 length; 66 67 hdr = readl(base + cap * 0x4); 68 69 cap_id = FIELD_GET(CXL_CM_CAP_HDR_ID_MASK, hdr); 70 offset = FIELD_GET(CXL_CM_CAP_PTR_MASK, hdr); 71 register_block = base + offset; 72 73 switch (cap_id) { 74 case CXL_CM_CAP_CAP_ID_HDM: 75 dev_dbg(dev, "found HDM decoder capability (0x%x)\n", 76 offset); 77 78 hdr = readl(register_block); 79 80 decoder_cnt = cxl_hdm_decoder_count(hdr); 81 length = 0x20 * decoder_cnt + 0x10; 82 83 map->hdm_decoder.valid = true; 84 map->hdm_decoder.offset = CXL_CM_OFFSET + offset; 85 map->hdm_decoder.size = length; 86 break; 87 default: 88 dev_dbg(dev, "Unknown CM cap ID: %d (0x%x)\n", cap_id, 89 offset); 90 break; 91 } 92 } 93 } 94 EXPORT_SYMBOL_NS_GPL(cxl_probe_component_regs, CXL); 95 96 /** 97 * cxl_probe_device_regs() - Detect CXL Device register blocks 98 * @dev: Host device of the @base mapping 99 * @base: Mapping of CXL 2.0 8.2.8 CXL Device Register Interface 100 * @map: Map object describing the register block information found 101 * 102 * Probe for device register information and return it in map object. 103 */ 104 void cxl_probe_device_regs(struct device *dev, void __iomem *base, 105 struct cxl_device_reg_map *map) 106 { 107 int cap, cap_count; 108 u64 cap_array; 109 110 *map = (struct cxl_device_reg_map){ 0 }; 111 112 cap_array = readq(base + CXLDEV_CAP_ARRAY_OFFSET); 113 if (FIELD_GET(CXLDEV_CAP_ARRAY_ID_MASK, cap_array) != 114 CXLDEV_CAP_ARRAY_CAP_ID) 115 return; 116 117 cap_count = FIELD_GET(CXLDEV_CAP_ARRAY_COUNT_MASK, cap_array); 118 119 for (cap = 1; cap <= cap_count; cap++) { 120 u32 offset, length; 121 u16 cap_id; 122 123 cap_id = FIELD_GET(CXLDEV_CAP_HDR_CAP_ID_MASK, 124 readl(base + cap * 0x10)); 125 offset = readl(base + cap * 0x10 + 0x4); 126 length = readl(base + cap * 0x10 + 0x8); 127 128 switch (cap_id) { 129 case CXLDEV_CAP_CAP_ID_DEVICE_STATUS: 130 dev_dbg(dev, "found Status capability (0x%x)\n", offset); 131 132 map->status.valid = true; 133 map->status.offset = offset; 134 map->status.size = length; 135 break; 136 case CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX: 137 dev_dbg(dev, "found Mailbox capability (0x%x)\n", offset); 138 map->mbox.valid = true; 139 map->mbox.offset = offset; 140 map->mbox.size = length; 141 break; 142 case CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX: 143 dev_dbg(dev, "found Secondary Mailbox capability (0x%x)\n", offset); 144 break; 145 case CXLDEV_CAP_CAP_ID_MEMDEV: 146 dev_dbg(dev, "found Memory Device capability (0x%x)\n", offset); 147 map->memdev.valid = true; 148 map->memdev.offset = offset; 149 map->memdev.size = length; 150 break; 151 default: 152 if (cap_id >= 0x8000) 153 dev_dbg(dev, "Vendor cap ID: %#x offset: %#x\n", cap_id, offset); 154 else 155 dev_dbg(dev, "Unknown cap ID: %#x offset: %#x\n", cap_id, offset); 156 break; 157 } 158 } 159 } 160 EXPORT_SYMBOL_NS_GPL(cxl_probe_device_regs, CXL); 161 162 void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr, 163 resource_size_t length) 164 { 165 void __iomem *ret_val; 166 struct resource *res; 167 168 res = devm_request_mem_region(dev, addr, length, dev_name(dev)); 169 if (!res) { 170 resource_size_t end = addr + length - 1; 171 172 dev_err(dev, "Failed to request region %pa-%pa\n", &addr, &end); 173 return NULL; 174 } 175 176 ret_val = devm_ioremap(dev, addr, length); 177 if (!ret_val) 178 dev_err(dev, "Failed to map region %pr\n", res); 179 180 return ret_val; 181 } 182 183 int cxl_map_component_regs(struct pci_dev *pdev, 184 struct cxl_component_regs *regs, 185 struct cxl_register_map *map) 186 { 187 struct device *dev = &pdev->dev; 188 resource_size_t phys_addr; 189 resource_size_t length; 190 191 phys_addr = pci_resource_start(pdev, map->barno); 192 phys_addr += map->block_offset; 193 194 phys_addr += map->component_map.hdm_decoder.offset; 195 length = map->component_map.hdm_decoder.size; 196 regs->hdm_decoder = devm_cxl_iomap_block(dev, phys_addr, length); 197 if (!regs->hdm_decoder) 198 return -ENOMEM; 199 200 return 0; 201 } 202 EXPORT_SYMBOL_NS_GPL(cxl_map_component_regs, CXL); 203 204 int cxl_map_device_regs(struct pci_dev *pdev, 205 struct cxl_device_regs *regs, 206 struct cxl_register_map *map) 207 { 208 struct device *dev = &pdev->dev; 209 resource_size_t phys_addr; 210 211 phys_addr = pci_resource_start(pdev, map->barno); 212 phys_addr += map->block_offset; 213 214 if (map->device_map.status.valid) { 215 resource_size_t addr; 216 resource_size_t length; 217 218 addr = phys_addr + map->device_map.status.offset; 219 length = map->device_map.status.size; 220 regs->status = devm_cxl_iomap_block(dev, addr, length); 221 if (!regs->status) 222 return -ENOMEM; 223 } 224 225 if (map->device_map.mbox.valid) { 226 resource_size_t addr; 227 resource_size_t length; 228 229 addr = phys_addr + map->device_map.mbox.offset; 230 length = map->device_map.mbox.size; 231 regs->mbox = devm_cxl_iomap_block(dev, addr, length); 232 if (!regs->mbox) 233 return -ENOMEM; 234 } 235 236 if (map->device_map.memdev.valid) { 237 resource_size_t addr; 238 resource_size_t length; 239 240 addr = phys_addr + map->device_map.memdev.offset; 241 length = map->device_map.memdev.size; 242 regs->memdev = devm_cxl_iomap_block(dev, addr, length); 243 if (!regs->memdev) 244 return -ENOMEM; 245 } 246 247 return 0; 248 } 249 EXPORT_SYMBOL_NS_GPL(cxl_map_device_regs, CXL); 250 251 static void cxl_decode_regblock(u32 reg_lo, u32 reg_hi, 252 struct cxl_register_map *map) 253 { 254 map->block_offset = ((u64)reg_hi << 32) | 255 (reg_lo & CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK); 256 map->barno = FIELD_GET(CXL_DVSEC_REG_LOCATOR_BIR_MASK, reg_lo); 257 map->reg_type = FIELD_GET(CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK, reg_lo); 258 } 259 260 /** 261 * cxl_find_regblock() - Locate register blocks by type 262 * @pdev: The CXL PCI device to enumerate. 263 * @type: Register Block Indicator id 264 * @map: Enumeration output, clobbered on error 265 * 266 * Return: 0 if register block enumerated, negative error code otherwise 267 * 268 * A CXL DVSEC may point to one or more register blocks, search for them 269 * by @type. 270 */ 271 int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, 272 struct cxl_register_map *map) 273 { 274 u32 regloc_size, regblocks; 275 int regloc, i; 276 277 map->block_offset = U64_MAX; 278 regloc = pci_find_dvsec_capability(pdev, PCI_DVSEC_VENDOR_ID_CXL, 279 CXL_DVSEC_REG_LOCATOR); 280 if (!regloc) 281 return -ENXIO; 282 283 pci_read_config_dword(pdev, regloc + PCI_DVSEC_HEADER1, ®loc_size); 284 regloc_size = FIELD_GET(PCI_DVSEC_HEADER1_LENGTH_MASK, regloc_size); 285 286 regloc += CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET; 287 regblocks = (regloc_size - CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET) / 8; 288 289 for (i = 0; i < regblocks; i++, regloc += 8) { 290 u32 reg_lo, reg_hi; 291 292 pci_read_config_dword(pdev, regloc, ®_lo); 293 pci_read_config_dword(pdev, regloc + 4, ®_hi); 294 295 cxl_decode_regblock(reg_lo, reg_hi, map); 296 297 if (map->reg_type == type) 298 return 0; 299 } 300 301 map->block_offset = U64_MAX; 302 return -ENODEV; 303 } 304 EXPORT_SYMBOL_NS_GPL(cxl_find_regblock, CXL); 305