1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020 Intel Corporation. */ 3 4 #ifndef __CXL_CORE_H__ 5 #define __CXL_CORE_H__ 6 7 #include <cxl/mailbox.h> 8 #include <linux/rwsem.h> 9 10 extern const struct device_type cxl_nvdimm_bridge_type; 11 extern const struct device_type cxl_nvdimm_type; 12 extern const struct device_type cxl_pmu_type; 13 14 extern struct attribute_group cxl_base_attribute_group; 15 16 enum cxl_detach_mode { 17 DETACH_ONLY, 18 DETACH_INVALIDATE, 19 }; 20 21 #ifdef CONFIG_CXL_REGION 22 23 struct cxl_region_context { 24 struct cxl_endpoint_decoder *cxled; 25 struct range hpa_range; 26 int interleave_ways; 27 int interleave_granularity; 28 }; 29 30 extern struct device_attribute dev_attr_create_pmem_region; 31 extern struct device_attribute dev_attr_create_ram_region; 32 extern struct device_attribute dev_attr_delete_region; 33 extern struct device_attribute dev_attr_region; 34 extern const struct device_type cxl_pmem_region_type; 35 extern const struct device_type cxl_dax_region_type; 36 extern const struct device_type cxl_region_type; 37 38 int cxl_decoder_detach(struct cxl_region *cxlr, 39 struct cxl_endpoint_decoder *cxled, int pos, 40 enum cxl_detach_mode mode); 41 42 #define CXL_REGION_ATTR(x) (&dev_attr_##x.attr) 43 #define CXL_REGION_TYPE(x) (&cxl_region_type) 44 #define SET_CXL_REGION_ATTR(x) (&dev_attr_##x.attr), 45 #define CXL_PMEM_REGION_TYPE(x) (&cxl_pmem_region_type) 46 #define CXL_DAX_REGION_TYPE(x) (&cxl_dax_region_type) 47 int cxl_region_init(void); 48 void cxl_region_exit(void); 49 int cxl_get_poison_by_endpoint(struct cxl_port *port); 50 struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 dpa); 51 u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, const struct cxl_memdev *cxlmd, 52 u64 dpa); 53 int devm_cxl_add_dax_region(struct cxl_region *cxlr); 54 int devm_cxl_add_pmem_region(struct cxl_region *cxlr); 55 56 #else 57 static inline u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, 58 const struct cxl_memdev *cxlmd, u64 dpa) 59 { 60 return ULLONG_MAX; 61 } 62 static inline 63 struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 dpa) 64 { 65 return NULL; 66 } 67 static inline int cxl_get_poison_by_endpoint(struct cxl_port *port) 68 { 69 return 0; 70 } 71 static inline int cxl_decoder_detach(struct cxl_region *cxlr, 72 struct cxl_endpoint_decoder *cxled, 73 int pos, enum cxl_detach_mode mode) 74 { 75 return 0; 76 } 77 static inline int cxl_region_init(void) 78 { 79 return 0; 80 } 81 static inline void cxl_region_exit(void) 82 { 83 } 84 #define CXL_REGION_ATTR(x) NULL 85 #define CXL_REGION_TYPE(x) NULL 86 #define SET_CXL_REGION_ATTR(x) 87 #define CXL_PMEM_REGION_TYPE(x) NULL 88 #define CXL_DAX_REGION_TYPE(x) NULL 89 #endif 90 91 struct cxl_send_command; 92 struct cxl_mem_query_commands; 93 int cxl_query_cmd(struct cxl_mailbox *cxl_mbox, 94 struct cxl_mem_query_commands __user *q); 95 int cxl_send_cmd(struct cxl_mailbox *cxl_mbox, struct cxl_send_command __user *s); 96 void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr, 97 resource_size_t length); 98 99 struct dentry *cxl_debugfs_create_dir(const char *dir); 100 int cxl_dpa_set_part(struct cxl_endpoint_decoder *cxled, 101 enum cxl_partition_mode mode); 102 int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, u64 size); 103 int cxl_dpa_free(struct cxl_endpoint_decoder *cxled); 104 resource_size_t cxl_dpa_size(struct cxl_endpoint_decoder *cxled); 105 resource_size_t cxl_dpa_resource_start(struct cxl_endpoint_decoder *cxled); 106 bool cxl_resource_contains_addr(const struct resource *res, const resource_size_t addr); 107 108 enum cxl_rcrb { 109 CXL_RCRB_DOWNSTREAM, 110 CXL_RCRB_UPSTREAM, 111 }; 112 struct cxl_rcrb_info; 113 resource_size_t __rcrb_to_component(struct device *dev, 114 struct cxl_rcrb_info *ri, 115 enum cxl_rcrb which); 116 u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb); 117 118 #define PCI_RCRB_CAP_LIST_ID_MASK GENMASK(7, 0) 119 #define PCI_RCRB_CAP_HDR_ID_MASK GENMASK(7, 0) 120 #define PCI_RCRB_CAP_HDR_NEXT_MASK GENMASK(15, 8) 121 #define PCI_CAP_EXP_SIZEOF 0x3c 122 123 struct cxl_rwsem { 124 /* 125 * All changes to HPA (interleave configuration) occur with this 126 * lock held for write. 127 */ 128 struct rw_semaphore region; 129 /* 130 * All changes to a device DPA space occur with this lock held 131 * for write. 132 */ 133 struct rw_semaphore dpa; 134 }; 135 136 extern struct cxl_rwsem cxl_rwsem; 137 138 int cxl_memdev_init(void); 139 void cxl_memdev_exit(void); 140 void cxl_mbox_init(void); 141 142 enum cxl_poison_trace_type { 143 CXL_POISON_TRACE_LIST, 144 CXL_POISON_TRACE_INJECT, 145 CXL_POISON_TRACE_CLEAR, 146 }; 147 148 enum poison_cmd_enabled_bits; 149 bool cxl_memdev_has_poison_cmd(struct cxl_memdev *cxlmd, 150 enum poison_cmd_enabled_bits cmd); 151 152 long cxl_pci_get_latency(struct pci_dev *pdev); 153 int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c); 154 int cxl_port_get_switch_dport_bandwidth(struct cxl_port *port, 155 struct access_coordinate *c); 156 157 static inline struct device *port_to_host(struct cxl_port *port) 158 { 159 struct cxl_port *parent = is_cxl_root(port) ? NULL : 160 to_cxl_port(port->dev.parent); 161 162 /* 163 * The host of CXL root port and the first level of ports is 164 * the platform firmware device, the host of all other ports 165 * is their parent port. 166 */ 167 if (!parent) 168 return port->uport_dev; 169 else if (is_cxl_root(parent)) 170 return parent->uport_dev; 171 else 172 return &parent->dev; 173 } 174 175 static inline struct device *dport_to_host(struct cxl_dport *dport) 176 { 177 struct cxl_port *port = dport->port; 178 179 if (is_cxl_root(port)) 180 return port->uport_dev; 181 return &port->dev; 182 } 183 #ifdef CONFIG_CXL_RAS 184 int cxl_ras_init(void); 185 void cxl_ras_exit(void); 186 bool cxl_handle_ras(struct device *dev, void __iomem *ras_base); 187 void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base); 188 void cxl_dport_map_rch_aer(struct cxl_dport *dport); 189 void cxl_disable_rch_root_ints(struct cxl_dport *dport); 190 void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds); 191 void devm_cxl_dport_ras_setup(struct cxl_dport *dport); 192 #else 193 static inline int cxl_ras_init(void) 194 { 195 return 0; 196 } 197 static inline void cxl_ras_exit(void) { } 198 static inline bool cxl_handle_ras(struct device *dev, void __iomem *ras_base) 199 { 200 return false; 201 } 202 static inline void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) { } 203 static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { } 204 static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { } 205 static inline void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) { } 206 static inline void devm_cxl_dport_ras_setup(struct cxl_dport *dport) { } 207 #endif /* CONFIG_CXL_RAS */ 208 209 int cxl_gpf_port_setup(struct cxl_dport *dport); 210 211 struct cxl_hdm; 212 int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, 213 struct cxl_endpoint_dvsec_info *info); 214 int cxl_port_get_possible_dports(struct cxl_port *port); 215 216 #ifdef CONFIG_CXL_FEATURES 217 struct cxl_feat_entry * 218 cxl_feature_info(struct cxl_features_state *cxlfs, const uuid_t *uuid); 219 size_t cxl_get_feature(struct cxl_mailbox *cxl_mbox, const uuid_t *feat_uuid, 220 enum cxl_get_feat_selection selection, 221 void *feat_out, size_t feat_out_size, u16 offset, 222 u16 *return_code); 223 int cxl_set_feature(struct cxl_mailbox *cxl_mbox, const uuid_t *feat_uuid, 224 u8 feat_version, const void *feat_data, 225 size_t feat_data_size, u32 feat_flag, u16 offset, 226 u16 *return_code); 227 #endif 228 229 resource_size_t cxl_rcd_component_reg_phys(struct device *dev, 230 struct cxl_dport *dport); 231 #endif /* __CXL_CORE_H__ */ 232