1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020 Intel Corporation. */ 3 4 #ifndef __CXL_CORE_H__ 5 #define __CXL_CORE_H__ 6 7 #include <cxl/mailbox.h> 8 #include <linux/rwsem.h> 9 10 extern const struct device_type cxl_nvdimm_bridge_type; 11 extern const struct device_type cxl_nvdimm_type; 12 extern const struct device_type cxl_pmu_type; 13 14 extern struct attribute_group cxl_base_attribute_group; 15 16 enum cxl_detach_mode { 17 DETACH_ONLY, 18 DETACH_INVALIDATE, 19 }; 20 21 #ifdef CONFIG_CXL_REGION 22 23 struct cxl_region_context { 24 struct cxl_endpoint_decoder *cxled; 25 struct range hpa_range; 26 int interleave_ways; 27 int interleave_granularity; 28 }; 29 30 extern struct device_attribute dev_attr_create_pmem_region; 31 extern struct device_attribute dev_attr_create_ram_region; 32 extern struct device_attribute dev_attr_delete_region; 33 extern struct device_attribute dev_attr_region; 34 extern const struct device_type cxl_pmem_region_type; 35 extern const struct device_type cxl_dax_region_type; 36 extern const struct device_type cxl_region_type; 37 38 int cxl_decoder_detach(struct cxl_region *cxlr, 39 struct cxl_endpoint_decoder *cxled, int pos, 40 enum cxl_detach_mode mode); 41 42 #define CXL_REGION_ATTR(x) (&dev_attr_##x.attr) 43 #define CXL_REGION_TYPE(x) (&cxl_region_type) 44 #define SET_CXL_REGION_ATTR(x) (&dev_attr_##x.attr), 45 #define CXL_PMEM_REGION_TYPE(x) (&cxl_pmem_region_type) 46 #define CXL_DAX_REGION_TYPE(x) (&cxl_dax_region_type) 47 int cxl_region_init(void); 48 void cxl_region_exit(void); 49 int cxl_get_poison_by_endpoint(struct cxl_port *port); 50 struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 dpa); 51 u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, const struct cxl_memdev *cxlmd, 52 u64 dpa); 53 54 #else 55 static inline u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, 56 const struct cxl_memdev *cxlmd, u64 dpa) 57 { 58 return ULLONG_MAX; 59 } 60 static inline 61 struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 dpa) 62 { 63 return NULL; 64 } 65 static inline int cxl_get_poison_by_endpoint(struct cxl_port *port) 66 { 67 return 0; 68 } 69 static inline int cxl_decoder_detach(struct cxl_region *cxlr, 70 struct cxl_endpoint_decoder *cxled, 71 int pos, enum cxl_detach_mode mode) 72 { 73 return 0; 74 } 75 static inline int cxl_region_init(void) 76 { 77 return 0; 78 } 79 static inline void cxl_region_exit(void) 80 { 81 } 82 #define CXL_REGION_ATTR(x) NULL 83 #define CXL_REGION_TYPE(x) NULL 84 #define SET_CXL_REGION_ATTR(x) 85 #define CXL_PMEM_REGION_TYPE(x) NULL 86 #define CXL_DAX_REGION_TYPE(x) NULL 87 #endif 88 89 struct cxl_send_command; 90 struct cxl_mem_query_commands; 91 int cxl_query_cmd(struct cxl_mailbox *cxl_mbox, 92 struct cxl_mem_query_commands __user *q); 93 int cxl_send_cmd(struct cxl_mailbox *cxl_mbox, struct cxl_send_command __user *s); 94 void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr, 95 resource_size_t length); 96 97 struct dentry *cxl_debugfs_create_dir(const char *dir); 98 int cxl_dpa_set_part(struct cxl_endpoint_decoder *cxled, 99 enum cxl_partition_mode mode); 100 int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, u64 size); 101 int cxl_dpa_free(struct cxl_endpoint_decoder *cxled); 102 resource_size_t cxl_dpa_size(struct cxl_endpoint_decoder *cxled); 103 resource_size_t cxl_dpa_resource_start(struct cxl_endpoint_decoder *cxled); 104 bool cxl_resource_contains_addr(const struct resource *res, const resource_size_t addr); 105 106 enum cxl_rcrb { 107 CXL_RCRB_DOWNSTREAM, 108 CXL_RCRB_UPSTREAM, 109 }; 110 struct cxl_rcrb_info; 111 resource_size_t __rcrb_to_component(struct device *dev, 112 struct cxl_rcrb_info *ri, 113 enum cxl_rcrb which); 114 u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb); 115 116 #define PCI_RCRB_CAP_LIST_ID_MASK GENMASK(7, 0) 117 #define PCI_RCRB_CAP_HDR_ID_MASK GENMASK(7, 0) 118 #define PCI_RCRB_CAP_HDR_NEXT_MASK GENMASK(15, 8) 119 #define PCI_CAP_EXP_SIZEOF 0x3c 120 121 struct cxl_rwsem { 122 /* 123 * All changes to HPA (interleave configuration) occur with this 124 * lock held for write. 125 */ 126 struct rw_semaphore region; 127 /* 128 * All changes to a device DPA space occur with this lock held 129 * for write. 130 */ 131 struct rw_semaphore dpa; 132 }; 133 134 extern struct cxl_rwsem cxl_rwsem; 135 136 int cxl_memdev_init(void); 137 void cxl_memdev_exit(void); 138 void cxl_mbox_init(void); 139 140 enum cxl_poison_trace_type { 141 CXL_POISON_TRACE_LIST, 142 CXL_POISON_TRACE_INJECT, 143 CXL_POISON_TRACE_CLEAR, 144 }; 145 146 enum poison_cmd_enabled_bits; 147 bool cxl_memdev_has_poison_cmd(struct cxl_memdev *cxlmd, 148 enum poison_cmd_enabled_bits cmd); 149 150 long cxl_pci_get_latency(struct pci_dev *pdev); 151 int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c); 152 int cxl_port_get_switch_dport_bandwidth(struct cxl_port *port, 153 struct access_coordinate *c); 154 155 static inline struct device *port_to_host(struct cxl_port *port) 156 { 157 struct cxl_port *parent = is_cxl_root(port) ? NULL : 158 to_cxl_port(port->dev.parent); 159 160 /* 161 * The host of CXL root port and the first level of ports is 162 * the platform firmware device, the host of all other ports 163 * is their parent port. 164 */ 165 if (!parent) 166 return port->uport_dev; 167 else if (is_cxl_root(parent)) 168 return parent->uport_dev; 169 else 170 return &parent->dev; 171 } 172 173 static inline struct device *dport_to_host(struct cxl_dport *dport) 174 { 175 struct cxl_port *port = dport->port; 176 177 if (is_cxl_root(port)) 178 return port->uport_dev; 179 return &port->dev; 180 } 181 #ifdef CONFIG_CXL_RAS 182 int cxl_ras_init(void); 183 void cxl_ras_exit(void); 184 bool cxl_handle_ras(struct device *dev, void __iomem *ras_base); 185 void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base); 186 void cxl_dport_map_rch_aer(struct cxl_dport *dport); 187 void cxl_disable_rch_root_ints(struct cxl_dport *dport); 188 void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds); 189 void devm_cxl_dport_ras_setup(struct cxl_dport *dport); 190 #else 191 static inline int cxl_ras_init(void) 192 { 193 return 0; 194 } 195 static inline void cxl_ras_exit(void) { } 196 static inline bool cxl_handle_ras(struct device *dev, void __iomem *ras_base) 197 { 198 return false; 199 } 200 static inline void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) { } 201 static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { } 202 static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { } 203 static inline void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) { } 204 static inline void devm_cxl_dport_ras_setup(struct cxl_dport *dport) { } 205 #endif /* CONFIG_CXL_RAS */ 206 207 int cxl_gpf_port_setup(struct cxl_dport *dport); 208 209 struct cxl_hdm; 210 int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, 211 struct cxl_endpoint_dvsec_info *info); 212 int cxl_port_get_possible_dports(struct cxl_port *port); 213 214 #ifdef CONFIG_CXL_FEATURES 215 struct cxl_feat_entry * 216 cxl_feature_info(struct cxl_features_state *cxlfs, const uuid_t *uuid); 217 size_t cxl_get_feature(struct cxl_mailbox *cxl_mbox, const uuid_t *feat_uuid, 218 enum cxl_get_feat_selection selection, 219 void *feat_out, size_t feat_out_size, u16 offset, 220 u16 *return_code); 221 int cxl_set_feature(struct cxl_mailbox *cxl_mbox, const uuid_t *feat_uuid, 222 u8 feat_version, const void *feat_data, 223 size_t feat_data_size, u32 feat_flag, u16 offset, 224 u16 *return_code); 225 #endif 226 227 #endif /* __CXL_CORE_H__ */ 228