xref: /linux/drivers/cxl/Makefile (revision b1966a1fd218e1f5d5376bf352f9a4c26aba50b5)
14cdadfd5SDan Williams# SPDX-License-Identifier: GPL-2.0
2*6575b268SDan Williams
3*6575b268SDan Williams# Order is important here for the built-in case:
4*6575b268SDan Williams# - 'core' first for fundamental init
5*6575b268SDan Williams# - 'port' before platform root drivers like 'acpi' so that CXL-root ports
6*6575b268SDan Williams#   are immediately enabled
7*6575b268SDan Williams# - 'mem' and 'pmem' before endpoint drivers so that memdevs are
8*6575b268SDan Williams#   immediately enabled
9*6575b268SDan Williams# - 'pci' last, also mirrors the hardware enumeration hierarchy
109ea4dcf4SDan Williamsobj-y += core/
11*6575b268SDan Williamsobj-$(CONFIG_CXL_PORT) += cxl_port.o
124812be97SDan Williamsobj-$(CONFIG_CXL_ACPI) += cxl_acpi.o
138fdcb170SDan Williamsobj-$(CONFIG_CXL_PMEM) += cxl_pmem.o
14*6575b268SDan Williamsobj-$(CONFIG_CXL_MEM) += cxl_mem.o
15*6575b268SDan Williamsobj-$(CONFIG_CXL_PCI) += cxl_pci.o
164cdadfd5SDan Williams
17*6575b268SDan Williamscxl_port-y := port.o
184812be97SDan Williamscxl_acpi-y := acpi.o
1932828115SDave Jiangcxl_pmem-y := pmem.o security.o
20*6575b268SDan Williamscxl_mem-y := mem.o
21*6575b268SDan Williamscxl_pci-y := pci.o
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