1# SPDX-License-Identifier: GPL-2.0-only 2menuconfig CXL_BUS 3 tristate "CXL (Compute Express Link) Devices Support" 4 depends on PCI 5 select FW_LOADER 6 select FW_UPLOAD 7 select PCI_DOE 8 select FIRMWARE_TABLE 9 select NUMA_KEEP_MEMINFO if NUMA_MEMBLKS 10 help 11 CXL is a bus that is electrically compatible with PCI Express, but 12 layers three protocols on that signalling (CXL.io, CXL.cache, and 13 CXL.mem). The CXL.cache protocol allows devices to hold cachelines 14 locally, the CXL.mem protocol allows devices to be fully coherent 15 memory targets, the CXL.io protocol is equivalent to PCI Express. 16 Say 'y' to enable support for the configuration and management of 17 devices supporting these protocols. 18 19if CXL_BUS 20 21config CXL_PCI 22 tristate "PCI manageability" 23 default CXL_BUS 24 help 25 The CXL specification defines a "CXL memory device" sub-class in the 26 PCI "memory controller" base class of devices. Device's identified by 27 this class code provide support for volatile and / or persistent 28 memory to be mapped into the system address map (Host-managed Device 29 Memory (HDM)). 30 31 Say 'y/m' to enable a driver that will attach to CXL memory expander 32 devices enumerated by the memory device class code for configuration 33 and management primarily via the mailbox interface. See Chapter 2.3 34 Type 3 CXL Device in the CXL 2.0 specification for more details. 35 36 If unsure say 'm'. 37 38config CXL_MEM_RAW_COMMANDS 39 bool "RAW Command Interface for Memory Devices" 40 depends on CXL_PCI 41 help 42 Enable CXL RAW command interface. 43 44 The CXL driver ioctl interface may assign a kernel ioctl command 45 number for each specification defined opcode. At any given point in 46 time the number of opcodes that the specification defines and a device 47 may implement may exceed the kernel's set of associated ioctl function 48 numbers. The mismatch is either by omission, specification is too new, 49 or by design. When prototyping new hardware, or developing / debugging 50 the driver it is useful to be able to submit any possible command to 51 the hardware, even commands that may crash the kernel due to their 52 potential impact to memory currently in use by the kernel. 53 54 If developing CXL hardware or the driver say Y, otherwise say N. 55 56config CXL_ACPI 57 tristate "CXL ACPI: Platform Support" 58 depends on ACPI 59 depends on ACPI_NUMA 60 default CXL_BUS 61 select ACPI_TABLE_LIB 62 select ACPI_HMAT 63 select CXL_PORT 64 help 65 Enable support for host managed device memory (HDM) resources 66 published by a platform's ACPI CXL memory layout description. See 67 Chapter 9.14.1 CXL Early Discovery Table (CEDT) in the CXL 2.0 68 specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS) 69 (https://www.computeexpresslink.org/spec-landing). The CXL core 70 consumes these resource to publish the root of a cxl_port decode 71 hierarchy to map regions that represent System RAM, or Persistent 72 Memory regions to be managed by LIBNVDIMM. 73 74 If unsure say 'm'. 75 76config CXL_PMEM 77 tristate "CXL PMEM: Persistent Memory Support" 78 depends on LIBNVDIMM 79 default CXL_BUS 80 help 81 In addition to typical memory resources a platform may also advertise 82 support for persistent memory attached via CXL. This support is 83 managed via a bridge driver from CXL to the LIBNVDIMM system 84 subsystem. Say 'y/m' to enable support for enumerating and 85 provisioning the persistent memory capacity of CXL memory expanders. 86 87 If unsure say 'm'. 88 89config CXL_MEM 90 tristate "CXL: Memory Expansion" 91 depends on CXL_PCI 92 default CXL_BUS 93 help 94 The CXL.mem protocol allows a device to act as a provider of "System 95 RAM" and/or "Persistent Memory" that is fully coherent as if the 96 memory were attached to the typical CPU memory controller. This is 97 known as HDM "Host-managed Device Memory". 98 99 Say 'y/m' to enable a driver that will attach to CXL.mem devices for 100 memory expansion and control of HDM. See Chapter 9.13 in the CXL 2.0 101 specification for a detailed description of HDM. 102 103 If unsure say 'm'. 104 105config CXL_PORT 106 default CXL_BUS 107 tristate 108 109config CXL_SUSPEND 110 def_bool y 111 depends on SUSPEND && CXL_MEM 112 113config CXL_REGION 114 bool "CXL: Region Support" 115 default CXL_BUS 116 # For MAX_PHYSMEM_BITS 117 depends on SPARSEMEM 118 select MEMREGION 119 select GET_FREE_REGION 120 help 121 Enable the CXL core to enumerate and provision CXL regions. A CXL 122 region is defined by one or more CXL expanders that decode a given 123 system-physical address range. For CXL regions established by 124 platform-firmware this option enables memory error handling to 125 identify the devices participating in a given interleaved memory 126 range. Otherwise, platform-firmware managed CXL is enabled by being 127 placed in the system address map and does not need a driver. 128 129 If unsure say 'y' 130 131config CXL_REGION_INVALIDATION_TEST 132 bool "CXL: Region Cache Management Bypass (TEST)" 133 depends on CXL_REGION 134 help 135 CXL Region management and security operations potentially invalidate 136 the content of CPU caches without notifying those caches to 137 invalidate the affected cachelines. The CXL Region driver attempts 138 to invalidate caches when those events occur. If that invalidation 139 fails the region will fail to enable. Reasons for cache 140 invalidation failure are due to the CPU not providing a cache 141 invalidation mechanism. For example usage of wbinvd is restricted to 142 bare metal x86. However, for testing purposes toggling this option 143 can disable that data integrity safety and proceed with enabling 144 regions when there might be conflicting contents in the CPU cache. 145 146 If unsure, or if this kernel is meant for production environments, 147 say N. 148 149endif 150