1# SPDX-License-Identifier: GPL-2.0-only 2menuconfig CXL_BUS 3 tristate "CXL (Compute Express Link) Devices Support" 4 depends on PCI 5 select FW_LOADER 6 select FW_UPLOAD 7 select PCI_DOE 8 select FIRMWARE_TABLE 9 select NUMA_KEEP_MEMINFO if NUMA_MEMBLKS 10 select FWCTL if CXL_FEATURES 11 help 12 CXL is a bus that is electrically compatible with PCI Express, but 13 layers three protocols on that signalling (CXL.io, CXL.cache, and 14 CXL.mem). The CXL.cache protocol allows devices to hold cachelines 15 locally, the CXL.mem protocol allows devices to be fully coherent 16 memory targets, the CXL.io protocol is equivalent to PCI Express. 17 Say 'y' to enable support for the configuration and management of 18 devices supporting these protocols. 19 20if CXL_BUS 21 22config CXL_PCI 23 tristate "PCI manageability" 24 default CXL_BUS 25 select CXL_MEM 26 help 27 The CXL specification defines a "CXL memory device" sub-class in the 28 PCI "memory controller" base class of devices. Device's identified by 29 this class code provide support for volatile and / or persistent 30 memory to be mapped into the system address map (Host-managed Device 31 Memory (HDM)). 32 33 Say 'y/m' to enable a driver that will attach to CXL memory expander 34 devices enumerated by the memory device class code for configuration 35 and management primarily via the mailbox interface. See Chapter 2.3 36 Type 3 CXL Device in the CXL 2.0 specification for more details. 37 38 If unsure say 'm'. 39 40config CXL_MEM_RAW_COMMANDS 41 bool "RAW Command Interface for Memory Devices" 42 depends on CXL_PCI 43 help 44 Enable CXL RAW command interface. 45 46 The CXL driver ioctl interface may assign a kernel ioctl command 47 number for each specification defined opcode. At any given point in 48 time the number of opcodes that the specification defines and a device 49 may implement may exceed the kernel's set of associated ioctl function 50 numbers. The mismatch is either by omission, specification is too new, 51 or by design. When prototyping new hardware, or developing / debugging 52 the driver it is useful to be able to submit any possible command to 53 the hardware, even commands that may crash the kernel due to their 54 potential impact to memory currently in use by the kernel. 55 56 If developing CXL hardware or the driver say Y, otherwise say N. 57 58config CXL_ACPI 59 tristate "CXL ACPI: Platform Support" 60 depends on ACPI 61 depends on ACPI_NUMA 62 depends on CXL_PMEM || !CXL_PMEM 63 default CXL_BUS 64 select ACPI_TABLE_LIB 65 select ACPI_HMAT 66 select CXL_PORT 67 help 68 Enable support for host managed device memory (HDM) resources 69 published by a platform's ACPI CXL memory layout description. See 70 Chapter 9.14.1 CXL Early Discovery Table (CEDT) in the CXL 2.0 71 specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS) 72 (https://www.computeexpresslink.org/spec-landing). The CXL core 73 consumes these resource to publish the root of a cxl_port decode 74 hierarchy to map regions that represent System RAM, or Persistent 75 Memory regions to be managed by LIBNVDIMM. 76 77 If unsure say 'm'. 78 79config CXL_PMEM 80 tristate "CXL PMEM: Persistent Memory Support" 81 depends on LIBNVDIMM 82 default CXL_BUS 83 help 84 In addition to typical memory resources a platform may also advertise 85 support for persistent memory attached via CXL. This support is 86 managed via a bridge driver from CXL to the LIBNVDIMM system 87 subsystem. Say 'y/m' to enable support for enumerating and 88 provisioning the persistent memory capacity of CXL memory expanders. 89 90 If unsure say 'm'. 91 92config CXL_MEM 93 tristate "CXL: Memory Expansion" 94 default CXL_BUS 95 help 96 The CXL.mem protocol allows a device to act as a provider of "System 97 RAM" and/or "Persistent Memory" that is fully coherent as if the 98 memory were attached to the typical CPU memory controller. This is 99 known as HDM "Host-managed Device Memory". 100 101 Say 'y/m' to enable a driver that will attach to CXL.mem devices for 102 memory expansion and control of HDM. See Chapter 9.13 in the CXL 2.0 103 specification for a detailed description of HDM. 104 105 If unsure say 'm'. 106 107config CXL_FEATURES 108 bool "CXL: Features" 109 depends on CXL_PCI 110 help 111 Enable support for CXL Features. A CXL device that includes a mailbox 112 supports commands that allows listing, getting, and setting of 113 optionally defined features such as memory sparing or post package 114 sparing. Vendors may define custom features for the device. 115 116 If unsure say 'n' 117 118config CXL_EDAC_MEM_FEATURES 119 bool "CXL: EDAC Memory Features" 120 depends on EXPERT 121 depends on CXL_MEM 122 depends on CXL_FEATURES 123 depends on EDAC >= CXL_BUS 124 help 125 The CXL EDAC memory feature is optional and allows host to 126 control the EDAC memory features configurations of CXL memory 127 expander devices. 128 129 Say 'y' if you have an expert need to change default settings 130 of a memory RAS feature established by the platform/device. 131 Otherwise say 'n'. 132 133config CXL_EDAC_SCRUB 134 bool "Enable CXL Patrol Scrub Control (Patrol Read)" 135 depends on CXL_EDAC_MEM_FEATURES 136 depends on EDAC_SCRUB 137 help 138 The CXL EDAC scrub control is optional and allows host to 139 control the scrub feature configurations of CXL memory expander 140 devices. 141 142 When enabled 'cxl_mem' and 'cxl_region' EDAC devices are 143 published with memory scrub control attributes as described by 144 Documentation/ABI/testing/sysfs-edac-scrub. 145 146 Say 'y' if you have an expert need to change default settings 147 of a memory scrub feature established by the platform/device 148 (e.g. scrub rates for the patrol scrub feature). 149 Otherwise say 'n'. 150 151config CXL_EDAC_ECS 152 bool "Enable CXL Error Check Scrub (Repair)" 153 depends on CXL_EDAC_MEM_FEATURES 154 depends on EDAC_ECS 155 help 156 The CXL EDAC ECS control is optional and allows host to 157 control the ECS feature configurations of CXL memory expander 158 devices. 159 160 When enabled 'cxl_mem' EDAC devices are published with memory 161 ECS control attributes as described by 162 Documentation/ABI/testing/sysfs-edac-ecs. 163 164 Say 'y' if you have an expert need to change default settings 165 of a memory ECS feature established by the platform/device. 166 Otherwise say 'n'. 167 168config CXL_EDAC_MEM_REPAIR 169 bool "Enable CXL Memory Repair" 170 depends on CXL_EDAC_MEM_FEATURES 171 depends on EDAC_MEM_REPAIR 172 help 173 The CXL EDAC memory repair control is optional and allows host 174 to control the memory repair features (e.g. sparing, PPR) 175 configurations of CXL memory expander devices. 176 177 When enabled, the memory repair feature requires an additional 178 memory of approximately 43KB to store CXL DRAM and CXL general 179 media event records. 180 181 When enabled 'cxl_mem' EDAC devices are published with memory 182 repair control attributes as described by 183 Documentation/ABI/testing/sysfs-edac-memory-repair. 184 185 Say 'y' if you have an expert need to change default settings 186 of a memory repair feature established by the platform/device. 187 Otherwise say 'n'. 188 189config CXL_PORT 190 default CXL_BUS 191 tristate 192 193config CXL_SUSPEND 194 def_bool y 195 depends on SUSPEND && CXL_MEM 196 197config CXL_REGION 198 bool "CXL: Region Support" 199 default CXL_BUS 200 # For MAX_PHYSMEM_BITS 201 depends on SPARSEMEM 202 select MEMREGION 203 select GET_FREE_REGION 204 help 205 Enable the CXL core to enumerate and provision CXL regions. A CXL 206 region is defined by one or more CXL expanders that decode a given 207 system-physical address range. For CXL regions established by 208 platform-firmware this option enables memory error handling to 209 identify the devices participating in a given interleaved memory 210 range. Otherwise, platform-firmware managed CXL is enabled by being 211 placed in the system address map and does not need a driver. 212 213 If unsure say 'y' 214 215config CXL_REGION_INVALIDATION_TEST 216 bool "CXL: Region Cache Management Bypass (TEST)" 217 depends on CXL_REGION 218 help 219 CXL Region management and security operations potentially invalidate 220 the content of CPU caches without notifying those caches to 221 invalidate the affected cachelines. The CXL Region driver attempts 222 to invalidate caches when those events occur. If that invalidation 223 fails the region will fail to enable. Reasons for cache 224 invalidation failure are due to the CPU not providing a cache 225 invalidation mechanism. For example usage of wbinvd is restricted to 226 bare metal x86. However, for testing purposes toggling this option 227 can disable that data integrity safety and proceed with enabling 228 regions when there might be conflicting contents in the CPU cache. 229 230 If unsure, or if this kernel is meant for production environments, 231 say N. 232 233config CXL_MCE 234 def_bool y 235 depends on X86_MCE && MEMORY_FAILURE 236 237config CXL_RAS 238 def_bool y 239 depends on ACPI_APEI_GHES && PCIEAER && CXL_BUS 240 241config CXL_ATL 242 def_bool y 243 depends on CXL_REGION 244 depends on ACPI_PRMT && AMD_NB 245 246endif 247