14cdadfd5SDan Williams# SPDX-License-Identifier: GPL-2.0-only 24cdadfd5SDan Williamsmenuconfig CXL_BUS 34cdadfd5SDan Williams tristate "CXL (Compute Express Link) Devices Support" 44cdadfd5SDan Williams depends on PCI 54cdadfd5SDan Williams help 64cdadfd5SDan Williams CXL is a bus that is electrically compatible with PCI Express, but 74cdadfd5SDan Williams layers three protocols on that signalling (CXL.io, CXL.cache, and 84cdadfd5SDan Williams CXL.mem). The CXL.cache protocol allows devices to hold cachelines 94cdadfd5SDan Williams locally, the CXL.mem protocol allows devices to be fully coherent 104cdadfd5SDan Williams memory targets, the CXL.io protocol is equivalent to PCI Express. 114cdadfd5SDan Williams Say 'y' to enable support for the configuration and management of 124cdadfd5SDan Williams devices supporting these protocols. 134cdadfd5SDan Williams 144cdadfd5SDan Williamsif CXL_BUS 154cdadfd5SDan Williams 164cdadfd5SDan Williamsconfig CXL_MEM 174cdadfd5SDan Williams tristate "CXL.mem: Memory Devices" 183feaa2d3SDan Williams default CXL_BUS 194cdadfd5SDan Williams help 204cdadfd5SDan Williams The CXL.mem protocol allows a device to act as a provider of 214cdadfd5SDan Williams "System RAM" and/or "Persistent Memory" that is fully coherent 224cdadfd5SDan Williams as if the memory was attached to the typical CPU memory 234cdadfd5SDan Williams controller. 244cdadfd5SDan Williams 2521e9f767SBen Widawsky Say 'y/m' to enable a driver that will attach to CXL.mem devices for 2621e9f767SBen Widawsky configuration and management primarily via the mailbox interface. See 2721e9f767SBen Widawsky Chapter 2.3 Type 3 CXL Device in the CXL 2.0 specification for more 2821e9f767SBen Widawsky details. 294cdadfd5SDan Williams 304cdadfd5SDan Williams If unsure say 'm'. 3113237183SBen Widawsky 3213237183SBen Widawskyconfig CXL_MEM_RAW_COMMANDS 3313237183SBen Widawsky bool "RAW Command Interface for Memory Devices" 3413237183SBen Widawsky depends on CXL_MEM 3513237183SBen Widawsky help 3613237183SBen Widawsky Enable CXL RAW command interface. 3713237183SBen Widawsky 3813237183SBen Widawsky The CXL driver ioctl interface may assign a kernel ioctl command 3913237183SBen Widawsky number for each specification defined opcode. At any given point in 4013237183SBen Widawsky time the number of opcodes that the specification defines and a device 4113237183SBen Widawsky may implement may exceed the kernel's set of associated ioctl function 4213237183SBen Widawsky numbers. The mismatch is either by omission, specification is too new, 4313237183SBen Widawsky or by design. When prototyping new hardware, or developing / debugging 4413237183SBen Widawsky the driver it is useful to be able to submit any possible command to 4513237183SBen Widawsky the hardware, even commands that may crash the kernel due to their 4613237183SBen Widawsky potential impact to memory currently in use by the kernel. 4713237183SBen Widawsky 4813237183SBen Widawsky If developing CXL hardware or the driver say Y, otherwise say N. 494812be97SDan Williams 504812be97SDan Williamsconfig CXL_ACPI 514812be97SDan Williams tristate "CXL ACPI: Platform Support" 524812be97SDan Williams depends on ACPI 533feaa2d3SDan Williams default CXL_BUS 54*f4ce1f76SDan Williams select ACPI_TABLE_LIB 554812be97SDan Williams help 564812be97SDan Williams Enable support for host managed device memory (HDM) resources 574812be97SDan Williams published by a platform's ACPI CXL memory layout description. See 584812be97SDan Williams Chapter 9.14.1 CXL Early Discovery Table (CEDT) in the CXL 2.0 594812be97SDan Williams specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS) 604812be97SDan Williams (https://www.computeexpresslink.org/spec-landing). The CXL core 614812be97SDan Williams consumes these resource to publish the root of a cxl_port decode 624812be97SDan Williams hierarchy to map regions that represent System RAM, or Persistent 634812be97SDan Williams Memory regions to be managed by LIBNVDIMM. 644812be97SDan Williams 654812be97SDan Williams If unsure say 'm'. 668fdcb170SDan Williams 678fdcb170SDan Williamsconfig CXL_PMEM 688fdcb170SDan Williams tristate "CXL PMEM: Persistent Memory Support" 698fdcb170SDan Williams depends on LIBNVDIMM 708fdcb170SDan Williams default CXL_BUS 718fdcb170SDan Williams help 728fdcb170SDan Williams In addition to typical memory resources a platform may also advertise 738fdcb170SDan Williams support for persistent memory attached via CXL. This support is 748fdcb170SDan Williams managed via a bridge driver from CXL to the LIBNVDIMM system 758fdcb170SDan Williams subsystem. Say 'y/m' to enable support for enumerating and 768fdcb170SDan Williams provisioning the persistent memory capacity of CXL memory expanders. 778fdcb170SDan Williams 788fdcb170SDan Williams If unsure say 'm'. 794cdadfd5SDan Williamsendif 80