xref: /linux/drivers/cxl/Kconfig (revision 4cdadfd5e0a70017fec735b7b6d7f2f731842dc6)
1*4cdadfd5SDan Williams# SPDX-License-Identifier: GPL-2.0-only
2*4cdadfd5SDan Williamsmenuconfig CXL_BUS
3*4cdadfd5SDan Williams	tristate "CXL (Compute Express Link) Devices Support"
4*4cdadfd5SDan Williams	depends on PCI
5*4cdadfd5SDan Williams	help
6*4cdadfd5SDan Williams	  CXL is a bus that is electrically compatible with PCI Express, but
7*4cdadfd5SDan Williams	  layers three protocols on that signalling (CXL.io, CXL.cache, and
8*4cdadfd5SDan Williams	  CXL.mem). The CXL.cache protocol allows devices to hold cachelines
9*4cdadfd5SDan Williams	  locally, the CXL.mem protocol allows devices to be fully coherent
10*4cdadfd5SDan Williams	  memory targets, the CXL.io protocol is equivalent to PCI Express.
11*4cdadfd5SDan Williams	  Say 'y' to enable support for the configuration and management of
12*4cdadfd5SDan Williams	  devices supporting these protocols.
13*4cdadfd5SDan Williams
14*4cdadfd5SDan Williamsif CXL_BUS
15*4cdadfd5SDan Williams
16*4cdadfd5SDan Williamsconfig CXL_MEM
17*4cdadfd5SDan Williams	tristate "CXL.mem: Memory Devices"
18*4cdadfd5SDan Williams	help
19*4cdadfd5SDan Williams	  The CXL.mem protocol allows a device to act as a provider of
20*4cdadfd5SDan Williams	  "System RAM" and/or "Persistent Memory" that is fully coherent
21*4cdadfd5SDan Williams	  as if the memory was attached to the typical CPU memory
22*4cdadfd5SDan Williams	  controller.
23*4cdadfd5SDan Williams
24*4cdadfd5SDan Williams	  Say 'y/m' to enable a driver (named "cxl_mem.ko" when built as
25*4cdadfd5SDan Williams	  a module) that will attach to CXL.mem devices for
26*4cdadfd5SDan Williams	  configuration, provisioning, and health monitoring. This
27*4cdadfd5SDan Williams	  driver is required for dynamic provisioning of CXL.mem
28*4cdadfd5SDan Williams	  attached memory which is a prerequisite for persistent memory
29*4cdadfd5SDan Williams	  support. Typically volatile memory is mapped by platform
30*4cdadfd5SDan Williams	  firmware and included in the platform memory map, but in some
31*4cdadfd5SDan Williams	  cases the OS is responsible for mapping that memory. See
32*4cdadfd5SDan Williams	  Chapter 2.3 Type 3 CXL Device in the CXL 2.0 specification.
33*4cdadfd5SDan Williams
34*4cdadfd5SDan Williams	  If unsure say 'm'.
35*4cdadfd5SDan Williamsendif
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