14cdadfd5SDan Williams# SPDX-License-Identifier: GPL-2.0-only 24cdadfd5SDan Williamsmenuconfig CXL_BUS 34cdadfd5SDan Williams tristate "CXL (Compute Express Link) Devices Support" 44cdadfd5SDan Williams depends on PCI 54cdadfd5SDan Williams help 64cdadfd5SDan Williams CXL is a bus that is electrically compatible with PCI Express, but 74cdadfd5SDan Williams layers three protocols on that signalling (CXL.io, CXL.cache, and 84cdadfd5SDan Williams CXL.mem). The CXL.cache protocol allows devices to hold cachelines 94cdadfd5SDan Williams locally, the CXL.mem protocol allows devices to be fully coherent 104cdadfd5SDan Williams memory targets, the CXL.io protocol is equivalent to PCI Express. 114cdadfd5SDan Williams Say 'y' to enable support for the configuration and management of 124cdadfd5SDan Williams devices supporting these protocols. 134cdadfd5SDan Williams 144cdadfd5SDan Williamsif CXL_BUS 154cdadfd5SDan Williams 164cdadfd5SDan Williamsconfig CXL_MEM 174cdadfd5SDan Williams tristate "CXL.mem: Memory Devices" 184cdadfd5SDan Williams help 194cdadfd5SDan Williams The CXL.mem protocol allows a device to act as a provider of 204cdadfd5SDan Williams "System RAM" and/or "Persistent Memory" that is fully coherent 214cdadfd5SDan Williams as if the memory was attached to the typical CPU memory 224cdadfd5SDan Williams controller. 234cdadfd5SDan Williams 2421e9f767SBen Widawsky Say 'y/m' to enable a driver that will attach to CXL.mem devices for 2521e9f767SBen Widawsky configuration and management primarily via the mailbox interface. See 2621e9f767SBen Widawsky Chapter 2.3 Type 3 CXL Device in the CXL 2.0 specification for more 2721e9f767SBen Widawsky details. 284cdadfd5SDan Williams 294cdadfd5SDan Williams If unsure say 'm'. 3013237183SBen Widawsky 3113237183SBen Widawskyconfig CXL_MEM_RAW_COMMANDS 3213237183SBen Widawsky bool "RAW Command Interface for Memory Devices" 3313237183SBen Widawsky depends on CXL_MEM 3413237183SBen Widawsky help 3513237183SBen Widawsky Enable CXL RAW command interface. 3613237183SBen Widawsky 3713237183SBen Widawsky The CXL driver ioctl interface may assign a kernel ioctl command 3813237183SBen Widawsky number for each specification defined opcode. At any given point in 3913237183SBen Widawsky time the number of opcodes that the specification defines and a device 4013237183SBen Widawsky may implement may exceed the kernel's set of associated ioctl function 4113237183SBen Widawsky numbers. The mismatch is either by omission, specification is too new, 4213237183SBen Widawsky or by design. When prototyping new hardware, or developing / debugging 4313237183SBen Widawsky the driver it is useful to be able to submit any possible command to 4413237183SBen Widawsky the hardware, even commands that may crash the kernel due to their 4513237183SBen Widawsky potential impact to memory currently in use by the kernel. 4613237183SBen Widawsky 4713237183SBen Widawsky If developing CXL hardware or the driver say Y, otherwise say N. 48*4812be97SDan Williams 49*4812be97SDan Williamsconfig CXL_ACPI 50*4812be97SDan Williams tristate "CXL ACPI: Platform Support" 51*4812be97SDan Williams depends on ACPI 52*4812be97SDan Williams help 53*4812be97SDan Williams Enable support for host managed device memory (HDM) resources 54*4812be97SDan Williams published by a platform's ACPI CXL memory layout description. See 55*4812be97SDan Williams Chapter 9.14.1 CXL Early Discovery Table (CEDT) in the CXL 2.0 56*4812be97SDan Williams specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS) 57*4812be97SDan Williams (https://www.computeexpresslink.org/spec-landing). The CXL core 58*4812be97SDan Williams consumes these resource to publish the root of a cxl_port decode 59*4812be97SDan Williams hierarchy to map regions that represent System RAM, or Persistent 60*4812be97SDan Williams Memory regions to be managed by LIBNVDIMM. 61*4812be97SDan Williams 62*4812be97SDan Williams If unsure say 'm'. 634cdadfd5SDan Williamsendif 64