14cdadfd5SDan Williams# SPDX-License-Identifier: GPL-2.0-only 24cdadfd5SDan Williamsmenuconfig CXL_BUS 34cdadfd5SDan Williams tristate "CXL (Compute Express Link) Devices Support" 44cdadfd5SDan Williams depends on PCI 54cdadfd5SDan Williams help 64cdadfd5SDan Williams CXL is a bus that is electrically compatible with PCI Express, but 74cdadfd5SDan Williams layers three protocols on that signalling (CXL.io, CXL.cache, and 84cdadfd5SDan Williams CXL.mem). The CXL.cache protocol allows devices to hold cachelines 94cdadfd5SDan Williams locally, the CXL.mem protocol allows devices to be fully coherent 104cdadfd5SDan Williams memory targets, the CXL.io protocol is equivalent to PCI Express. 114cdadfd5SDan Williams Say 'y' to enable support for the configuration and management of 124cdadfd5SDan Williams devices supporting these protocols. 134cdadfd5SDan Williams 144cdadfd5SDan Williamsif CXL_BUS 154cdadfd5SDan Williams 164cdadfd5SDan Williamsconfig CXL_MEM 174cdadfd5SDan Williams tristate "CXL.mem: Memory Devices" 184cdadfd5SDan Williams help 194cdadfd5SDan Williams The CXL.mem protocol allows a device to act as a provider of 204cdadfd5SDan Williams "System RAM" and/or "Persistent Memory" that is fully coherent 214cdadfd5SDan Williams as if the memory was attached to the typical CPU memory 224cdadfd5SDan Williams controller. 234cdadfd5SDan Williams 244cdadfd5SDan Williams Say 'y/m' to enable a driver (named "cxl_mem.ko" when built as 254cdadfd5SDan Williams a module) that will attach to CXL.mem devices for 264cdadfd5SDan Williams configuration, provisioning, and health monitoring. This 274cdadfd5SDan Williams driver is required for dynamic provisioning of CXL.mem 284cdadfd5SDan Williams attached memory which is a prerequisite for persistent memory 294cdadfd5SDan Williams support. Typically volatile memory is mapped by platform 304cdadfd5SDan Williams firmware and included in the platform memory map, but in some 314cdadfd5SDan Williams cases the OS is responsible for mapping that memory. See 324cdadfd5SDan Williams Chapter 2.3 Type 3 CXL Device in the CXL 2.0 specification. 334cdadfd5SDan Williams 344cdadfd5SDan Williams If unsure say 'm'. 35*13237183SBen Widawsky 36*13237183SBen Widawskyconfig CXL_MEM_RAW_COMMANDS 37*13237183SBen Widawsky bool "RAW Command Interface for Memory Devices" 38*13237183SBen Widawsky depends on CXL_MEM 39*13237183SBen Widawsky help 40*13237183SBen Widawsky Enable CXL RAW command interface. 41*13237183SBen Widawsky 42*13237183SBen Widawsky The CXL driver ioctl interface may assign a kernel ioctl command 43*13237183SBen Widawsky number for each specification defined opcode. At any given point in 44*13237183SBen Widawsky time the number of opcodes that the specification defines and a device 45*13237183SBen Widawsky may implement may exceed the kernel's set of associated ioctl function 46*13237183SBen Widawsky numbers. The mismatch is either by omission, specification is too new, 47*13237183SBen Widawsky or by design. When prototyping new hardware, or developing / debugging 48*13237183SBen Widawsky the driver it is useful to be able to submit any possible command to 49*13237183SBen Widawsky the hardware, even commands that may crash the kernel due to their 50*13237183SBen Widawsky potential impact to memory currently in use by the kernel. 51*13237183SBen Widawsky 52*13237183SBen Widawsky If developing CXL hardware or the driver say Y, otherwise say N. 534cdadfd5SDan Williamsendif 54