1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Xilinx ZynqMP AES Driver. 4 * Copyright (c) 2020 Xilinx Inc. 5 */ 6 7 #include <crypto/aes.h> 8 #include <crypto/engine.h> 9 #include <crypto/gcm.h> 10 #include <crypto/internal/aead.h> 11 #include <crypto/scatterwalk.h> 12 13 #include <linux/module.h> 14 #include <linux/of_device.h> 15 #include <linux/platform_device.h> 16 17 #include <linux/firmware/xlnx-zynqmp.h> 18 19 #define ZYNQMP_DMA_BIT_MASK 32U 20 21 #define ZYNQMP_AES_KEY_SIZE AES_KEYSIZE_256 22 #define ZYNQMP_AES_AUTH_SIZE 16U 23 #define ZYNQMP_KEY_SRC_SEL_KEY_LEN 1U 24 #define ZYNQMP_AES_BLK_SIZE 1U 25 #define ZYNQMP_AES_MIN_INPUT_BLK_SIZE 4U 26 #define ZYNQMP_AES_WORD_LEN 4U 27 28 #define ZYNQMP_AES_GCM_TAG_MISMATCH_ERR 0x01 29 #define ZYNQMP_AES_WRONG_KEY_SRC_ERR 0x13 30 #define ZYNQMP_AES_PUF_NOT_PROGRAMMED 0xE300 31 32 enum zynqmp_aead_op { 33 ZYNQMP_AES_DECRYPT = 0, 34 ZYNQMP_AES_ENCRYPT 35 }; 36 37 enum zynqmp_aead_keysrc { 38 ZYNQMP_AES_KUP_KEY = 0, 39 ZYNQMP_AES_DEV_KEY, 40 ZYNQMP_AES_PUF_KEY 41 }; 42 43 struct zynqmp_aead_drv_ctx { 44 union { 45 struct aead_alg aead; 46 } alg; 47 struct device *dev; 48 struct crypto_engine *engine; 49 const struct zynqmp_eemi_ops *eemi_ops; 50 }; 51 52 struct zynqmp_aead_hw_req { 53 u64 src; 54 u64 iv; 55 u64 key; 56 u64 dst; 57 u64 size; 58 u64 op; 59 u64 keysrc; 60 }; 61 62 struct zynqmp_aead_tfm_ctx { 63 struct crypto_engine_ctx engine_ctx; 64 struct device *dev; 65 u8 key[ZYNQMP_AES_KEY_SIZE]; 66 u8 *iv; 67 u32 keylen; 68 u32 authsize; 69 enum zynqmp_aead_keysrc keysrc; 70 struct crypto_aead *fbk_cipher; 71 }; 72 73 struct zynqmp_aead_req_ctx { 74 enum zynqmp_aead_op op; 75 }; 76 77 static int zynqmp_aes_aead_cipher(struct aead_request *req) 78 { 79 struct crypto_aead *aead = crypto_aead_reqtfm(req); 80 struct zynqmp_aead_tfm_ctx *tfm_ctx = crypto_aead_ctx(aead); 81 struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(req); 82 struct device *dev = tfm_ctx->dev; 83 struct aead_alg *alg = crypto_aead_alg(aead); 84 struct zynqmp_aead_drv_ctx *drv_ctx; 85 struct zynqmp_aead_hw_req *hwreq; 86 dma_addr_t dma_addr_data, dma_addr_hw_req; 87 unsigned int data_size; 88 unsigned int status; 89 size_t dma_size; 90 char *kbuf; 91 int err; 92 93 drv_ctx = container_of(alg, struct zynqmp_aead_drv_ctx, alg.aead); 94 95 if (!drv_ctx->eemi_ops->aes) 96 return -ENOTSUPP; 97 98 if (tfm_ctx->keysrc == ZYNQMP_AES_KUP_KEY) 99 dma_size = req->cryptlen + ZYNQMP_AES_KEY_SIZE 100 + GCM_AES_IV_SIZE; 101 else 102 dma_size = req->cryptlen + GCM_AES_IV_SIZE; 103 104 kbuf = dma_alloc_coherent(dev, dma_size, &dma_addr_data, GFP_KERNEL); 105 if (!kbuf) 106 return -ENOMEM; 107 108 hwreq = dma_alloc_coherent(dev, sizeof(struct zynqmp_aead_hw_req), 109 &dma_addr_hw_req, GFP_KERNEL); 110 if (!hwreq) { 111 dma_free_coherent(dev, dma_size, kbuf, dma_addr_data); 112 return -ENOMEM; 113 } 114 115 data_size = req->cryptlen; 116 scatterwalk_map_and_copy(kbuf, req->src, 0, req->cryptlen, 0); 117 memcpy(kbuf + data_size, req->iv, GCM_AES_IV_SIZE); 118 119 hwreq->src = dma_addr_data; 120 hwreq->dst = dma_addr_data; 121 hwreq->iv = hwreq->src + data_size; 122 hwreq->keysrc = tfm_ctx->keysrc; 123 hwreq->op = rq_ctx->op; 124 125 if (hwreq->op == ZYNQMP_AES_ENCRYPT) 126 hwreq->size = data_size; 127 else 128 hwreq->size = data_size - ZYNQMP_AES_AUTH_SIZE; 129 130 if (hwreq->keysrc == ZYNQMP_AES_KUP_KEY) { 131 memcpy(kbuf + data_size + GCM_AES_IV_SIZE, 132 tfm_ctx->key, ZYNQMP_AES_KEY_SIZE); 133 134 hwreq->key = hwreq->src + data_size + GCM_AES_IV_SIZE; 135 } else { 136 hwreq->key = 0; 137 } 138 139 drv_ctx->eemi_ops->aes(dma_addr_hw_req, &status); 140 141 if (status) { 142 switch (status) { 143 case ZYNQMP_AES_GCM_TAG_MISMATCH_ERR: 144 dev_err(dev, "ERROR: Gcm Tag mismatch\n"); 145 break; 146 case ZYNQMP_AES_WRONG_KEY_SRC_ERR: 147 dev_err(dev, "ERROR: Wrong KeySrc, enable secure mode\n"); 148 break; 149 case ZYNQMP_AES_PUF_NOT_PROGRAMMED: 150 dev_err(dev, "ERROR: PUF is not registered\n"); 151 break; 152 default: 153 dev_err(dev, "ERROR: Unknown error\n"); 154 break; 155 } 156 err = -status; 157 } else { 158 if (hwreq->op == ZYNQMP_AES_ENCRYPT) 159 data_size = data_size + ZYNQMP_AES_AUTH_SIZE; 160 else 161 data_size = data_size - ZYNQMP_AES_AUTH_SIZE; 162 163 sg_copy_from_buffer(req->dst, sg_nents(req->dst), 164 kbuf, data_size); 165 err = 0; 166 } 167 168 if (kbuf) { 169 memzero_explicit(kbuf, dma_size); 170 dma_free_coherent(dev, dma_size, kbuf, dma_addr_data); 171 } 172 if (hwreq) { 173 memzero_explicit(hwreq, sizeof(struct zynqmp_aead_hw_req)); 174 dma_free_coherent(dev, sizeof(struct zynqmp_aead_hw_req), 175 hwreq, dma_addr_hw_req); 176 } 177 return err; 178 } 179 180 static int zynqmp_fallback_check(struct zynqmp_aead_tfm_ctx *tfm_ctx, 181 struct aead_request *req) 182 { 183 int need_fallback = 0; 184 struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(req); 185 186 if (tfm_ctx->authsize != ZYNQMP_AES_AUTH_SIZE) 187 need_fallback = 1; 188 189 if (tfm_ctx->keysrc == ZYNQMP_AES_KUP_KEY && 190 tfm_ctx->keylen != ZYNQMP_AES_KEY_SIZE) { 191 need_fallback = 1; 192 } 193 if (req->assoclen != 0 || 194 req->cryptlen < ZYNQMP_AES_MIN_INPUT_BLK_SIZE) { 195 need_fallback = 1; 196 } 197 if ((req->cryptlen % ZYNQMP_AES_WORD_LEN) != 0) 198 need_fallback = 1; 199 200 if (rq_ctx->op == ZYNQMP_AES_DECRYPT && 201 req->cryptlen <= ZYNQMP_AES_AUTH_SIZE) { 202 need_fallback = 1; 203 } 204 return need_fallback; 205 } 206 207 static int zynqmp_handle_aes_req(struct crypto_engine *engine, 208 void *req) 209 { 210 struct aead_request *areq = 211 container_of(req, struct aead_request, base); 212 struct crypto_aead *aead = crypto_aead_reqtfm(req); 213 struct zynqmp_aead_tfm_ctx *tfm_ctx = crypto_aead_ctx(aead); 214 struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(areq); 215 struct aead_request *subreq = aead_request_ctx(req); 216 int need_fallback; 217 int err; 218 219 need_fallback = zynqmp_fallback_check(tfm_ctx, areq); 220 221 if (need_fallback) { 222 aead_request_set_tfm(subreq, tfm_ctx->fbk_cipher); 223 224 aead_request_set_callback(subreq, areq->base.flags, 225 NULL, NULL); 226 aead_request_set_crypt(subreq, areq->src, areq->dst, 227 areq->cryptlen, areq->iv); 228 aead_request_set_ad(subreq, areq->assoclen); 229 if (rq_ctx->op == ZYNQMP_AES_ENCRYPT) 230 err = crypto_aead_encrypt(subreq); 231 else 232 err = crypto_aead_decrypt(subreq); 233 } else { 234 err = zynqmp_aes_aead_cipher(areq); 235 } 236 237 crypto_finalize_aead_request(engine, areq, err); 238 return 0; 239 } 240 241 static int zynqmp_aes_aead_setkey(struct crypto_aead *aead, const u8 *key, 242 unsigned int keylen) 243 { 244 struct crypto_tfm *tfm = crypto_aead_tfm(aead); 245 struct zynqmp_aead_tfm_ctx *tfm_ctx = 246 (struct zynqmp_aead_tfm_ctx *)crypto_tfm_ctx(tfm); 247 unsigned char keysrc; 248 249 if (keylen == ZYNQMP_KEY_SRC_SEL_KEY_LEN) { 250 keysrc = *key; 251 if (keysrc == ZYNQMP_AES_KUP_KEY || 252 keysrc == ZYNQMP_AES_DEV_KEY || 253 keysrc == ZYNQMP_AES_PUF_KEY) { 254 tfm_ctx->keysrc = (enum zynqmp_aead_keysrc)keysrc; 255 } else { 256 tfm_ctx->keylen = keylen; 257 } 258 } else { 259 tfm_ctx->keylen = keylen; 260 if (keylen == ZYNQMP_AES_KEY_SIZE) { 261 tfm_ctx->keysrc = ZYNQMP_AES_KUP_KEY; 262 memcpy(tfm_ctx->key, key, keylen); 263 } 264 } 265 266 tfm_ctx->fbk_cipher->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK; 267 tfm_ctx->fbk_cipher->base.crt_flags |= (aead->base.crt_flags & 268 CRYPTO_TFM_REQ_MASK); 269 270 return crypto_aead_setkey(tfm_ctx->fbk_cipher, key, keylen); 271 } 272 273 static int zynqmp_aes_aead_setauthsize(struct crypto_aead *aead, 274 unsigned int authsize) 275 { 276 struct crypto_tfm *tfm = crypto_aead_tfm(aead); 277 struct zynqmp_aead_tfm_ctx *tfm_ctx = 278 (struct zynqmp_aead_tfm_ctx *)crypto_tfm_ctx(tfm); 279 280 tfm_ctx->authsize = authsize; 281 return crypto_aead_setauthsize(tfm_ctx->fbk_cipher, authsize); 282 } 283 284 static int zynqmp_aes_aead_encrypt(struct aead_request *req) 285 { 286 struct zynqmp_aead_drv_ctx *drv_ctx; 287 struct crypto_aead *aead = crypto_aead_reqtfm(req); 288 struct aead_alg *alg = crypto_aead_alg(aead); 289 struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(req); 290 291 rq_ctx->op = ZYNQMP_AES_ENCRYPT; 292 drv_ctx = container_of(alg, struct zynqmp_aead_drv_ctx, alg.aead); 293 294 return crypto_transfer_aead_request_to_engine(drv_ctx->engine, req); 295 } 296 297 static int zynqmp_aes_aead_decrypt(struct aead_request *req) 298 { 299 struct zynqmp_aead_drv_ctx *drv_ctx; 300 struct crypto_aead *aead = crypto_aead_reqtfm(req); 301 struct aead_alg *alg = crypto_aead_alg(aead); 302 struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(req); 303 304 rq_ctx->op = ZYNQMP_AES_DECRYPT; 305 drv_ctx = container_of(alg, struct zynqmp_aead_drv_ctx, alg.aead); 306 307 return crypto_transfer_aead_request_to_engine(drv_ctx->engine, req); 308 } 309 310 static int zynqmp_aes_aead_init(struct crypto_aead *aead) 311 { 312 struct crypto_tfm *tfm = crypto_aead_tfm(aead); 313 struct zynqmp_aead_tfm_ctx *tfm_ctx = 314 (struct zynqmp_aead_tfm_ctx *)crypto_tfm_ctx(tfm); 315 struct zynqmp_aead_drv_ctx *drv_ctx; 316 struct aead_alg *alg = crypto_aead_alg(aead); 317 318 drv_ctx = container_of(alg, struct zynqmp_aead_drv_ctx, alg.aead); 319 tfm_ctx->dev = drv_ctx->dev; 320 321 tfm_ctx->engine_ctx.op.do_one_request = zynqmp_handle_aes_req; 322 tfm_ctx->engine_ctx.op.prepare_request = NULL; 323 tfm_ctx->engine_ctx.op.unprepare_request = NULL; 324 325 tfm_ctx->fbk_cipher = crypto_alloc_aead(drv_ctx->alg.aead.base.cra_name, 326 0, 327 CRYPTO_ALG_NEED_FALLBACK); 328 329 if (IS_ERR(tfm_ctx->fbk_cipher)) { 330 pr_err("%s() Error: failed to allocate fallback for %s\n", 331 __func__, drv_ctx->alg.aead.base.cra_name); 332 return PTR_ERR(tfm_ctx->fbk_cipher); 333 } 334 335 crypto_aead_set_reqsize(aead, 336 max(sizeof(struct zynqmp_aead_req_ctx), 337 sizeof(struct aead_request) + 338 crypto_aead_reqsize(tfm_ctx->fbk_cipher))); 339 return 0; 340 } 341 342 static void zynqmp_aes_aead_exit(struct crypto_aead *aead) 343 { 344 struct crypto_tfm *tfm = crypto_aead_tfm(aead); 345 struct zynqmp_aead_tfm_ctx *tfm_ctx = 346 (struct zynqmp_aead_tfm_ctx *)crypto_tfm_ctx(tfm); 347 348 if (tfm_ctx->fbk_cipher) { 349 crypto_free_aead(tfm_ctx->fbk_cipher); 350 tfm_ctx->fbk_cipher = NULL; 351 } 352 memzero_explicit(tfm_ctx, sizeof(struct zynqmp_aead_tfm_ctx)); 353 } 354 355 static struct zynqmp_aead_drv_ctx aes_drv_ctx = { 356 .alg.aead = { 357 .setkey = zynqmp_aes_aead_setkey, 358 .setauthsize = zynqmp_aes_aead_setauthsize, 359 .encrypt = zynqmp_aes_aead_encrypt, 360 .decrypt = zynqmp_aes_aead_decrypt, 361 .init = zynqmp_aes_aead_init, 362 .exit = zynqmp_aes_aead_exit, 363 .ivsize = GCM_AES_IV_SIZE, 364 .maxauthsize = ZYNQMP_AES_AUTH_SIZE, 365 .base = { 366 .cra_name = "gcm(aes)", 367 .cra_driver_name = "xilinx-zynqmp-aes-gcm", 368 .cra_priority = 200, 369 .cra_flags = CRYPTO_ALG_TYPE_AEAD | 370 CRYPTO_ALG_ASYNC | 371 CRYPTO_ALG_KERN_DRIVER_ONLY | 372 CRYPTO_ALG_NEED_FALLBACK, 373 .cra_blocksize = ZYNQMP_AES_BLK_SIZE, 374 .cra_ctxsize = sizeof(struct zynqmp_aead_tfm_ctx), 375 .cra_module = THIS_MODULE, 376 } 377 } 378 }; 379 380 static int zynqmp_aes_aead_probe(struct platform_device *pdev) 381 { 382 struct device *dev = &pdev->dev; 383 int err; 384 385 /* ZynqMP AES driver supports only one instance */ 386 if (!aes_drv_ctx.dev) 387 aes_drv_ctx.dev = dev; 388 else 389 return -ENODEV; 390 391 aes_drv_ctx.eemi_ops = zynqmp_pm_get_eemi_ops(); 392 if (IS_ERR(aes_drv_ctx.eemi_ops)) { 393 dev_err(dev, "Failed to get ZynqMP EEMI interface\n"); 394 return PTR_ERR(aes_drv_ctx.eemi_ops); 395 } 396 397 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(ZYNQMP_DMA_BIT_MASK)); 398 if (err < 0) { 399 dev_err(dev, "No usable DMA configuration\n"); 400 return err; 401 } 402 403 aes_drv_ctx.engine = crypto_engine_alloc_init(dev, 1); 404 if (!aes_drv_ctx.engine) { 405 dev_err(dev, "Cannot alloc AES engine\n"); 406 err = -ENOMEM; 407 goto err_engine; 408 } 409 410 err = crypto_engine_start(aes_drv_ctx.engine); 411 if (err) { 412 dev_err(dev, "Cannot start AES engine\n"); 413 goto err_engine; 414 } 415 416 err = crypto_register_aead(&aes_drv_ctx.alg.aead); 417 if (err < 0) { 418 dev_err(dev, "Failed to register AEAD alg.\n"); 419 goto err_aead; 420 } 421 return 0; 422 423 err_aead: 424 crypto_unregister_aead(&aes_drv_ctx.alg.aead); 425 426 err_engine: 427 if (aes_drv_ctx.engine) 428 crypto_engine_exit(aes_drv_ctx.engine); 429 430 return err; 431 } 432 433 static int zynqmp_aes_aead_remove(struct platform_device *pdev) 434 { 435 crypto_engine_exit(aes_drv_ctx.engine); 436 crypto_unregister_aead(&aes_drv_ctx.alg.aead); 437 438 return 0; 439 } 440 441 static const struct of_device_id zynqmp_aes_dt_ids[] = { 442 { .compatible = "xlnx,zynqmp-aes" }, 443 { /* sentinel */ } 444 }; 445 MODULE_DEVICE_TABLE(of, zynqmp_aes_dt_ids); 446 447 static struct platform_driver zynqmp_aes_driver = { 448 .probe = zynqmp_aes_aead_probe, 449 .remove = zynqmp_aes_aead_remove, 450 .driver = { 451 .name = "zynqmp-aes", 452 .of_match_table = zynqmp_aes_dt_ids, 453 }, 454 }; 455 456 module_platform_driver(zynqmp_aes_driver); 457 MODULE_LICENSE("GPL"); 458