1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) STMicroelectronics SA 2017 4 * Author: Fabien Dessenne <fabien.dessenne@st.com> 5 */ 6 7 #include <linux/bitrev.h> 8 #include <linux/clk.h> 9 #include <linux/crc32poly.h> 10 #include <linux/module.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_runtime.h> 14 15 #include <crypto/internal/hash.h> 16 17 #include <asm/unaligned.h> 18 19 #define DRIVER_NAME "stm32-crc32" 20 #define CHKSUM_DIGEST_SIZE 4 21 #define CHKSUM_BLOCK_SIZE 1 22 23 /* Registers */ 24 #define CRC_DR 0x00000000 25 #define CRC_CR 0x00000008 26 #define CRC_INIT 0x00000010 27 #define CRC_POL 0x00000014 28 29 /* Registers values */ 30 #define CRC_CR_RESET BIT(0) 31 #define CRC_CR_REVERSE (BIT(7) | BIT(6) | BIT(5)) 32 #define CRC_INIT_DEFAULT 0xFFFFFFFF 33 34 #define CRC_AUTOSUSPEND_DELAY 50 35 36 struct stm32_crc { 37 struct list_head list; 38 struct device *dev; 39 void __iomem *regs; 40 struct clk *clk; 41 u8 pending_data[sizeof(u32)]; 42 size_t nb_pending_bytes; 43 }; 44 45 struct stm32_crc_list { 46 struct list_head dev_list; 47 spinlock_t lock; /* protect dev_list */ 48 }; 49 50 static struct stm32_crc_list crc_list = { 51 .dev_list = LIST_HEAD_INIT(crc_list.dev_list), 52 .lock = __SPIN_LOCK_UNLOCKED(crc_list.lock), 53 }; 54 55 struct stm32_crc_ctx { 56 u32 key; 57 u32 poly; 58 }; 59 60 struct stm32_crc_desc_ctx { 61 u32 partial; /* crc32c: partial in first 4 bytes of that struct */ 62 struct stm32_crc *crc; 63 }; 64 65 static int stm32_crc32_cra_init(struct crypto_tfm *tfm) 66 { 67 struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm); 68 69 mctx->key = CRC_INIT_DEFAULT; 70 mctx->poly = CRC32_POLY_LE; 71 return 0; 72 } 73 74 static int stm32_crc32c_cra_init(struct crypto_tfm *tfm) 75 { 76 struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm); 77 78 mctx->key = CRC_INIT_DEFAULT; 79 mctx->poly = CRC32C_POLY_LE; 80 return 0; 81 } 82 83 static int stm32_crc_setkey(struct crypto_shash *tfm, const u8 *key, 84 unsigned int keylen) 85 { 86 struct stm32_crc_ctx *mctx = crypto_shash_ctx(tfm); 87 88 if (keylen != sizeof(u32)) 89 return -EINVAL; 90 91 mctx->key = get_unaligned_le32(key); 92 return 0; 93 } 94 95 static int stm32_crc_init(struct shash_desc *desc) 96 { 97 struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc); 98 struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm); 99 struct stm32_crc *crc; 100 101 spin_lock_bh(&crc_list.lock); 102 list_for_each_entry(crc, &crc_list.dev_list, list) { 103 ctx->crc = crc; 104 break; 105 } 106 spin_unlock_bh(&crc_list.lock); 107 108 pm_runtime_get_sync(ctx->crc->dev); 109 110 /* Reset, set key, poly and configure in bit reverse mode */ 111 writel_relaxed(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT); 112 writel_relaxed(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL); 113 writel_relaxed(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR); 114 115 /* Store partial result */ 116 ctx->partial = readl_relaxed(ctx->crc->regs + CRC_DR); 117 ctx->crc->nb_pending_bytes = 0; 118 119 pm_runtime_mark_last_busy(ctx->crc->dev); 120 pm_runtime_put_autosuspend(ctx->crc->dev); 121 122 return 0; 123 } 124 125 static int stm32_crc_update(struct shash_desc *desc, const u8 *d8, 126 unsigned int length) 127 { 128 struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc); 129 struct stm32_crc *crc = ctx->crc; 130 u32 *d32; 131 unsigned int i; 132 133 pm_runtime_get_sync(crc->dev); 134 135 if (unlikely(crc->nb_pending_bytes)) { 136 while (crc->nb_pending_bytes != sizeof(u32) && length) { 137 /* Fill in pending data */ 138 crc->pending_data[crc->nb_pending_bytes++] = *(d8++); 139 length--; 140 } 141 142 if (crc->nb_pending_bytes == sizeof(u32)) { 143 /* Process completed pending data */ 144 writel_relaxed(*(u32 *)crc->pending_data, 145 crc->regs + CRC_DR); 146 crc->nb_pending_bytes = 0; 147 } 148 } 149 150 d32 = (u32 *)d8; 151 for (i = 0; i < length >> 2; i++) 152 /* Process 32 bits data */ 153 writel_relaxed(*(d32++), crc->regs + CRC_DR); 154 155 /* Store partial result */ 156 ctx->partial = readl_relaxed(crc->regs + CRC_DR); 157 158 pm_runtime_mark_last_busy(crc->dev); 159 pm_runtime_put_autosuspend(crc->dev); 160 161 /* Check for pending data (non 32 bits) */ 162 length &= 3; 163 if (likely(!length)) 164 return 0; 165 166 if ((crc->nb_pending_bytes + length) >= sizeof(u32)) { 167 /* Shall not happen */ 168 dev_err(crc->dev, "Pending data overflow\n"); 169 return -EINVAL; 170 } 171 172 d8 = (const u8 *)d32; 173 for (i = 0; i < length; i++) 174 /* Store pending data */ 175 crc->pending_data[crc->nb_pending_bytes++] = *(d8++); 176 177 return 0; 178 } 179 180 static int stm32_crc_final(struct shash_desc *desc, u8 *out) 181 { 182 struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc); 183 struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm); 184 185 /* Send computed CRC */ 186 put_unaligned_le32(mctx->poly == CRC32C_POLY_LE ? 187 ~ctx->partial : ctx->partial, out); 188 189 return 0; 190 } 191 192 static int stm32_crc_finup(struct shash_desc *desc, const u8 *data, 193 unsigned int length, u8 *out) 194 { 195 return stm32_crc_update(desc, data, length) ?: 196 stm32_crc_final(desc, out); 197 } 198 199 static int stm32_crc_digest(struct shash_desc *desc, const u8 *data, 200 unsigned int length, u8 *out) 201 { 202 return stm32_crc_init(desc) ?: stm32_crc_finup(desc, data, length, out); 203 } 204 205 static struct shash_alg algs[] = { 206 /* CRC-32 */ 207 { 208 .setkey = stm32_crc_setkey, 209 .init = stm32_crc_init, 210 .update = stm32_crc_update, 211 .final = stm32_crc_final, 212 .finup = stm32_crc_finup, 213 .digest = stm32_crc_digest, 214 .descsize = sizeof(struct stm32_crc_desc_ctx), 215 .digestsize = CHKSUM_DIGEST_SIZE, 216 .base = { 217 .cra_name = "crc32", 218 .cra_driver_name = DRIVER_NAME, 219 .cra_priority = 200, 220 .cra_flags = CRYPTO_ALG_OPTIONAL_KEY, 221 .cra_blocksize = CHKSUM_BLOCK_SIZE, 222 .cra_alignmask = 3, 223 .cra_ctxsize = sizeof(struct stm32_crc_ctx), 224 .cra_module = THIS_MODULE, 225 .cra_init = stm32_crc32_cra_init, 226 } 227 }, 228 /* CRC-32Castagnoli */ 229 { 230 .setkey = stm32_crc_setkey, 231 .init = stm32_crc_init, 232 .update = stm32_crc_update, 233 .final = stm32_crc_final, 234 .finup = stm32_crc_finup, 235 .digest = stm32_crc_digest, 236 .descsize = sizeof(struct stm32_crc_desc_ctx), 237 .digestsize = CHKSUM_DIGEST_SIZE, 238 .base = { 239 .cra_name = "crc32c", 240 .cra_driver_name = DRIVER_NAME, 241 .cra_priority = 200, 242 .cra_flags = CRYPTO_ALG_OPTIONAL_KEY, 243 .cra_blocksize = CHKSUM_BLOCK_SIZE, 244 .cra_alignmask = 3, 245 .cra_ctxsize = sizeof(struct stm32_crc_ctx), 246 .cra_module = THIS_MODULE, 247 .cra_init = stm32_crc32c_cra_init, 248 } 249 } 250 }; 251 252 static int stm32_crc_probe(struct platform_device *pdev) 253 { 254 struct device *dev = &pdev->dev; 255 struct stm32_crc *crc; 256 int ret; 257 258 crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL); 259 if (!crc) 260 return -ENOMEM; 261 262 crc->dev = dev; 263 264 crc->regs = devm_platform_ioremap_resource(pdev, 0); 265 if (IS_ERR(crc->regs)) { 266 dev_err(dev, "Cannot map CRC IO\n"); 267 return PTR_ERR(crc->regs); 268 } 269 270 crc->clk = devm_clk_get(dev, NULL); 271 if (IS_ERR(crc->clk)) { 272 dev_err(dev, "Could not get clock\n"); 273 return PTR_ERR(crc->clk); 274 } 275 276 ret = clk_prepare_enable(crc->clk); 277 if (ret) { 278 dev_err(crc->dev, "Failed to enable clock\n"); 279 return ret; 280 } 281 282 pm_runtime_set_autosuspend_delay(dev, CRC_AUTOSUSPEND_DELAY); 283 pm_runtime_use_autosuspend(dev); 284 285 pm_runtime_get_noresume(dev); 286 pm_runtime_set_active(dev); 287 pm_runtime_enable(dev); 288 289 platform_set_drvdata(pdev, crc); 290 291 spin_lock(&crc_list.lock); 292 list_add(&crc->list, &crc_list.dev_list); 293 spin_unlock(&crc_list.lock); 294 295 ret = crypto_register_shashes(algs, ARRAY_SIZE(algs)); 296 if (ret) { 297 dev_err(dev, "Failed to register\n"); 298 clk_disable_unprepare(crc->clk); 299 return ret; 300 } 301 302 dev_info(dev, "Initialized\n"); 303 304 pm_runtime_put_sync(dev); 305 306 return 0; 307 } 308 309 static int stm32_crc_remove(struct platform_device *pdev) 310 { 311 struct stm32_crc *crc = platform_get_drvdata(pdev); 312 int ret = pm_runtime_get_sync(crc->dev); 313 314 if (ret < 0) 315 return ret; 316 317 spin_lock(&crc_list.lock); 318 list_del(&crc->list); 319 spin_unlock(&crc_list.lock); 320 321 crypto_unregister_shashes(algs, ARRAY_SIZE(algs)); 322 323 pm_runtime_disable(crc->dev); 324 pm_runtime_put_noidle(crc->dev); 325 326 clk_disable_unprepare(crc->clk); 327 328 return 0; 329 } 330 331 #ifdef CONFIG_PM 332 static int stm32_crc_runtime_suspend(struct device *dev) 333 { 334 struct stm32_crc *crc = dev_get_drvdata(dev); 335 336 clk_disable_unprepare(crc->clk); 337 338 return 0; 339 } 340 341 static int stm32_crc_runtime_resume(struct device *dev) 342 { 343 struct stm32_crc *crc = dev_get_drvdata(dev); 344 int ret; 345 346 ret = clk_prepare_enable(crc->clk); 347 if (ret) { 348 dev_err(crc->dev, "Failed to prepare_enable clock\n"); 349 return ret; 350 } 351 352 return 0; 353 } 354 #endif 355 356 static const struct dev_pm_ops stm32_crc_pm_ops = { 357 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 358 pm_runtime_force_resume) 359 SET_RUNTIME_PM_OPS(stm32_crc_runtime_suspend, 360 stm32_crc_runtime_resume, NULL) 361 }; 362 363 static const struct of_device_id stm32_dt_ids[] = { 364 { .compatible = "st,stm32f7-crc", }, 365 {}, 366 }; 367 MODULE_DEVICE_TABLE(of, stm32_dt_ids); 368 369 static struct platform_driver stm32_crc_driver = { 370 .probe = stm32_crc_probe, 371 .remove = stm32_crc_remove, 372 .driver = { 373 .name = DRIVER_NAME, 374 .pm = &stm32_crc_pm_ops, 375 .of_match_table = stm32_dt_ids, 376 }, 377 }; 378 379 module_platform_driver(stm32_crc_driver); 380 381 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>"); 382 MODULE_DESCRIPTION("STMicrolectronics STM32 CRC32 hardware driver"); 383 MODULE_LICENSE("GPL"); 384