1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Cryptographic API. 4 * 5 * Support for StarFive hardware cryptographic engine. 6 * Copyright (c) 2022 StarFive Technology 7 * 8 */ 9 10 #include <crypto/engine.h> 11 #include "jh7110-cryp.h" 12 #include <linux/clk.h> 13 #include <linux/completion.h> 14 #include <linux/err.h> 15 #include <linux/interrupt.h> 16 #include <linux/iopoll.h> 17 #include <linux/kernel.h> 18 #include <linux/mod_devicetable.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/reset.h> 23 #include <linux/spinlock.h> 24 25 #define DRIVER_NAME "jh7110-crypto" 26 27 struct starfive_dev_list { 28 struct list_head dev_list; 29 spinlock_t lock; /* protect dev_list */ 30 }; 31 32 static struct starfive_dev_list dev_list = { 33 .dev_list = LIST_HEAD_INIT(dev_list.dev_list), 34 .lock = __SPIN_LOCK_UNLOCKED(dev_list.lock), 35 }; 36 37 struct starfive_cryp_dev *starfive_cryp_find_dev(struct starfive_cryp_ctx *ctx) 38 { 39 struct starfive_cryp_dev *cryp; 40 41 spin_lock_bh(&dev_list.lock); 42 if (!ctx->cryp) 43 ctx->cryp = list_first_entry_or_null(&dev_list.dev_list, 44 struct starfive_cryp_dev, 45 list); 46 cryp = ctx->cryp; 47 spin_unlock_bh(&dev_list.lock); 48 49 return cryp; 50 } 51 52 static u16 side_chan; 53 module_param(side_chan, ushort, 0); 54 MODULE_PARM_DESC(side_chan, "Enable side channel mitigation for AES module.\n" 55 "Enabling this feature will reduce speed performance.\n" 56 " 0 - Disabled\n" 57 " other - Enabled"); 58 59 static int starfive_dma_init(struct starfive_cryp_dev *cryp) 60 { 61 dma_cap_mask_t mask; 62 63 dma_cap_zero(mask); 64 dma_cap_set(DMA_SLAVE, mask); 65 66 cryp->tx = dma_request_chan(cryp->dev, "tx"); 67 if (IS_ERR(cryp->tx)) 68 return dev_err_probe(cryp->dev, PTR_ERR(cryp->tx), 69 "Error requesting tx dma channel.\n"); 70 71 cryp->rx = dma_request_chan(cryp->dev, "rx"); 72 if (IS_ERR(cryp->rx)) { 73 dma_release_channel(cryp->tx); 74 return dev_err_probe(cryp->dev, PTR_ERR(cryp->rx), 75 "Error requesting rx dma channel.\n"); 76 } 77 78 return 0; 79 } 80 81 static void starfive_dma_cleanup(struct starfive_cryp_dev *cryp) 82 { 83 dma_release_channel(cryp->tx); 84 dma_release_channel(cryp->rx); 85 } 86 87 static int starfive_cryp_probe(struct platform_device *pdev) 88 { 89 struct starfive_cryp_dev *cryp; 90 struct resource *res; 91 int ret; 92 93 cryp = devm_kzalloc(&pdev->dev, sizeof(*cryp), GFP_KERNEL); 94 if (!cryp) 95 return -ENOMEM; 96 97 platform_set_drvdata(pdev, cryp); 98 cryp->dev = &pdev->dev; 99 100 cryp->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 101 if (IS_ERR(cryp->base)) 102 return dev_err_probe(&pdev->dev, PTR_ERR(cryp->base), 103 "Error remapping memory for platform device\n"); 104 105 cryp->phys_base = res->start; 106 cryp->dma_maxburst = 32; 107 cryp->side_chan = side_chan; 108 109 cryp->hclk = devm_clk_get(&pdev->dev, "hclk"); 110 if (IS_ERR(cryp->hclk)) 111 return dev_err_probe(&pdev->dev, PTR_ERR(cryp->hclk), 112 "Error getting hardware reference clock\n"); 113 114 cryp->ahb = devm_clk_get(&pdev->dev, "ahb"); 115 if (IS_ERR(cryp->ahb)) 116 return dev_err_probe(&pdev->dev, PTR_ERR(cryp->ahb), 117 "Error getting ahb reference clock\n"); 118 119 cryp->rst = devm_reset_control_get_shared(cryp->dev, NULL); 120 if (IS_ERR(cryp->rst)) 121 return dev_err_probe(&pdev->dev, PTR_ERR(cryp->rst), 122 "Error getting hardware reset line\n"); 123 124 clk_prepare_enable(cryp->hclk); 125 clk_prepare_enable(cryp->ahb); 126 reset_control_deassert(cryp->rst); 127 128 spin_lock(&dev_list.lock); 129 list_add(&cryp->list, &dev_list.dev_list); 130 spin_unlock(&dev_list.lock); 131 132 ret = starfive_dma_init(cryp); 133 if (ret) 134 goto err_dma_init; 135 136 /* Initialize crypto engine */ 137 cryp->engine = crypto_engine_alloc_init(&pdev->dev, 1); 138 if (!cryp->engine) { 139 ret = -ENOMEM; 140 goto err_engine; 141 } 142 143 ret = crypto_engine_start(cryp->engine); 144 if (ret) 145 goto err_engine_start; 146 147 ret = starfive_aes_register_algs(); 148 if (ret) 149 goto err_engine_start; 150 151 ret = starfive_hash_register_algs(); 152 if (ret) 153 goto err_algs_hash; 154 155 ret = starfive_rsa_register_algs(); 156 if (ret) 157 goto err_algs_rsa; 158 159 return 0; 160 161 err_algs_rsa: 162 starfive_hash_unregister_algs(); 163 err_algs_hash: 164 starfive_aes_unregister_algs(); 165 err_engine_start: 166 crypto_engine_exit(cryp->engine); 167 err_engine: 168 starfive_dma_cleanup(cryp); 169 err_dma_init: 170 spin_lock(&dev_list.lock); 171 list_del(&cryp->list); 172 spin_unlock(&dev_list.lock); 173 174 clk_disable_unprepare(cryp->hclk); 175 clk_disable_unprepare(cryp->ahb); 176 reset_control_assert(cryp->rst); 177 178 return ret; 179 } 180 181 static void starfive_cryp_remove(struct platform_device *pdev) 182 { 183 struct starfive_cryp_dev *cryp = platform_get_drvdata(pdev); 184 185 starfive_aes_unregister_algs(); 186 starfive_hash_unregister_algs(); 187 starfive_rsa_unregister_algs(); 188 189 crypto_engine_exit(cryp->engine); 190 191 starfive_dma_cleanup(cryp); 192 193 spin_lock(&dev_list.lock); 194 list_del(&cryp->list); 195 spin_unlock(&dev_list.lock); 196 197 clk_disable_unprepare(cryp->hclk); 198 clk_disable_unprepare(cryp->ahb); 199 reset_control_assert(cryp->rst); 200 } 201 202 static const struct of_device_id starfive_dt_ids[] __maybe_unused = { 203 { .compatible = "starfive,jh7110-crypto", .data = NULL}, 204 {}, 205 }; 206 MODULE_DEVICE_TABLE(of, starfive_dt_ids); 207 208 static struct platform_driver starfive_cryp_driver = { 209 .probe = starfive_cryp_probe, 210 .remove = starfive_cryp_remove, 211 .driver = { 212 .name = DRIVER_NAME, 213 .of_match_table = starfive_dt_ids, 214 }, 215 }; 216 217 module_platform_driver(starfive_cryp_driver); 218 219 MODULE_LICENSE("GPL"); 220 MODULE_DESCRIPTION("StarFive JH7110 Cryptographic Module"); 221