1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Cryptographic API. 4 // 5 // Support for Samsung S5PV210 and Exynos HW acceleration. 6 // 7 // Copyright (C) 2011 NetUP Inc. All rights reserved. 8 // Copyright (c) 2017 Samsung Electronics Co., Ltd. All rights reserved. 9 // 10 // Hash part based on omap-sham.c driver. 11 12 #include <crypto/aes.h> 13 #include <crypto/ctr.h> 14 #include <crypto/internal/hash.h> 15 #include <crypto/internal/skcipher.h> 16 #include <crypto/md5.h> 17 #include <crypto/scatterwalk.h> 18 #include <crypto/sha1.h> 19 #include <crypto/sha2.h> 20 #include <linux/clk.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/err.h> 23 #include <linux/init.h> 24 #include <linux/interrupt.h> 25 #include <linux/io.h> 26 #include <linux/kernel.h> 27 #include <linux/module.h> 28 #include <linux/of.h> 29 #include <linux/platform_device.h> 30 #include <linux/scatterlist.h> 31 #include <linux/slab.h> 32 #include <linux/spinlock.h> 33 #include <linux/string.h> 34 35 #define _SBF(s, v) ((v) << (s)) 36 37 /* Feed control registers */ 38 #define SSS_REG_FCINTSTAT 0x0000 39 #define SSS_FCINTSTAT_HPARTINT BIT(7) 40 #define SSS_FCINTSTAT_HDONEINT BIT(5) 41 #define SSS_FCINTSTAT_BRDMAINT BIT(3) 42 #define SSS_FCINTSTAT_BTDMAINT BIT(2) 43 #define SSS_FCINTSTAT_HRDMAINT BIT(1) 44 #define SSS_FCINTSTAT_PKDMAINT BIT(0) 45 46 #define SSS_REG_FCINTENSET 0x0004 47 #define SSS_FCINTENSET_HPARTINTENSET BIT(7) 48 #define SSS_FCINTENSET_HDONEINTENSET BIT(5) 49 #define SSS_FCINTENSET_BRDMAINTENSET BIT(3) 50 #define SSS_FCINTENSET_BTDMAINTENSET BIT(2) 51 #define SSS_FCINTENSET_HRDMAINTENSET BIT(1) 52 #define SSS_FCINTENSET_PKDMAINTENSET BIT(0) 53 54 #define SSS_REG_FCINTENCLR 0x0008 55 #define SSS_FCINTENCLR_HPARTINTENCLR BIT(7) 56 #define SSS_FCINTENCLR_HDONEINTENCLR BIT(5) 57 #define SSS_FCINTENCLR_BRDMAINTENCLR BIT(3) 58 #define SSS_FCINTENCLR_BTDMAINTENCLR BIT(2) 59 #define SSS_FCINTENCLR_HRDMAINTENCLR BIT(1) 60 #define SSS_FCINTENCLR_PKDMAINTENCLR BIT(0) 61 62 #define SSS_REG_FCINTPEND 0x000C 63 #define SSS_FCINTPEND_HPARTINTP BIT(7) 64 #define SSS_FCINTPEND_HDONEINTP BIT(5) 65 #define SSS_FCINTPEND_BRDMAINTP BIT(3) 66 #define SSS_FCINTPEND_BTDMAINTP BIT(2) 67 #define SSS_FCINTPEND_HRDMAINTP BIT(1) 68 #define SSS_FCINTPEND_PKDMAINTP BIT(0) 69 70 #define SSS_REG_FCFIFOSTAT 0x0010 71 #define SSS_FCFIFOSTAT_BRFIFOFUL BIT(7) 72 #define SSS_FCFIFOSTAT_BRFIFOEMP BIT(6) 73 #define SSS_FCFIFOSTAT_BTFIFOFUL BIT(5) 74 #define SSS_FCFIFOSTAT_BTFIFOEMP BIT(4) 75 #define SSS_FCFIFOSTAT_HRFIFOFUL BIT(3) 76 #define SSS_FCFIFOSTAT_HRFIFOEMP BIT(2) 77 #define SSS_FCFIFOSTAT_PKFIFOFUL BIT(1) 78 #define SSS_FCFIFOSTAT_PKFIFOEMP BIT(0) 79 80 #define SSS_REG_FCFIFOCTRL 0x0014 81 #define SSS_FCFIFOCTRL_DESSEL BIT(2) 82 #define SSS_HASHIN_INDEPENDENT _SBF(0, 0x00) 83 #define SSS_HASHIN_CIPHER_INPUT _SBF(0, 0x01) 84 #define SSS_HASHIN_CIPHER_OUTPUT _SBF(0, 0x02) 85 #define SSS_HASHIN_MASK _SBF(0, 0x03) 86 87 #define SSS_REG_FCBRDMAS 0x0020 88 #define SSS_REG_FCBRDMAL 0x0024 89 #define SSS_REG_FCBRDMAC 0x0028 90 #define SSS_FCBRDMAC_BYTESWAP BIT(1) 91 #define SSS_FCBRDMAC_FLUSH BIT(0) 92 93 #define SSS_REG_FCBTDMAS 0x0030 94 #define SSS_REG_FCBTDMAL 0x0034 95 #define SSS_REG_FCBTDMAC 0x0038 96 #define SSS_FCBTDMAC_BYTESWAP BIT(1) 97 #define SSS_FCBTDMAC_FLUSH BIT(0) 98 99 #define SSS_REG_FCHRDMAS 0x0040 100 #define SSS_REG_FCHRDMAL 0x0044 101 #define SSS_REG_FCHRDMAC 0x0048 102 #define SSS_FCHRDMAC_BYTESWAP BIT(1) 103 #define SSS_FCHRDMAC_FLUSH BIT(0) 104 105 #define SSS_REG_FCPKDMAS 0x0050 106 #define SSS_REG_FCPKDMAL 0x0054 107 #define SSS_REG_FCPKDMAC 0x0058 108 #define SSS_FCPKDMAC_BYTESWAP BIT(3) 109 #define SSS_FCPKDMAC_DESCEND BIT(2) 110 #define SSS_FCPKDMAC_TRANSMIT BIT(1) 111 #define SSS_FCPKDMAC_FLUSH BIT(0) 112 113 #define SSS_REG_FCPKDMAO 0x005C 114 115 /* AES registers */ 116 #define SSS_REG_AES_CONTROL 0x00 117 #define SSS_AES_BYTESWAP_DI BIT(11) 118 #define SSS_AES_BYTESWAP_DO BIT(10) 119 #define SSS_AES_BYTESWAP_IV BIT(9) 120 #define SSS_AES_BYTESWAP_CNT BIT(8) 121 #define SSS_AES_BYTESWAP_KEY BIT(7) 122 #define SSS_AES_KEY_CHANGE_MODE BIT(6) 123 #define SSS_AES_KEY_SIZE_128 _SBF(4, 0x00) 124 #define SSS_AES_KEY_SIZE_192 _SBF(4, 0x01) 125 #define SSS_AES_KEY_SIZE_256 _SBF(4, 0x02) 126 #define SSS_AES_FIFO_MODE BIT(3) 127 #define SSS_AES_CHAIN_MODE_ECB _SBF(1, 0x00) 128 #define SSS_AES_CHAIN_MODE_CBC _SBF(1, 0x01) 129 #define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02) 130 #define SSS_AES_MODE_DECRYPT BIT(0) 131 132 #define SSS_REG_AES_STATUS 0x04 133 #define SSS_AES_BUSY BIT(2) 134 #define SSS_AES_INPUT_READY BIT(1) 135 #define SSS_AES_OUTPUT_READY BIT(0) 136 137 #define SSS_REG_AES_IN_DATA(s) (0x10 + (s << 2)) 138 #define SSS_REG_AES_OUT_DATA(s) (0x20 + (s << 2)) 139 #define SSS_REG_AES_IV_DATA(s) (0x30 + (s << 2)) 140 #define SSS_REG_AES_CNT_DATA(s) (0x40 + (s << 2)) 141 #define SSS_REG_AES_KEY_DATA(s) (0x80 + (s << 2)) 142 143 #define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg)) 144 #define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg)) 145 #define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg)) 146 147 #define SSS_AES_REG(dev, reg) ((dev)->aes_ioaddr + SSS_REG_##reg) 148 #define SSS_AES_WRITE(dev, reg, val) __raw_writel((val), \ 149 SSS_AES_REG(dev, reg)) 150 151 /* HW engine modes */ 152 #define FLAGS_AES_DECRYPT BIT(0) 153 #define FLAGS_AES_MODE_MASK _SBF(1, 0x03) 154 #define FLAGS_AES_CBC _SBF(1, 0x01) 155 #define FLAGS_AES_CTR _SBF(1, 0x02) 156 157 #define AES_KEY_LEN 16 158 #define CRYPTO_QUEUE_LEN 1 159 160 /* HASH registers */ 161 #define SSS_REG_HASH_CTRL 0x00 162 163 #define SSS_HASH_USER_IV_EN BIT(5) 164 #define SSS_HASH_INIT_BIT BIT(4) 165 #define SSS_HASH_ENGINE_SHA1 _SBF(1, 0x00) 166 #define SSS_HASH_ENGINE_MD5 _SBF(1, 0x01) 167 #define SSS_HASH_ENGINE_SHA256 _SBF(1, 0x02) 168 169 #define SSS_HASH_ENGINE_MASK _SBF(1, 0x03) 170 171 #define SSS_REG_HASH_CTRL_PAUSE 0x04 172 173 #define SSS_HASH_PAUSE BIT(0) 174 175 #define SSS_REG_HASH_CTRL_FIFO 0x08 176 177 #define SSS_HASH_FIFO_MODE_DMA BIT(0) 178 #define SSS_HASH_FIFO_MODE_CPU 0 179 180 #define SSS_REG_HASH_CTRL_SWAP 0x0C 181 182 #define SSS_HASH_BYTESWAP_DI BIT(3) 183 #define SSS_HASH_BYTESWAP_DO BIT(2) 184 #define SSS_HASH_BYTESWAP_IV BIT(1) 185 #define SSS_HASH_BYTESWAP_KEY BIT(0) 186 187 #define SSS_REG_HASH_STATUS 0x10 188 189 #define SSS_HASH_STATUS_MSG_DONE BIT(6) 190 #define SSS_HASH_STATUS_PARTIAL_DONE BIT(4) 191 #define SSS_HASH_STATUS_BUFFER_READY BIT(0) 192 193 #define SSS_REG_HASH_MSG_SIZE_LOW 0x20 194 #define SSS_REG_HASH_MSG_SIZE_HIGH 0x24 195 196 #define SSS_REG_HASH_PRE_MSG_SIZE_LOW 0x28 197 #define SSS_REG_HASH_PRE_MSG_SIZE_HIGH 0x2C 198 199 #define SSS_REG_HASH_IV(s) (0xB0 + ((s) << 2)) 200 #define SSS_REG_HASH_OUT(s) (0x100 + ((s) << 2)) 201 202 #define HASH_BLOCK_SIZE 64 203 #define HASH_REG_SIZEOF 4 204 #define HASH_MD5_MAX_REG (MD5_DIGEST_SIZE / HASH_REG_SIZEOF) 205 #define HASH_SHA1_MAX_REG (SHA1_DIGEST_SIZE / HASH_REG_SIZEOF) 206 #define HASH_SHA256_MAX_REG (SHA256_DIGEST_SIZE / HASH_REG_SIZEOF) 207 208 /* 209 * HASH bit numbers, used by device, setting in dev->hash_flags with 210 * functions set_bit(), clear_bit() or tested with test_bit() or BIT(), 211 * to keep HASH state BUSY or FREE, or to signal state from irq_handler 212 * to hash_tasklet. SGS keep track of allocated memory for scatterlist 213 */ 214 #define HASH_FLAGS_BUSY 0 215 #define HASH_FLAGS_FINAL 1 216 #define HASH_FLAGS_DMA_ACTIVE 2 217 #define HASH_FLAGS_OUTPUT_READY 3 218 #define HASH_FLAGS_DMA_READY 4 219 #define HASH_FLAGS_SGS_COPIED 5 220 #define HASH_FLAGS_SGS_ALLOCED 6 221 222 /* HASH HW constants */ 223 #define BUFLEN HASH_BLOCK_SIZE 224 225 #define SSS_HASH_QUEUE_LENGTH 10 226 227 /** 228 * struct samsung_aes_variant - platform specific SSS driver data 229 * @aes_offset: AES register offset from SSS module's base. 230 * @hash_offset: HASH register offset from SSS module's base. 231 * @clk_names: names of clocks needed to run SSS IP 232 * 233 * Specifies platform specific configuration of SSS module. 234 * Note: A structure for driver specific platform data is used for future 235 * expansion of its usage. 236 */ 237 struct samsung_aes_variant { 238 unsigned int aes_offset; 239 unsigned int hash_offset; 240 const char *clk_names[2]; 241 }; 242 243 struct s5p_aes_reqctx { 244 unsigned long mode; 245 }; 246 247 struct s5p_aes_ctx { 248 struct s5p_aes_dev *dev; 249 250 u8 aes_key[AES_MAX_KEY_SIZE]; 251 u8 nonce[CTR_RFC3686_NONCE_SIZE]; 252 int keylen; 253 }; 254 255 /** 256 * struct s5p_aes_dev - Crypto device state container 257 * @dev: Associated device 258 * @clk: Clock for accessing hardware 259 * @pclk: APB bus clock necessary to access the hardware 260 * @ioaddr: Mapped IO memory region 261 * @aes_ioaddr: Per-varian offset for AES block IO memory 262 * @irq_fc: Feed control interrupt line 263 * @req: Crypto request currently handled by the device 264 * @ctx: Configuration for currently handled crypto request 265 * @sg_src: Scatter list with source data for currently handled block 266 * in device. This is DMA-mapped into device. 267 * @sg_dst: Scatter list with destination data for currently handled block 268 * in device. This is DMA-mapped into device. 269 * @sg_src_cpy: In case of unaligned access, copied scatter list 270 * with source data. 271 * @sg_dst_cpy: In case of unaligned access, copied scatter list 272 * with destination data. 273 * @tasklet: New request scheduling jib 274 * @queue: Crypto queue 275 * @busy: Indicates whether the device is currently handling some request 276 * thus it uses some of the fields from this state, like: 277 * req, ctx, sg_src/dst (and copies). This essentially 278 * protects against concurrent access to these fields. 279 * @lock: Lock for protecting both access to device hardware registers 280 * and fields related to current request (including the busy field). 281 * @res: Resources for hash. 282 * @io_hash_base: Per-variant offset for HASH block IO memory. 283 * @hash_lock: Lock for protecting hash_req, hash_queue and hash_flags 284 * variable. 285 * @hash_flags: Flags for current HASH op. 286 * @hash_queue: Async hash queue. 287 * @hash_tasklet: New HASH request scheduling job. 288 * @xmit_buf: Buffer for current HASH request transfer into SSS block. 289 * @hash_req: Current request sending to SSS HASH block. 290 * @hash_sg_iter: Scatterlist transferred through DMA into SSS HASH block. 291 * @hash_sg_cnt: Counter for hash_sg_iter. 292 * 293 * @use_hash: true if HASH algs enabled 294 */ 295 struct s5p_aes_dev { 296 struct device *dev; 297 struct clk *clk; 298 struct clk *pclk; 299 void __iomem *ioaddr; 300 void __iomem *aes_ioaddr; 301 int irq_fc; 302 303 struct skcipher_request *req; 304 struct s5p_aes_ctx *ctx; 305 struct scatterlist *sg_src; 306 struct scatterlist *sg_dst; 307 308 struct scatterlist *sg_src_cpy; 309 struct scatterlist *sg_dst_cpy; 310 311 struct tasklet_struct tasklet; 312 struct crypto_queue queue; 313 bool busy; 314 spinlock_t lock; 315 316 struct resource *res; 317 void __iomem *io_hash_base; 318 319 spinlock_t hash_lock; /* protect hash_ vars */ 320 unsigned long hash_flags; 321 struct crypto_queue hash_queue; 322 struct tasklet_struct hash_tasklet; 323 324 u8 xmit_buf[BUFLEN]; 325 struct ahash_request *hash_req; 326 struct scatterlist *hash_sg_iter; 327 unsigned int hash_sg_cnt; 328 329 bool use_hash; 330 }; 331 332 /** 333 * struct s5p_hash_reqctx - HASH request context 334 * @dd: Associated device 335 * @op_update: Current request operation (OP_UPDATE or OP_FINAL) 336 * @digcnt: Number of bytes processed by HW (without buffer[] ones) 337 * @digest: Digest message or IV for partial result 338 * @nregs: Number of HW registers for digest or IV read/write 339 * @engine: Bits for selecting type of HASH in SSS block 340 * @sg: sg for DMA transfer 341 * @sg_len: Length of sg for DMA transfer 342 * @sgl: sg for joining buffer and req->src scatterlist 343 * @skip: Skip offset in req->src for current op 344 * @total: Total number of bytes for current request 345 * @finup: Keep state for finup or final. 346 * @error: Keep track of error. 347 * @bufcnt: Number of bytes holded in buffer[] 348 * @buffer: For byte(s) from end of req->src in UPDATE op 349 */ 350 struct s5p_hash_reqctx { 351 struct s5p_aes_dev *dd; 352 bool op_update; 353 354 u64 digcnt; 355 u8 digest[SHA256_DIGEST_SIZE]; 356 357 unsigned int nregs; /* digest_size / sizeof(reg) */ 358 u32 engine; 359 360 struct scatterlist *sg; 361 unsigned int sg_len; 362 struct scatterlist sgl[2]; 363 unsigned int skip; 364 unsigned int total; 365 bool finup; 366 bool error; 367 368 u32 bufcnt; 369 u8 buffer[]; 370 }; 371 372 /** 373 * struct s5p_hash_ctx - HASH transformation context 374 * @dd: Associated device 375 * @flags: Bits for algorithm HASH. 376 * @fallback: Software transformation for zero message or size < BUFLEN. 377 */ 378 struct s5p_hash_ctx { 379 struct s5p_aes_dev *dd; 380 unsigned long flags; 381 struct crypto_shash *fallback; 382 }; 383 384 static const struct samsung_aes_variant s5p_aes_data = { 385 .aes_offset = 0x4000, 386 .hash_offset = 0x6000, 387 .clk_names = { "secss", }, 388 }; 389 390 static const struct samsung_aes_variant exynos_aes_data = { 391 .aes_offset = 0x200, 392 .hash_offset = 0x400, 393 .clk_names = { "secss", }, 394 }; 395 396 static const struct samsung_aes_variant exynos5433_slim_aes_data = { 397 .aes_offset = 0x400, 398 .hash_offset = 0x800, 399 .clk_names = { "aclk", "pclk", }, 400 }; 401 402 static const struct of_device_id s5p_sss_dt_match[] = { 403 { 404 .compatible = "samsung,s5pv210-secss", 405 .data = &s5p_aes_data, 406 }, 407 { 408 .compatible = "samsung,exynos4210-secss", 409 .data = &exynos_aes_data, 410 }, 411 { 412 .compatible = "samsung,exynos5433-slim-sss", 413 .data = &exynos5433_slim_aes_data, 414 }, 415 { }, 416 }; 417 MODULE_DEVICE_TABLE(of, s5p_sss_dt_match); 418 419 static inline const struct samsung_aes_variant *find_s5p_sss_version 420 (const struct platform_device *pdev) 421 { 422 if (IS_ENABLED(CONFIG_OF) && (pdev->dev.of_node)) 423 return of_device_get_match_data(&pdev->dev); 424 425 return (const struct samsung_aes_variant *) 426 platform_get_device_id(pdev)->driver_data; 427 } 428 429 static struct s5p_aes_dev *s5p_dev; 430 431 static void s5p_set_dma_indata(struct s5p_aes_dev *dev, 432 const struct scatterlist *sg) 433 { 434 SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg)); 435 SSS_WRITE(dev, FCBRDMAL, sg_dma_len(sg)); 436 } 437 438 static void s5p_set_dma_outdata(struct s5p_aes_dev *dev, 439 const struct scatterlist *sg) 440 { 441 SSS_WRITE(dev, FCBTDMAS, sg_dma_address(sg)); 442 SSS_WRITE(dev, FCBTDMAL, sg_dma_len(sg)); 443 } 444 445 static void s5p_free_sg_cpy(struct s5p_aes_dev *dev, struct scatterlist **sg) 446 { 447 int len; 448 449 if (!*sg) 450 return; 451 452 len = ALIGN(dev->req->cryptlen, AES_BLOCK_SIZE); 453 free_pages((unsigned long)sg_virt(*sg), get_order(len)); 454 455 kfree(*sg); 456 *sg = NULL; 457 } 458 459 static void s5p_sg_done(struct s5p_aes_dev *dev) 460 { 461 struct skcipher_request *req = dev->req; 462 struct s5p_aes_reqctx *reqctx = skcipher_request_ctx(req); 463 464 if (dev->sg_dst_cpy) { 465 dev_dbg(dev->dev, 466 "Copying %d bytes of output data back to original place\n", 467 dev->req->cryptlen); 468 memcpy_to_sglist(dev->req->dst, 0, sg_virt(dev->sg_dst_cpy), 469 dev->req->cryptlen); 470 } 471 s5p_free_sg_cpy(dev, &dev->sg_src_cpy); 472 s5p_free_sg_cpy(dev, &dev->sg_dst_cpy); 473 if (reqctx->mode & FLAGS_AES_CBC) 474 memcpy_fromio(req->iv, dev->aes_ioaddr + SSS_REG_AES_IV_DATA(0), AES_BLOCK_SIZE); 475 476 else if (reqctx->mode & FLAGS_AES_CTR) 477 memcpy_fromio(req->iv, dev->aes_ioaddr + SSS_REG_AES_CNT_DATA(0), AES_BLOCK_SIZE); 478 } 479 480 /* Calls the completion. Cannot be called with dev->lock hold. */ 481 static void s5p_aes_complete(struct skcipher_request *req, int err) 482 { 483 skcipher_request_complete(req, err); 484 } 485 486 static void s5p_unset_outdata(struct s5p_aes_dev *dev) 487 { 488 dma_unmap_sg(dev->dev, dev->sg_dst, 1, DMA_FROM_DEVICE); 489 } 490 491 static void s5p_unset_indata(struct s5p_aes_dev *dev) 492 { 493 dma_unmap_sg(dev->dev, dev->sg_src, 1, DMA_TO_DEVICE); 494 } 495 496 static int s5p_make_sg_cpy(struct s5p_aes_dev *dev, struct scatterlist *src, 497 struct scatterlist **dst) 498 { 499 void *pages; 500 int len; 501 502 *dst = kmalloc_obj(**dst, GFP_ATOMIC); 503 if (!*dst) 504 return -ENOMEM; 505 506 len = ALIGN(dev->req->cryptlen, AES_BLOCK_SIZE); 507 pages = (void *)__get_free_pages(GFP_ATOMIC, get_order(len)); 508 if (!pages) { 509 kfree(*dst); 510 *dst = NULL; 511 return -ENOMEM; 512 } 513 514 memcpy_from_sglist(pages, src, 0, dev->req->cryptlen); 515 516 sg_init_table(*dst, 1); 517 sg_set_buf(*dst, pages, len); 518 519 return 0; 520 } 521 522 static int s5p_set_outdata(struct s5p_aes_dev *dev, struct scatterlist *sg) 523 { 524 if (!sg->length) 525 return -EINVAL; 526 527 if (!dma_map_sg(dev->dev, sg, 1, DMA_FROM_DEVICE)) 528 return -ENOMEM; 529 530 dev->sg_dst = sg; 531 532 return 0; 533 } 534 535 static int s5p_set_indata(struct s5p_aes_dev *dev, struct scatterlist *sg) 536 { 537 if (!sg->length) 538 return -EINVAL; 539 540 if (!dma_map_sg(dev->dev, sg, 1, DMA_TO_DEVICE)) 541 return -ENOMEM; 542 543 dev->sg_src = sg; 544 545 return 0; 546 } 547 548 /* 549 * Returns -ERRNO on error (mapping of new data failed). 550 * On success returns: 551 * - 0 if there is no more data, 552 * - 1 if new transmitting (output) data is ready and its address+length 553 * have to be written to device (by calling s5p_set_dma_outdata()). 554 */ 555 static int s5p_aes_tx(struct s5p_aes_dev *dev) 556 { 557 int ret = 0; 558 559 s5p_unset_outdata(dev); 560 561 if (!sg_is_last(dev->sg_dst)) { 562 ret = s5p_set_outdata(dev, sg_next(dev->sg_dst)); 563 if (!ret) 564 ret = 1; 565 } 566 567 return ret; 568 } 569 570 /* 571 * Returns -ERRNO on error (mapping of new data failed). 572 * On success returns: 573 * - 0 if there is no more data, 574 * - 1 if new receiving (input) data is ready and its address+length 575 * have to be written to device (by calling s5p_set_dma_indata()). 576 */ 577 static int s5p_aes_rx(struct s5p_aes_dev *dev/*, bool *set_dma*/) 578 { 579 int ret = 0; 580 581 s5p_unset_indata(dev); 582 583 if (!sg_is_last(dev->sg_src)) { 584 ret = s5p_set_indata(dev, sg_next(dev->sg_src)); 585 if (!ret) 586 ret = 1; 587 } 588 589 return ret; 590 } 591 592 static inline u32 s5p_hash_read(struct s5p_aes_dev *dd, u32 offset) 593 { 594 return __raw_readl(dd->io_hash_base + offset); 595 } 596 597 static inline void s5p_hash_write(struct s5p_aes_dev *dd, 598 u32 offset, u32 value) 599 { 600 __raw_writel(value, dd->io_hash_base + offset); 601 } 602 603 /** 604 * s5p_set_dma_hashdata() - start DMA with sg 605 * @dev: device 606 * @sg: scatterlist ready to DMA transmit 607 */ 608 static void s5p_set_dma_hashdata(struct s5p_aes_dev *dev, 609 const struct scatterlist *sg) 610 { 611 dev->hash_sg_cnt--; 612 SSS_WRITE(dev, FCHRDMAS, sg_dma_address(sg)); 613 SSS_WRITE(dev, FCHRDMAL, sg_dma_len(sg)); /* DMA starts */ 614 } 615 616 /** 617 * s5p_hash_rx() - get next hash_sg_iter 618 * @dev: device 619 * 620 * Return: 621 * 2 if there is no more data and it is UPDATE op 622 * 1 if new receiving (input) data is ready and can be written to device 623 * 0 if there is no more data and it is FINAL op 624 */ 625 static int s5p_hash_rx(struct s5p_aes_dev *dev) 626 { 627 if (dev->hash_sg_cnt > 0) { 628 dev->hash_sg_iter = sg_next(dev->hash_sg_iter); 629 return 1; 630 } 631 632 set_bit(HASH_FLAGS_DMA_READY, &dev->hash_flags); 633 if (test_bit(HASH_FLAGS_FINAL, &dev->hash_flags)) 634 return 0; 635 636 return 2; 637 } 638 639 static irqreturn_t s5p_aes_interrupt(int irq, void *dev_id) 640 { 641 struct s5p_aes_dev *dev = dev_id; 642 struct skcipher_request *req; 643 int err_dma_tx = 0; 644 int err_dma_rx = 0; 645 int err_dma_hx = 0; 646 bool tx_end = false; 647 bool hx_end = false; 648 unsigned long flags; 649 u32 status, st_bits; 650 int err; 651 652 spin_lock_irqsave(&dev->lock, flags); 653 654 /* 655 * Handle rx or tx interrupt. If there is still data (scatterlist did not 656 * reach end), then map next scatterlist entry. 657 * In case of such mapping error, s5p_aes_complete() should be called. 658 * 659 * If there is no more data in tx scatter list, call s5p_aes_complete() 660 * and schedule new tasklet. 661 * 662 * Handle hx interrupt. If there is still data map next entry. 663 */ 664 status = SSS_READ(dev, FCINTSTAT); 665 if (status & SSS_FCINTSTAT_BRDMAINT) 666 err_dma_rx = s5p_aes_rx(dev); 667 668 if (status & SSS_FCINTSTAT_BTDMAINT) { 669 if (sg_is_last(dev->sg_dst)) 670 tx_end = true; 671 err_dma_tx = s5p_aes_tx(dev); 672 } 673 674 if (status & SSS_FCINTSTAT_HRDMAINT) 675 err_dma_hx = s5p_hash_rx(dev); 676 677 st_bits = status & (SSS_FCINTSTAT_BRDMAINT | SSS_FCINTSTAT_BTDMAINT | 678 SSS_FCINTSTAT_HRDMAINT); 679 /* clear DMA bits */ 680 SSS_WRITE(dev, FCINTPEND, st_bits); 681 682 /* clear HASH irq bits */ 683 if (status & (SSS_FCINTSTAT_HDONEINT | SSS_FCINTSTAT_HPARTINT)) { 684 /* cannot have both HPART and HDONE */ 685 if (status & SSS_FCINTSTAT_HPARTINT) 686 st_bits = SSS_HASH_STATUS_PARTIAL_DONE; 687 688 if (status & SSS_FCINTSTAT_HDONEINT) 689 st_bits = SSS_HASH_STATUS_MSG_DONE; 690 691 set_bit(HASH_FLAGS_OUTPUT_READY, &dev->hash_flags); 692 s5p_hash_write(dev, SSS_REG_HASH_STATUS, st_bits); 693 hx_end = true; 694 /* when DONE or PART, do not handle HASH DMA */ 695 err_dma_hx = 0; 696 } 697 698 if (err_dma_rx < 0) { 699 err = err_dma_rx; 700 goto error; 701 } 702 if (err_dma_tx < 0) { 703 err = err_dma_tx; 704 goto error; 705 } 706 707 if (tx_end) { 708 s5p_sg_done(dev); 709 if (err_dma_hx == 1) 710 s5p_set_dma_hashdata(dev, dev->hash_sg_iter); 711 712 spin_unlock_irqrestore(&dev->lock, flags); 713 714 s5p_aes_complete(dev->req, 0); 715 /* Device is still busy */ 716 tasklet_schedule(&dev->tasklet); 717 } else { 718 /* 719 * Writing length of DMA block (either receiving or 720 * transmitting) will start the operation immediately, so this 721 * should be done at the end (even after clearing pending 722 * interrupts to not miss the interrupt). 723 */ 724 if (err_dma_tx == 1) 725 s5p_set_dma_outdata(dev, dev->sg_dst); 726 if (err_dma_rx == 1) 727 s5p_set_dma_indata(dev, dev->sg_src); 728 if (err_dma_hx == 1) 729 s5p_set_dma_hashdata(dev, dev->hash_sg_iter); 730 731 spin_unlock_irqrestore(&dev->lock, flags); 732 } 733 734 goto hash_irq_end; 735 736 error: 737 s5p_sg_done(dev); 738 dev->busy = false; 739 req = dev->req; 740 if (err_dma_hx == 1) 741 s5p_set_dma_hashdata(dev, dev->hash_sg_iter); 742 743 spin_unlock_irqrestore(&dev->lock, flags); 744 s5p_aes_complete(req, err); 745 746 hash_irq_end: 747 /* 748 * Note about else if: 749 * when hash_sg_iter reaches end and its UPDATE op, 750 * issue SSS_HASH_PAUSE and wait for HPART irq 751 */ 752 if (hx_end) 753 tasklet_schedule(&dev->hash_tasklet); 754 else if (err_dma_hx == 2) 755 s5p_hash_write(dev, SSS_REG_HASH_CTRL_PAUSE, 756 SSS_HASH_PAUSE); 757 758 return IRQ_HANDLED; 759 } 760 761 /** 762 * s5p_hash_read_msg() - read message or IV from HW 763 * @req: AHASH request 764 */ 765 static void s5p_hash_read_msg(struct ahash_request *req) 766 { 767 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 768 struct s5p_aes_dev *dd = ctx->dd; 769 u32 *hash = (u32 *)ctx->digest; 770 unsigned int i; 771 772 for (i = 0; i < ctx->nregs; i++) 773 hash[i] = s5p_hash_read(dd, SSS_REG_HASH_OUT(i)); 774 } 775 776 /** 777 * s5p_hash_write_ctx_iv() - write IV for next partial/finup op. 778 * @dd: device 779 * @ctx: request context 780 */ 781 static void s5p_hash_write_ctx_iv(struct s5p_aes_dev *dd, 782 const struct s5p_hash_reqctx *ctx) 783 { 784 const u32 *hash = (const u32 *)ctx->digest; 785 unsigned int i; 786 787 for (i = 0; i < ctx->nregs; i++) 788 s5p_hash_write(dd, SSS_REG_HASH_IV(i), hash[i]); 789 } 790 791 /** 792 * s5p_hash_write_iv() - write IV for next partial/finup op. 793 * @req: AHASH request 794 */ 795 static void s5p_hash_write_iv(struct ahash_request *req) 796 { 797 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 798 799 s5p_hash_write_ctx_iv(ctx->dd, ctx); 800 } 801 802 /** 803 * s5p_hash_copy_result() - copy digest into req->result 804 * @req: AHASH request 805 */ 806 static void s5p_hash_copy_result(struct ahash_request *req) 807 { 808 const struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 809 810 if (!req->result) 811 return; 812 813 memcpy(req->result, ctx->digest, ctx->nregs * HASH_REG_SIZEOF); 814 } 815 816 /** 817 * s5p_hash_dma_flush() - flush HASH DMA 818 * @dev: secss device 819 */ 820 static void s5p_hash_dma_flush(struct s5p_aes_dev *dev) 821 { 822 SSS_WRITE(dev, FCHRDMAC, SSS_FCHRDMAC_FLUSH); 823 } 824 825 /** 826 * s5p_hash_dma_enable() - enable DMA mode for HASH 827 * @dev: secss device 828 * 829 * enable DMA mode for HASH 830 */ 831 static void s5p_hash_dma_enable(struct s5p_aes_dev *dev) 832 { 833 s5p_hash_write(dev, SSS_REG_HASH_CTRL_FIFO, SSS_HASH_FIFO_MODE_DMA); 834 } 835 836 /** 837 * s5p_hash_irq_disable() - disable irq HASH signals 838 * @dev: secss device 839 * @flags: bitfield with irq's to be disabled 840 */ 841 static void s5p_hash_irq_disable(struct s5p_aes_dev *dev, u32 flags) 842 { 843 SSS_WRITE(dev, FCINTENCLR, flags); 844 } 845 846 /** 847 * s5p_hash_irq_enable() - enable irq signals 848 * @dev: secss device 849 * @flags: bitfield with irq's to be enabled 850 */ 851 static void s5p_hash_irq_enable(struct s5p_aes_dev *dev, int flags) 852 { 853 SSS_WRITE(dev, FCINTENSET, flags); 854 } 855 856 /** 857 * s5p_hash_set_flow() - set flow inside SecSS AES/DES with/without HASH 858 * @dev: secss device 859 * @hashflow: HASH stream flow with/without crypto AES/DES 860 */ 861 static void s5p_hash_set_flow(struct s5p_aes_dev *dev, u32 hashflow) 862 { 863 unsigned long flags; 864 u32 flow; 865 866 spin_lock_irqsave(&dev->lock, flags); 867 868 flow = SSS_READ(dev, FCFIFOCTRL); 869 flow &= ~SSS_HASHIN_MASK; 870 flow |= hashflow; 871 SSS_WRITE(dev, FCFIFOCTRL, flow); 872 873 spin_unlock_irqrestore(&dev->lock, flags); 874 } 875 876 /** 877 * s5p_ahash_dma_init() - enable DMA and set HASH flow inside SecSS 878 * @dev: secss device 879 * @hashflow: HASH stream flow with/without AES/DES 880 * 881 * flush HASH DMA and enable DMA, set HASH stream flow inside SecSS HW, 882 * enable HASH irq's HRDMA, HDONE, HPART 883 */ 884 static void s5p_ahash_dma_init(struct s5p_aes_dev *dev, u32 hashflow) 885 { 886 s5p_hash_irq_disable(dev, SSS_FCINTENCLR_HRDMAINTENCLR | 887 SSS_FCINTENCLR_HDONEINTENCLR | 888 SSS_FCINTENCLR_HPARTINTENCLR); 889 s5p_hash_dma_flush(dev); 890 891 s5p_hash_dma_enable(dev); 892 s5p_hash_set_flow(dev, hashflow & SSS_HASHIN_MASK); 893 s5p_hash_irq_enable(dev, SSS_FCINTENSET_HRDMAINTENSET | 894 SSS_FCINTENSET_HDONEINTENSET | 895 SSS_FCINTENSET_HPARTINTENSET); 896 } 897 898 /** 899 * s5p_hash_write_ctrl() - prepare HASH block in SecSS for processing 900 * @dd: secss device 901 * @length: length for request 902 * @final: true if final op 903 * 904 * Prepare SSS HASH block for processing bytes in DMA mode. If it is called 905 * after previous updates, fill up IV words. For final, calculate and set 906 * lengths for HASH so SecSS can finalize hash. For partial, set SSS HASH 907 * length as 2^63 so it will be never reached and set to zero prelow and 908 * prehigh. 909 * 910 * This function does not start DMA transfer. 911 */ 912 static void s5p_hash_write_ctrl(struct s5p_aes_dev *dd, size_t length, 913 bool final) 914 { 915 struct s5p_hash_reqctx *ctx = ahash_request_ctx(dd->hash_req); 916 u32 prelow, prehigh, low, high; 917 u32 configflags, swapflags; 918 u64 tmplen; 919 920 configflags = ctx->engine | SSS_HASH_INIT_BIT; 921 922 if (likely(ctx->digcnt)) { 923 s5p_hash_write_ctx_iv(dd, ctx); 924 configflags |= SSS_HASH_USER_IV_EN; 925 } 926 927 if (final) { 928 /* number of bytes for last part */ 929 low = length; 930 high = 0; 931 /* total number of bits prev hashed */ 932 tmplen = ctx->digcnt * 8; 933 prelow = (u32)tmplen; 934 prehigh = (u32)(tmplen >> 32); 935 } else { 936 prelow = 0; 937 prehigh = 0; 938 low = 0; 939 high = BIT(31); 940 } 941 942 swapflags = SSS_HASH_BYTESWAP_DI | SSS_HASH_BYTESWAP_DO | 943 SSS_HASH_BYTESWAP_IV | SSS_HASH_BYTESWAP_KEY; 944 945 s5p_hash_write(dd, SSS_REG_HASH_MSG_SIZE_LOW, low); 946 s5p_hash_write(dd, SSS_REG_HASH_MSG_SIZE_HIGH, high); 947 s5p_hash_write(dd, SSS_REG_HASH_PRE_MSG_SIZE_LOW, prelow); 948 s5p_hash_write(dd, SSS_REG_HASH_PRE_MSG_SIZE_HIGH, prehigh); 949 950 s5p_hash_write(dd, SSS_REG_HASH_CTRL_SWAP, swapflags); 951 s5p_hash_write(dd, SSS_REG_HASH_CTRL, configflags); 952 } 953 954 /** 955 * s5p_hash_xmit_dma() - start DMA hash processing 956 * @dd: secss device 957 * @length: length for request 958 * @final: true if final op 959 * 960 * Update digcnt here, as it is needed for finup/final op. 961 */ 962 static int s5p_hash_xmit_dma(struct s5p_aes_dev *dd, size_t length, 963 bool final) 964 { 965 struct s5p_hash_reqctx *ctx = ahash_request_ctx(dd->hash_req); 966 unsigned int cnt; 967 968 cnt = dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE); 969 if (!cnt) { 970 dev_err(dd->dev, "dma_map_sg error\n"); 971 ctx->error = true; 972 return -EINVAL; 973 } 974 975 set_bit(HASH_FLAGS_DMA_ACTIVE, &dd->hash_flags); 976 dd->hash_sg_iter = ctx->sg; 977 dd->hash_sg_cnt = cnt; 978 s5p_hash_write_ctrl(dd, length, final); 979 ctx->digcnt += length; 980 ctx->total -= length; 981 982 /* catch last interrupt */ 983 if (final) 984 set_bit(HASH_FLAGS_FINAL, &dd->hash_flags); 985 986 s5p_set_dma_hashdata(dd, dd->hash_sg_iter); /* DMA starts */ 987 988 return -EINPROGRESS; 989 } 990 991 /** 992 * s5p_hash_copy_sgs() - copy request's bytes into new buffer 993 * @ctx: request context 994 * @sg: source scatterlist request 995 * @new_len: number of bytes to process from sg 996 * 997 * Allocate new buffer, copy data for HASH into it. If there was xmit_buf 998 * filled, copy it first, then copy data from sg into it. Prepare one sgl[0] 999 * with allocated buffer. 1000 * 1001 * Set bit in dd->hash_flag so we can free it after irq ends processing. 1002 */ 1003 static int s5p_hash_copy_sgs(struct s5p_hash_reqctx *ctx, 1004 struct scatterlist *sg, unsigned int new_len) 1005 { 1006 unsigned int pages, len; 1007 void *buf; 1008 1009 len = new_len + ctx->bufcnt; 1010 pages = get_order(len); 1011 1012 buf = (void *)__get_free_pages(GFP_ATOMIC, pages); 1013 if (!buf) { 1014 dev_err(ctx->dd->dev, "alloc pages for unaligned case.\n"); 1015 ctx->error = true; 1016 return -ENOMEM; 1017 } 1018 1019 if (ctx->bufcnt) 1020 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt); 1021 1022 memcpy_from_sglist(buf + ctx->bufcnt, sg, ctx->skip, new_len); 1023 sg_init_table(ctx->sgl, 1); 1024 sg_set_buf(ctx->sgl, buf, len); 1025 ctx->sg = ctx->sgl; 1026 ctx->sg_len = 1; 1027 ctx->bufcnt = 0; 1028 ctx->skip = 0; 1029 set_bit(HASH_FLAGS_SGS_COPIED, &ctx->dd->hash_flags); 1030 1031 return 0; 1032 } 1033 1034 /** 1035 * s5p_hash_copy_sg_lists() - copy sg list and make fixes in copy 1036 * @ctx: request context 1037 * @sg: source scatterlist request 1038 * @new_len: number of bytes to process from sg 1039 * 1040 * Allocate new scatterlist table, copy data for HASH into it. If there was 1041 * xmit_buf filled, prepare it first, then copy page, length and offset from 1042 * source sg into it, adjusting begin and/or end for skip offset and 1043 * hash_later value. 1044 * 1045 * Resulting sg table will be assigned to ctx->sg. Set flag so we can free 1046 * it after irq ends processing. 1047 */ 1048 static int s5p_hash_copy_sg_lists(struct s5p_hash_reqctx *ctx, 1049 struct scatterlist *sg, unsigned int new_len) 1050 { 1051 unsigned int skip = ctx->skip, n = sg_nents(sg); 1052 struct scatterlist *tmp; 1053 unsigned int len; 1054 1055 if (ctx->bufcnt) 1056 n++; 1057 1058 ctx->sg = kmalloc_objs(*sg, n); 1059 if (!ctx->sg) { 1060 ctx->error = true; 1061 return -ENOMEM; 1062 } 1063 1064 sg_init_table(ctx->sg, n); 1065 1066 tmp = ctx->sg; 1067 1068 ctx->sg_len = 0; 1069 1070 if (ctx->bufcnt) { 1071 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt); 1072 tmp = sg_next(tmp); 1073 ctx->sg_len++; 1074 } 1075 1076 while (sg && skip >= sg->length) { 1077 skip -= sg->length; 1078 sg = sg_next(sg); 1079 } 1080 1081 while (sg && new_len) { 1082 len = sg->length - skip; 1083 if (new_len < len) 1084 len = new_len; 1085 1086 new_len -= len; 1087 sg_set_page(tmp, sg_page(sg), len, sg->offset + skip); 1088 skip = 0; 1089 if (new_len <= 0) 1090 sg_mark_end(tmp); 1091 1092 tmp = sg_next(tmp); 1093 ctx->sg_len++; 1094 sg = sg_next(sg); 1095 } 1096 1097 set_bit(HASH_FLAGS_SGS_ALLOCED, &ctx->dd->hash_flags); 1098 1099 return 0; 1100 } 1101 1102 /** 1103 * s5p_hash_prepare_sgs() - prepare sg for processing 1104 * @ctx: request context 1105 * @sg: source scatterlist request 1106 * @new_len: number of bytes to process from sg 1107 * @final: final flag 1108 * 1109 * Check two conditions: (1) if buffers in sg have len aligned data, and (2) 1110 * sg table have good aligned elements (list_ok). If one of this checks fails, 1111 * then either (1) allocates new buffer for data with s5p_hash_copy_sgs, copy 1112 * data into this buffer and prepare request in sgl, or (2) allocates new sg 1113 * table and prepare sg elements. 1114 * 1115 * For digest or finup all conditions can be good, and we may not need any 1116 * fixes. 1117 */ 1118 static int s5p_hash_prepare_sgs(struct s5p_hash_reqctx *ctx, 1119 struct scatterlist *sg, 1120 unsigned int new_len, bool final) 1121 { 1122 unsigned int skip = ctx->skip, nbytes = new_len, n = 0; 1123 bool aligned = true, list_ok = true; 1124 struct scatterlist *sg_tmp = sg; 1125 1126 if (!sg || !sg->length || !new_len) 1127 return 0; 1128 1129 if (skip || !final) 1130 list_ok = false; 1131 1132 while (nbytes > 0 && sg_tmp) { 1133 n++; 1134 if (skip >= sg_tmp->length) { 1135 skip -= sg_tmp->length; 1136 if (!sg_tmp->length) { 1137 aligned = false; 1138 break; 1139 } 1140 } else { 1141 if (!IS_ALIGNED(sg_tmp->length - skip, BUFLEN)) { 1142 aligned = false; 1143 break; 1144 } 1145 1146 if (nbytes < sg_tmp->length - skip) { 1147 list_ok = false; 1148 break; 1149 } 1150 1151 nbytes -= sg_tmp->length - skip; 1152 skip = 0; 1153 } 1154 1155 sg_tmp = sg_next(sg_tmp); 1156 } 1157 1158 if (!aligned) 1159 return s5p_hash_copy_sgs(ctx, sg, new_len); 1160 else if (!list_ok) 1161 return s5p_hash_copy_sg_lists(ctx, sg, new_len); 1162 1163 /* 1164 * Have aligned data from previous operation and/or current 1165 * Note: will enter here only if (digest or finup) and aligned 1166 */ 1167 if (ctx->bufcnt) { 1168 ctx->sg_len = n; 1169 sg_init_table(ctx->sgl, 2); 1170 sg_set_buf(ctx->sgl, ctx->dd->xmit_buf, ctx->bufcnt); 1171 sg_chain(ctx->sgl, 2, sg); 1172 ctx->sg = ctx->sgl; 1173 ctx->sg_len++; 1174 } else { 1175 ctx->sg = sg; 1176 ctx->sg_len = n; 1177 } 1178 1179 return 0; 1180 } 1181 1182 /** 1183 * s5p_hash_prepare_request() - prepare request for processing 1184 * @req: AHASH request 1185 * @update: true if UPDATE op 1186 * 1187 * Note 1: we can have update flag _and_ final flag at the same time. 1188 * Note 2: we enter here when digcnt > BUFLEN (=HASH_BLOCK_SIZE) or 1189 * either req->nbytes or ctx->bufcnt + req->nbytes is > BUFLEN or 1190 * we have final op 1191 */ 1192 static int s5p_hash_prepare_request(struct ahash_request *req, bool update) 1193 { 1194 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1195 bool final = ctx->finup; 1196 int xmit_len, hash_later, nbytes; 1197 int ret; 1198 1199 if (update) 1200 nbytes = req->nbytes; 1201 else 1202 nbytes = 0; 1203 1204 ctx->total = nbytes + ctx->bufcnt; 1205 if (!ctx->total) 1206 return 0; 1207 1208 if (nbytes && (!IS_ALIGNED(ctx->bufcnt, BUFLEN))) { 1209 /* bytes left from previous request, so fill up to BUFLEN */ 1210 int len = BUFLEN - ctx->bufcnt % BUFLEN; 1211 1212 if (len > nbytes) 1213 len = nbytes; 1214 1215 memcpy_from_sglist(ctx->buffer + ctx->bufcnt, req->src, 0, len); 1216 ctx->bufcnt += len; 1217 nbytes -= len; 1218 ctx->skip = len; 1219 } else { 1220 ctx->skip = 0; 1221 } 1222 1223 if (ctx->bufcnt) 1224 memcpy(ctx->dd->xmit_buf, ctx->buffer, ctx->bufcnt); 1225 1226 xmit_len = ctx->total; 1227 if (final) { 1228 hash_later = 0; 1229 } else { 1230 if (IS_ALIGNED(xmit_len, BUFLEN)) 1231 xmit_len -= BUFLEN; 1232 else 1233 xmit_len -= xmit_len & (BUFLEN - 1); 1234 1235 hash_later = ctx->total - xmit_len; 1236 /* copy hash_later bytes from end of req->src */ 1237 /* previous bytes are in xmit_buf, so no overwrite */ 1238 memcpy_from_sglist(ctx->buffer, req->src, 1239 req->nbytes - hash_later, hash_later); 1240 } 1241 1242 if (xmit_len > BUFLEN) { 1243 ret = s5p_hash_prepare_sgs(ctx, req->src, nbytes - hash_later, 1244 final); 1245 if (ret) 1246 return ret; 1247 } else { 1248 /* have buffered data only */ 1249 if (unlikely(!ctx->bufcnt)) { 1250 /* first update didn't fill up buffer */ 1251 memcpy_from_sglist(ctx->dd->xmit_buf, req->src, 1252 0, xmit_len); 1253 } 1254 1255 sg_init_table(ctx->sgl, 1); 1256 sg_set_buf(ctx->sgl, ctx->dd->xmit_buf, xmit_len); 1257 1258 ctx->sg = ctx->sgl; 1259 ctx->sg_len = 1; 1260 } 1261 1262 ctx->bufcnt = hash_later; 1263 if (!final) 1264 ctx->total = xmit_len; 1265 1266 return 0; 1267 } 1268 1269 /** 1270 * s5p_hash_update_dma_stop() - unmap DMA 1271 * @dd: secss device 1272 * 1273 * Unmap scatterlist ctx->sg. 1274 */ 1275 static void s5p_hash_update_dma_stop(struct s5p_aes_dev *dd) 1276 { 1277 const struct s5p_hash_reqctx *ctx = ahash_request_ctx(dd->hash_req); 1278 1279 dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE); 1280 clear_bit(HASH_FLAGS_DMA_ACTIVE, &dd->hash_flags); 1281 } 1282 1283 /** 1284 * s5p_hash_finish() - copy calculated digest to crypto layer 1285 * @req: AHASH request 1286 */ 1287 static void s5p_hash_finish(struct ahash_request *req) 1288 { 1289 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1290 struct s5p_aes_dev *dd = ctx->dd; 1291 1292 if (ctx->digcnt) 1293 s5p_hash_copy_result(req); 1294 1295 dev_dbg(dd->dev, "hash_finish digcnt: %lld\n", ctx->digcnt); 1296 } 1297 1298 /** 1299 * s5p_hash_finish_req() - finish request 1300 * @req: AHASH request 1301 * @err: error 1302 */ 1303 static void s5p_hash_finish_req(struct ahash_request *req, int err) 1304 { 1305 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1306 struct s5p_aes_dev *dd = ctx->dd; 1307 unsigned long flags; 1308 1309 if (test_bit(HASH_FLAGS_SGS_COPIED, &dd->hash_flags)) 1310 free_pages((unsigned long)sg_virt(ctx->sg), 1311 get_order(ctx->sg->length)); 1312 1313 if (test_bit(HASH_FLAGS_SGS_ALLOCED, &dd->hash_flags)) 1314 kfree(ctx->sg); 1315 1316 ctx->sg = NULL; 1317 dd->hash_flags &= ~(BIT(HASH_FLAGS_SGS_ALLOCED) | 1318 BIT(HASH_FLAGS_SGS_COPIED)); 1319 1320 if (!err && !ctx->error) { 1321 s5p_hash_read_msg(req); 1322 if (test_bit(HASH_FLAGS_FINAL, &dd->hash_flags)) 1323 s5p_hash_finish(req); 1324 } else { 1325 ctx->error = true; 1326 } 1327 1328 spin_lock_irqsave(&dd->hash_lock, flags); 1329 dd->hash_flags &= ~(BIT(HASH_FLAGS_BUSY) | BIT(HASH_FLAGS_FINAL) | 1330 BIT(HASH_FLAGS_DMA_READY) | 1331 BIT(HASH_FLAGS_OUTPUT_READY)); 1332 spin_unlock_irqrestore(&dd->hash_lock, flags); 1333 1334 if (req->base.complete) 1335 ahash_request_complete(req, err); 1336 } 1337 1338 /** 1339 * s5p_hash_handle_queue() - handle hash queue 1340 * @dd: device s5p_aes_dev 1341 * @req: AHASH request 1342 * 1343 * If req!=NULL enqueue it on dd->queue, if FLAGS_BUSY is not set on the 1344 * device then processes the first request from the dd->queue 1345 * 1346 * Returns: see s5p_hash_final below. 1347 */ 1348 static int s5p_hash_handle_queue(struct s5p_aes_dev *dd, 1349 struct ahash_request *req) 1350 { 1351 struct crypto_async_request *async_req, *backlog; 1352 struct s5p_hash_reqctx *ctx; 1353 unsigned long flags; 1354 int err = 0, ret = 0; 1355 1356 retry: 1357 spin_lock_irqsave(&dd->hash_lock, flags); 1358 if (req) 1359 ret = ahash_enqueue_request(&dd->hash_queue, req); 1360 1361 if (test_bit(HASH_FLAGS_BUSY, &dd->hash_flags)) { 1362 spin_unlock_irqrestore(&dd->hash_lock, flags); 1363 return ret; 1364 } 1365 1366 backlog = crypto_get_backlog(&dd->hash_queue); 1367 async_req = crypto_dequeue_request(&dd->hash_queue); 1368 if (async_req) 1369 set_bit(HASH_FLAGS_BUSY, &dd->hash_flags); 1370 1371 spin_unlock_irqrestore(&dd->hash_lock, flags); 1372 1373 if (!async_req) 1374 return ret; 1375 1376 if (backlog) 1377 crypto_request_complete(backlog, -EINPROGRESS); 1378 1379 req = ahash_request_cast(async_req); 1380 dd->hash_req = req; 1381 ctx = ahash_request_ctx(req); 1382 1383 err = s5p_hash_prepare_request(req, ctx->op_update); 1384 if (err || !ctx->total) 1385 goto out; 1386 1387 dev_dbg(dd->dev, "handling new req, op_update: %u, nbytes: %d\n", 1388 ctx->op_update, req->nbytes); 1389 1390 s5p_ahash_dma_init(dd, SSS_HASHIN_INDEPENDENT); 1391 if (ctx->digcnt) 1392 s5p_hash_write_iv(req); /* restore hash IV */ 1393 1394 if (ctx->op_update) { /* HASH_OP_UPDATE */ 1395 err = s5p_hash_xmit_dma(dd, ctx->total, ctx->finup); 1396 if (err != -EINPROGRESS && ctx->finup && !ctx->error) 1397 /* no final() after finup() */ 1398 err = s5p_hash_xmit_dma(dd, ctx->total, true); 1399 } else { /* HASH_OP_FINAL */ 1400 err = s5p_hash_xmit_dma(dd, ctx->total, true); 1401 } 1402 out: 1403 if (err != -EINPROGRESS) { 1404 /* hash_tasklet_cb will not finish it, so do it here */ 1405 s5p_hash_finish_req(req, err); 1406 req = NULL; 1407 1408 /* 1409 * Execute next request immediately if there is anything 1410 * in queue. 1411 */ 1412 goto retry; 1413 } 1414 1415 return ret; 1416 } 1417 1418 /** 1419 * s5p_hash_tasklet_cb() - hash tasklet 1420 * @data: ptr to s5p_aes_dev 1421 */ 1422 static void s5p_hash_tasklet_cb(unsigned long data) 1423 { 1424 struct s5p_aes_dev *dd = (struct s5p_aes_dev *)data; 1425 1426 if (!test_bit(HASH_FLAGS_BUSY, &dd->hash_flags)) { 1427 s5p_hash_handle_queue(dd, NULL); 1428 return; 1429 } 1430 1431 if (test_bit(HASH_FLAGS_DMA_READY, &dd->hash_flags)) { 1432 if (test_and_clear_bit(HASH_FLAGS_DMA_ACTIVE, 1433 &dd->hash_flags)) { 1434 s5p_hash_update_dma_stop(dd); 1435 } 1436 1437 if (test_and_clear_bit(HASH_FLAGS_OUTPUT_READY, 1438 &dd->hash_flags)) { 1439 /* hash or semi-hash ready */ 1440 clear_bit(HASH_FLAGS_DMA_READY, &dd->hash_flags); 1441 goto finish; 1442 } 1443 } 1444 1445 return; 1446 1447 finish: 1448 /* finish current request */ 1449 s5p_hash_finish_req(dd->hash_req, 0); 1450 1451 /* If we are not busy, process next req */ 1452 if (!test_bit(HASH_FLAGS_BUSY, &dd->hash_flags)) 1453 s5p_hash_handle_queue(dd, NULL); 1454 } 1455 1456 /** 1457 * s5p_hash_enqueue() - enqueue request 1458 * @req: AHASH request 1459 * @op: operation UPDATE (true) or FINAL (false) 1460 * 1461 * Returns: see s5p_hash_final below. 1462 */ 1463 static int s5p_hash_enqueue(struct ahash_request *req, bool op) 1464 { 1465 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1466 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 1467 1468 ctx->op_update = op; 1469 1470 return s5p_hash_handle_queue(tctx->dd, req); 1471 } 1472 1473 /** 1474 * s5p_hash_update() - process the hash input data 1475 * @req: AHASH request 1476 * 1477 * If request will fit in buffer, copy it and return immediately 1478 * else enqueue it with OP_UPDATE. 1479 * 1480 * Returns: see s5p_hash_final below. 1481 */ 1482 static int s5p_hash_update(struct ahash_request *req) 1483 { 1484 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1485 1486 if (!req->nbytes) 1487 return 0; 1488 1489 if (ctx->bufcnt + req->nbytes <= BUFLEN) { 1490 memcpy_from_sglist(ctx->buffer + ctx->bufcnt, req->src, 1491 0, req->nbytes); 1492 ctx->bufcnt += req->nbytes; 1493 return 0; 1494 } 1495 1496 return s5p_hash_enqueue(req, true); /* HASH_OP_UPDATE */ 1497 } 1498 1499 /** 1500 * s5p_hash_final() - close up hash and calculate digest 1501 * @req: AHASH request 1502 * 1503 * Note: in final req->src do not have any data, and req->nbytes can be 1504 * non-zero. 1505 * 1506 * If there were no input data processed yet and the buffered hash data is 1507 * less than BUFLEN (64) then calculate the final hash immediately by using 1508 * SW algorithm fallback. 1509 * 1510 * Otherwise enqueues the current AHASH request with OP_FINAL operation op 1511 * and finalize hash message in HW. Note that if digcnt!=0 then there were 1512 * previous update op, so there are always some buffered bytes in ctx->buffer, 1513 * which means that ctx->bufcnt!=0 1514 * 1515 * Returns: 1516 * 0 if the request has been processed immediately, 1517 * -EINPROGRESS if the operation has been queued for later execution or is set 1518 * to processing by HW, 1519 * -EBUSY if queue is full and request should be resubmitted later, 1520 * other negative values denotes an error. 1521 */ 1522 static int s5p_hash_final(struct ahash_request *req) 1523 { 1524 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1525 1526 ctx->finup = true; 1527 if (ctx->error) 1528 return -EINVAL; /* uncompleted hash is not needed */ 1529 1530 if (!ctx->digcnt && ctx->bufcnt < BUFLEN) { 1531 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 1532 1533 return crypto_shash_tfm_digest(tctx->fallback, ctx->buffer, 1534 ctx->bufcnt, req->result); 1535 } 1536 1537 return s5p_hash_enqueue(req, false); /* HASH_OP_FINAL */ 1538 } 1539 1540 /** 1541 * s5p_hash_finup() - process last req->src and calculate digest 1542 * @req: AHASH request containing the last update data 1543 * 1544 * Return values: see s5p_hash_final above. 1545 */ 1546 static int s5p_hash_finup(struct ahash_request *req) 1547 { 1548 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1549 int err1, err2; 1550 1551 ctx->finup = true; 1552 1553 err1 = s5p_hash_update(req); 1554 if (err1 == -EINPROGRESS || err1 == -EBUSY) 1555 return err1; 1556 1557 /* 1558 * final() has to be always called to cleanup resources even if 1559 * update() failed, except EINPROGRESS or calculate digest for small 1560 * size 1561 */ 1562 err2 = s5p_hash_final(req); 1563 1564 return err1 ?: err2; 1565 } 1566 1567 /** 1568 * s5p_hash_init() - initialize AHASH request contex 1569 * @req: AHASH request 1570 * 1571 * Init async hash request context. 1572 */ 1573 static int s5p_hash_init(struct ahash_request *req) 1574 { 1575 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1576 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 1577 struct s5p_hash_ctx *tctx = crypto_ahash_ctx(tfm); 1578 1579 ctx->dd = tctx->dd; 1580 ctx->error = false; 1581 ctx->finup = false; 1582 ctx->bufcnt = 0; 1583 ctx->digcnt = 0; 1584 ctx->total = 0; 1585 ctx->skip = 0; 1586 1587 dev_dbg(tctx->dd->dev, "init: digest size: %d\n", 1588 crypto_ahash_digestsize(tfm)); 1589 1590 switch (crypto_ahash_digestsize(tfm)) { 1591 case MD5_DIGEST_SIZE: 1592 ctx->engine = SSS_HASH_ENGINE_MD5; 1593 ctx->nregs = HASH_MD5_MAX_REG; 1594 break; 1595 case SHA1_DIGEST_SIZE: 1596 ctx->engine = SSS_HASH_ENGINE_SHA1; 1597 ctx->nregs = HASH_SHA1_MAX_REG; 1598 break; 1599 case SHA256_DIGEST_SIZE: 1600 ctx->engine = SSS_HASH_ENGINE_SHA256; 1601 ctx->nregs = HASH_SHA256_MAX_REG; 1602 break; 1603 default: 1604 ctx->error = true; 1605 return -EINVAL; 1606 } 1607 1608 return 0; 1609 } 1610 1611 /** 1612 * s5p_hash_digest - calculate digest from req->src 1613 * @req: AHASH request 1614 * 1615 * Return values: see s5p_hash_final above. 1616 */ 1617 static int s5p_hash_digest(struct ahash_request *req) 1618 { 1619 return s5p_hash_init(req) ?: s5p_hash_finup(req); 1620 } 1621 1622 /** 1623 * s5p_hash_cra_init_alg - init crypto alg transformation 1624 * @tfm: crypto transformation 1625 */ 1626 static int s5p_hash_cra_init_alg(struct crypto_tfm *tfm) 1627 { 1628 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(tfm); 1629 const char *alg_name = crypto_tfm_alg_name(tfm); 1630 1631 tctx->dd = s5p_dev; 1632 /* Allocate a fallback and abort if it failed. */ 1633 tctx->fallback = crypto_alloc_shash(alg_name, 0, 1634 CRYPTO_ALG_NEED_FALLBACK); 1635 if (IS_ERR(tctx->fallback)) { 1636 pr_err("fallback alloc fails for '%s'\n", alg_name); 1637 return PTR_ERR(tctx->fallback); 1638 } 1639 1640 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), 1641 sizeof(struct s5p_hash_reqctx) + BUFLEN); 1642 1643 return 0; 1644 } 1645 1646 /** 1647 * s5p_hash_cra_init - init crypto tfm 1648 * @tfm: crypto transformation 1649 */ 1650 static int s5p_hash_cra_init(struct crypto_tfm *tfm) 1651 { 1652 return s5p_hash_cra_init_alg(tfm); 1653 } 1654 1655 /** 1656 * s5p_hash_cra_exit - exit crypto tfm 1657 * @tfm: crypto transformation 1658 * 1659 * free allocated fallback 1660 */ 1661 static void s5p_hash_cra_exit(struct crypto_tfm *tfm) 1662 { 1663 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(tfm); 1664 1665 crypto_free_shash(tctx->fallback); 1666 tctx->fallback = NULL; 1667 } 1668 1669 /** 1670 * s5p_hash_export - export hash state 1671 * @req: AHASH request 1672 * @out: buffer for exported state 1673 */ 1674 static int s5p_hash_export(struct ahash_request *req, void *out) 1675 { 1676 const struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1677 1678 memcpy(out, ctx, sizeof(*ctx) + ctx->bufcnt); 1679 1680 return 0; 1681 } 1682 1683 /** 1684 * s5p_hash_import - import hash state 1685 * @req: AHASH request 1686 * @in: buffer with state to be imported from 1687 */ 1688 static int s5p_hash_import(struct ahash_request *req, const void *in) 1689 { 1690 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1691 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 1692 struct s5p_hash_ctx *tctx = crypto_ahash_ctx(tfm); 1693 const struct s5p_hash_reqctx *ctx_in = in; 1694 1695 memcpy(ctx, in, sizeof(*ctx) + BUFLEN); 1696 if (ctx_in->bufcnt > BUFLEN) { 1697 ctx->error = true; 1698 return -EINVAL; 1699 } 1700 1701 ctx->dd = tctx->dd; 1702 ctx->error = false; 1703 1704 return 0; 1705 } 1706 1707 static struct ahash_alg algs_sha1_md5_sha256[] = { 1708 { 1709 .init = s5p_hash_init, 1710 .update = s5p_hash_update, 1711 .final = s5p_hash_final, 1712 .finup = s5p_hash_finup, 1713 .digest = s5p_hash_digest, 1714 .export = s5p_hash_export, 1715 .import = s5p_hash_import, 1716 .halg.statesize = sizeof(struct s5p_hash_reqctx) + BUFLEN, 1717 .halg.digestsize = SHA1_DIGEST_SIZE, 1718 .halg.base = { 1719 .cra_name = "sha1", 1720 .cra_driver_name = "exynos-sha1", 1721 .cra_priority = 100, 1722 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1723 CRYPTO_ALG_ASYNC | 1724 CRYPTO_ALG_NEED_FALLBACK, 1725 .cra_blocksize = HASH_BLOCK_SIZE, 1726 .cra_ctxsize = sizeof(struct s5p_hash_ctx), 1727 .cra_module = THIS_MODULE, 1728 .cra_init = s5p_hash_cra_init, 1729 .cra_exit = s5p_hash_cra_exit, 1730 } 1731 }, 1732 { 1733 .init = s5p_hash_init, 1734 .update = s5p_hash_update, 1735 .final = s5p_hash_final, 1736 .finup = s5p_hash_finup, 1737 .digest = s5p_hash_digest, 1738 .export = s5p_hash_export, 1739 .import = s5p_hash_import, 1740 .halg.statesize = sizeof(struct s5p_hash_reqctx) + BUFLEN, 1741 .halg.digestsize = MD5_DIGEST_SIZE, 1742 .halg.base = { 1743 .cra_name = "md5", 1744 .cra_driver_name = "exynos-md5", 1745 .cra_priority = 100, 1746 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1747 CRYPTO_ALG_ASYNC | 1748 CRYPTO_ALG_NEED_FALLBACK, 1749 .cra_blocksize = HASH_BLOCK_SIZE, 1750 .cra_ctxsize = sizeof(struct s5p_hash_ctx), 1751 .cra_module = THIS_MODULE, 1752 .cra_init = s5p_hash_cra_init, 1753 .cra_exit = s5p_hash_cra_exit, 1754 } 1755 }, 1756 { 1757 .init = s5p_hash_init, 1758 .update = s5p_hash_update, 1759 .final = s5p_hash_final, 1760 .finup = s5p_hash_finup, 1761 .digest = s5p_hash_digest, 1762 .export = s5p_hash_export, 1763 .import = s5p_hash_import, 1764 .halg.statesize = sizeof(struct s5p_hash_reqctx) + BUFLEN, 1765 .halg.digestsize = SHA256_DIGEST_SIZE, 1766 .halg.base = { 1767 .cra_name = "sha256", 1768 .cra_driver_name = "exynos-sha256", 1769 .cra_priority = 100, 1770 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1771 CRYPTO_ALG_ASYNC | 1772 CRYPTO_ALG_NEED_FALLBACK, 1773 .cra_blocksize = HASH_BLOCK_SIZE, 1774 .cra_ctxsize = sizeof(struct s5p_hash_ctx), 1775 .cra_module = THIS_MODULE, 1776 .cra_init = s5p_hash_cra_init, 1777 .cra_exit = s5p_hash_cra_exit, 1778 } 1779 } 1780 1781 }; 1782 1783 static void s5p_set_aes(struct s5p_aes_dev *dev, 1784 const u8 *key, const u8 *iv, const u8 *ctr, 1785 unsigned int keylen) 1786 { 1787 void __iomem *keystart; 1788 1789 if (iv) 1790 memcpy_toio(dev->aes_ioaddr + SSS_REG_AES_IV_DATA(0), iv, 1791 AES_BLOCK_SIZE); 1792 1793 if (ctr) 1794 memcpy_toio(dev->aes_ioaddr + SSS_REG_AES_CNT_DATA(0), ctr, 1795 AES_BLOCK_SIZE); 1796 1797 if (keylen == AES_KEYSIZE_256) 1798 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(0); 1799 else if (keylen == AES_KEYSIZE_192) 1800 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(2); 1801 else 1802 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(4); 1803 1804 memcpy_toio(keystart, key, keylen); 1805 } 1806 1807 static bool s5p_is_sg_aligned(struct scatterlist *sg) 1808 { 1809 while (sg) { 1810 if (!IS_ALIGNED(sg->length, AES_BLOCK_SIZE)) 1811 return false; 1812 sg = sg_next(sg); 1813 } 1814 1815 return true; 1816 } 1817 1818 static int s5p_set_indata_start(struct s5p_aes_dev *dev, 1819 struct skcipher_request *req) 1820 { 1821 struct scatterlist *sg; 1822 int err; 1823 1824 dev->sg_src_cpy = NULL; 1825 sg = req->src; 1826 if (!s5p_is_sg_aligned(sg)) { 1827 dev_dbg(dev->dev, 1828 "At least one unaligned source scatter list, making a copy\n"); 1829 err = s5p_make_sg_cpy(dev, sg, &dev->sg_src_cpy); 1830 if (err) 1831 return err; 1832 1833 sg = dev->sg_src_cpy; 1834 } 1835 1836 err = s5p_set_indata(dev, sg); 1837 if (err) { 1838 s5p_free_sg_cpy(dev, &dev->sg_src_cpy); 1839 return err; 1840 } 1841 1842 return 0; 1843 } 1844 1845 static int s5p_set_outdata_start(struct s5p_aes_dev *dev, 1846 struct skcipher_request *req) 1847 { 1848 struct scatterlist *sg; 1849 int err; 1850 1851 dev->sg_dst_cpy = NULL; 1852 sg = req->dst; 1853 if (!s5p_is_sg_aligned(sg)) { 1854 dev_dbg(dev->dev, 1855 "At least one unaligned dest scatter list, making a copy\n"); 1856 err = s5p_make_sg_cpy(dev, sg, &dev->sg_dst_cpy); 1857 if (err) 1858 return err; 1859 1860 sg = dev->sg_dst_cpy; 1861 } 1862 1863 err = s5p_set_outdata(dev, sg); 1864 if (err) { 1865 s5p_free_sg_cpy(dev, &dev->sg_dst_cpy); 1866 return err; 1867 } 1868 1869 return 0; 1870 } 1871 1872 static void s5p_aes_crypt_start(struct s5p_aes_dev *dev, unsigned long mode) 1873 { 1874 struct skcipher_request *req = dev->req; 1875 u32 aes_control; 1876 unsigned long flags; 1877 int err; 1878 u8 *iv, *ctr; 1879 1880 /* This sets bit [13:12] to 00, which selects 128-bit counter */ 1881 aes_control = SSS_AES_KEY_CHANGE_MODE; 1882 if (mode & FLAGS_AES_DECRYPT) 1883 aes_control |= SSS_AES_MODE_DECRYPT; 1884 1885 if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CBC) { 1886 aes_control |= SSS_AES_CHAIN_MODE_CBC; 1887 iv = req->iv; 1888 ctr = NULL; 1889 } else if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CTR) { 1890 aes_control |= SSS_AES_CHAIN_MODE_CTR; 1891 iv = NULL; 1892 ctr = req->iv; 1893 } else { 1894 iv = NULL; /* AES_ECB */ 1895 ctr = NULL; 1896 } 1897 1898 if (dev->ctx->keylen == AES_KEYSIZE_192) 1899 aes_control |= SSS_AES_KEY_SIZE_192; 1900 else if (dev->ctx->keylen == AES_KEYSIZE_256) 1901 aes_control |= SSS_AES_KEY_SIZE_256; 1902 1903 aes_control |= SSS_AES_FIFO_MODE; 1904 1905 /* as a variant it is possible to use byte swapping on DMA side */ 1906 aes_control |= SSS_AES_BYTESWAP_DI 1907 | SSS_AES_BYTESWAP_DO 1908 | SSS_AES_BYTESWAP_IV 1909 | SSS_AES_BYTESWAP_KEY 1910 | SSS_AES_BYTESWAP_CNT; 1911 1912 spin_lock_irqsave(&dev->lock, flags); 1913 1914 SSS_WRITE(dev, FCINTENCLR, 1915 SSS_FCINTENCLR_BTDMAINTENCLR | SSS_FCINTENCLR_BRDMAINTENCLR); 1916 SSS_WRITE(dev, FCFIFOCTRL, 0x00); 1917 1918 err = s5p_set_indata_start(dev, req); 1919 if (err) 1920 goto indata_error; 1921 1922 err = s5p_set_outdata_start(dev, req); 1923 if (err) 1924 goto outdata_error; 1925 1926 SSS_AES_WRITE(dev, AES_CONTROL, aes_control); 1927 s5p_set_aes(dev, dev->ctx->aes_key, iv, ctr, dev->ctx->keylen); 1928 1929 s5p_set_dma_indata(dev, dev->sg_src); 1930 s5p_set_dma_outdata(dev, dev->sg_dst); 1931 1932 SSS_WRITE(dev, FCINTENSET, 1933 SSS_FCINTENSET_BTDMAINTENSET | SSS_FCINTENSET_BRDMAINTENSET); 1934 1935 spin_unlock_irqrestore(&dev->lock, flags); 1936 1937 return; 1938 1939 outdata_error: 1940 s5p_unset_indata(dev); 1941 1942 indata_error: 1943 s5p_sg_done(dev); 1944 dev->busy = false; 1945 spin_unlock_irqrestore(&dev->lock, flags); 1946 s5p_aes_complete(req, err); 1947 } 1948 1949 static void s5p_tasklet_cb(unsigned long data) 1950 { 1951 struct s5p_aes_dev *dev = (struct s5p_aes_dev *)data; 1952 struct crypto_async_request *async_req, *backlog; 1953 struct s5p_aes_reqctx *reqctx; 1954 unsigned long flags; 1955 1956 spin_lock_irqsave(&dev->lock, flags); 1957 backlog = crypto_get_backlog(&dev->queue); 1958 async_req = crypto_dequeue_request(&dev->queue); 1959 1960 if (!async_req) { 1961 dev->busy = false; 1962 spin_unlock_irqrestore(&dev->lock, flags); 1963 return; 1964 } 1965 spin_unlock_irqrestore(&dev->lock, flags); 1966 1967 if (backlog) 1968 crypto_request_complete(backlog, -EINPROGRESS); 1969 1970 dev->req = skcipher_request_cast(async_req); 1971 dev->ctx = crypto_tfm_ctx(dev->req->base.tfm); 1972 reqctx = skcipher_request_ctx(dev->req); 1973 1974 s5p_aes_crypt_start(dev, reqctx->mode); 1975 } 1976 1977 static int s5p_aes_handle_req(struct s5p_aes_dev *dev, 1978 struct skcipher_request *req) 1979 { 1980 unsigned long flags; 1981 int err; 1982 1983 spin_lock_irqsave(&dev->lock, flags); 1984 err = crypto_enqueue_request(&dev->queue, &req->base); 1985 if (dev->busy) { 1986 spin_unlock_irqrestore(&dev->lock, flags); 1987 return err; 1988 } 1989 dev->busy = true; 1990 1991 spin_unlock_irqrestore(&dev->lock, flags); 1992 1993 tasklet_schedule(&dev->tasklet); 1994 1995 return err; 1996 } 1997 1998 static int s5p_aes_crypt(struct skcipher_request *req, unsigned long mode) 1999 { 2000 struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); 2001 struct s5p_aes_reqctx *reqctx = skcipher_request_ctx(req); 2002 struct s5p_aes_ctx *ctx = crypto_skcipher_ctx(tfm); 2003 struct s5p_aes_dev *dev = ctx->dev; 2004 2005 if (!req->cryptlen) 2006 return 0; 2007 2008 if (!IS_ALIGNED(req->cryptlen, AES_BLOCK_SIZE) && 2009 ((mode & FLAGS_AES_MODE_MASK) != FLAGS_AES_CTR)) { 2010 dev_dbg(dev->dev, "request size is not exact amount of AES blocks\n"); 2011 return -EINVAL; 2012 } 2013 2014 reqctx->mode = mode; 2015 2016 return s5p_aes_handle_req(dev, req); 2017 } 2018 2019 static int s5p_aes_setkey(struct crypto_skcipher *cipher, 2020 const u8 *key, unsigned int keylen) 2021 { 2022 struct crypto_tfm *tfm = crypto_skcipher_tfm(cipher); 2023 struct s5p_aes_ctx *ctx = crypto_tfm_ctx(tfm); 2024 2025 if (keylen != AES_KEYSIZE_128 && 2026 keylen != AES_KEYSIZE_192 && 2027 keylen != AES_KEYSIZE_256) 2028 return -EINVAL; 2029 2030 memcpy(ctx->aes_key, key, keylen); 2031 ctx->keylen = keylen; 2032 2033 return 0; 2034 } 2035 2036 static int s5p_aes_ecb_encrypt(struct skcipher_request *req) 2037 { 2038 return s5p_aes_crypt(req, 0); 2039 } 2040 2041 static int s5p_aes_ecb_decrypt(struct skcipher_request *req) 2042 { 2043 return s5p_aes_crypt(req, FLAGS_AES_DECRYPT); 2044 } 2045 2046 static int s5p_aes_cbc_encrypt(struct skcipher_request *req) 2047 { 2048 return s5p_aes_crypt(req, FLAGS_AES_CBC); 2049 } 2050 2051 static int s5p_aes_cbc_decrypt(struct skcipher_request *req) 2052 { 2053 return s5p_aes_crypt(req, FLAGS_AES_DECRYPT | FLAGS_AES_CBC); 2054 } 2055 2056 static int s5p_aes_ctr_crypt(struct skcipher_request *req) 2057 { 2058 return s5p_aes_crypt(req, FLAGS_AES_CTR); 2059 } 2060 2061 static int s5p_aes_init_tfm(struct crypto_skcipher *tfm) 2062 { 2063 struct s5p_aes_ctx *ctx = crypto_skcipher_ctx(tfm); 2064 2065 ctx->dev = s5p_dev; 2066 crypto_skcipher_set_reqsize(tfm, sizeof(struct s5p_aes_reqctx)); 2067 2068 return 0; 2069 } 2070 2071 static struct skcipher_alg algs[] = { 2072 { 2073 .base.cra_name = "ecb(aes)", 2074 .base.cra_driver_name = "ecb-aes-s5p", 2075 .base.cra_priority = 100, 2076 .base.cra_flags = CRYPTO_ALG_ASYNC | 2077 CRYPTO_ALG_KERN_DRIVER_ONLY, 2078 .base.cra_blocksize = AES_BLOCK_SIZE, 2079 .base.cra_ctxsize = sizeof(struct s5p_aes_ctx), 2080 .base.cra_alignmask = 0x0f, 2081 .base.cra_module = THIS_MODULE, 2082 2083 .min_keysize = AES_MIN_KEY_SIZE, 2084 .max_keysize = AES_MAX_KEY_SIZE, 2085 .setkey = s5p_aes_setkey, 2086 .encrypt = s5p_aes_ecb_encrypt, 2087 .decrypt = s5p_aes_ecb_decrypt, 2088 .init = s5p_aes_init_tfm, 2089 }, 2090 { 2091 .base.cra_name = "cbc(aes)", 2092 .base.cra_driver_name = "cbc-aes-s5p", 2093 .base.cra_priority = 100, 2094 .base.cra_flags = CRYPTO_ALG_ASYNC | 2095 CRYPTO_ALG_KERN_DRIVER_ONLY, 2096 .base.cra_blocksize = AES_BLOCK_SIZE, 2097 .base.cra_ctxsize = sizeof(struct s5p_aes_ctx), 2098 .base.cra_alignmask = 0x0f, 2099 .base.cra_module = THIS_MODULE, 2100 2101 .min_keysize = AES_MIN_KEY_SIZE, 2102 .max_keysize = AES_MAX_KEY_SIZE, 2103 .ivsize = AES_BLOCK_SIZE, 2104 .setkey = s5p_aes_setkey, 2105 .encrypt = s5p_aes_cbc_encrypt, 2106 .decrypt = s5p_aes_cbc_decrypt, 2107 .init = s5p_aes_init_tfm, 2108 }, 2109 { 2110 .base.cra_name = "ctr(aes)", 2111 .base.cra_driver_name = "ctr-aes-s5p", 2112 .base.cra_priority = 100, 2113 .base.cra_flags = CRYPTO_ALG_ASYNC | 2114 CRYPTO_ALG_KERN_DRIVER_ONLY, 2115 .base.cra_blocksize = 1, 2116 .base.cra_ctxsize = sizeof(struct s5p_aes_ctx), 2117 .base.cra_alignmask = 0x0f, 2118 .base.cra_module = THIS_MODULE, 2119 2120 .min_keysize = AES_MIN_KEY_SIZE, 2121 .max_keysize = AES_MAX_KEY_SIZE, 2122 .ivsize = AES_BLOCK_SIZE, 2123 .setkey = s5p_aes_setkey, 2124 .encrypt = s5p_aes_ctr_crypt, 2125 .decrypt = s5p_aes_ctr_crypt, 2126 .init = s5p_aes_init_tfm, 2127 }, 2128 }; 2129 2130 static int s5p_aes_probe(struct platform_device *pdev) 2131 { 2132 struct device *dev = &pdev->dev; 2133 int i, err; 2134 const struct samsung_aes_variant *variant; 2135 struct s5p_aes_dev *pdata; 2136 struct resource *res; 2137 unsigned int hash_i; 2138 2139 if (s5p_dev) 2140 return -EEXIST; 2141 2142 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 2143 if (!pdata) 2144 return -ENOMEM; 2145 2146 variant = find_s5p_sss_version(pdev); 2147 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2148 if (!res) 2149 return -EINVAL; 2150 2151 /* 2152 * Note: HASH and PRNG uses the same registers in secss, avoid 2153 * overwrite each other. This will drop HASH when CONFIG_EXYNOS_RNG 2154 * is enabled in config. We need larger size for HASH registers in 2155 * secss, current describe only AES/DES 2156 */ 2157 if (IS_ENABLED(CONFIG_CRYPTO_DEV_EXYNOS_HASH)) { 2158 if (variant == &exynos_aes_data) { 2159 res->end += 0x300; 2160 pdata->use_hash = true; 2161 } 2162 } 2163 2164 pdata->res = res; 2165 pdata->ioaddr = devm_ioremap_resource(dev, res); 2166 if (IS_ERR(pdata->ioaddr)) { 2167 if (!pdata->use_hash) 2168 return PTR_ERR(pdata->ioaddr); 2169 /* try AES without HASH */ 2170 res->end -= 0x300; 2171 pdata->use_hash = false; 2172 pdata->ioaddr = devm_ioremap_resource(dev, res); 2173 if (IS_ERR(pdata->ioaddr)) 2174 return PTR_ERR(pdata->ioaddr); 2175 } 2176 2177 pdata->clk = devm_clk_get(dev, variant->clk_names[0]); 2178 if (IS_ERR(pdata->clk)) 2179 return dev_err_probe(dev, PTR_ERR(pdata->clk), 2180 "failed to find secss clock %s\n", 2181 variant->clk_names[0]); 2182 2183 err = clk_prepare_enable(pdata->clk); 2184 if (err < 0) { 2185 dev_err(dev, "Enabling clock %s failed, err %d\n", 2186 variant->clk_names[0], err); 2187 return err; 2188 } 2189 2190 if (variant->clk_names[1]) { 2191 pdata->pclk = devm_clk_get(dev, variant->clk_names[1]); 2192 if (IS_ERR(pdata->pclk)) { 2193 err = dev_err_probe(dev, PTR_ERR(pdata->pclk), 2194 "failed to find clock %s\n", 2195 variant->clk_names[1]); 2196 goto err_clk; 2197 } 2198 2199 err = clk_prepare_enable(pdata->pclk); 2200 if (err < 0) { 2201 dev_err(dev, "Enabling clock %s failed, err %d\n", 2202 variant->clk_names[0], err); 2203 goto err_clk; 2204 } 2205 } else { 2206 pdata->pclk = NULL; 2207 } 2208 2209 spin_lock_init(&pdata->lock); 2210 spin_lock_init(&pdata->hash_lock); 2211 2212 pdata->aes_ioaddr = pdata->ioaddr + variant->aes_offset; 2213 pdata->io_hash_base = pdata->ioaddr + variant->hash_offset; 2214 2215 pdata->irq_fc = platform_get_irq(pdev, 0); 2216 if (pdata->irq_fc < 0) { 2217 err = pdata->irq_fc; 2218 dev_warn(dev, "feed control interrupt is not available.\n"); 2219 goto err_irq; 2220 } 2221 err = devm_request_threaded_irq(dev, pdata->irq_fc, NULL, 2222 s5p_aes_interrupt, IRQF_ONESHOT, 2223 pdev->name, pdata); 2224 if (err < 0) { 2225 dev_warn(dev, "feed control interrupt is not available.\n"); 2226 goto err_irq; 2227 } 2228 2229 pdata->busy = false; 2230 pdata->dev = dev; 2231 platform_set_drvdata(pdev, pdata); 2232 s5p_dev = pdata; 2233 2234 tasklet_init(&pdata->tasklet, s5p_tasklet_cb, (unsigned long)pdata); 2235 crypto_init_queue(&pdata->queue, CRYPTO_QUEUE_LEN); 2236 2237 for (i = 0; i < ARRAY_SIZE(algs); i++) { 2238 err = crypto_register_skcipher(&algs[i]); 2239 if (err) { 2240 dev_err(dev, "can't register '%s': %d\n", 2241 algs[i].base.cra_name, err); 2242 goto err_algs; 2243 } 2244 } 2245 2246 if (pdata->use_hash) { 2247 tasklet_init(&pdata->hash_tasklet, s5p_hash_tasklet_cb, 2248 (unsigned long)pdata); 2249 crypto_init_queue(&pdata->hash_queue, SSS_HASH_QUEUE_LENGTH); 2250 2251 for (hash_i = 0; hash_i < ARRAY_SIZE(algs_sha1_md5_sha256); 2252 hash_i++) { 2253 struct ahash_alg *alg; 2254 2255 alg = &algs_sha1_md5_sha256[hash_i]; 2256 err = crypto_register_ahash(alg); 2257 if (err) { 2258 dev_err(dev, "can't register '%s': %d\n", 2259 alg->halg.base.cra_driver_name, err); 2260 goto err_hash; 2261 } 2262 } 2263 } 2264 2265 dev_info(dev, "s5p-sss driver registered\n"); 2266 2267 return 0; 2268 2269 err_hash: 2270 crypto_unregister_ahashes(algs_sha1_md5_sha256, hash_i); 2271 tasklet_kill(&pdata->hash_tasklet); 2272 res->end -= 0x300; 2273 2274 err_algs: 2275 crypto_unregister_skciphers(algs, i); 2276 tasklet_kill(&pdata->tasklet); 2277 2278 err_irq: 2279 clk_disable_unprepare(pdata->pclk); 2280 2281 err_clk: 2282 clk_disable_unprepare(pdata->clk); 2283 s5p_dev = NULL; 2284 2285 return err; 2286 } 2287 2288 static void s5p_aes_remove(struct platform_device *pdev) 2289 { 2290 struct s5p_aes_dev *pdata = platform_get_drvdata(pdev); 2291 2292 crypto_unregister_skciphers(algs, ARRAY_SIZE(algs)); 2293 2294 tasklet_kill(&pdata->tasklet); 2295 if (pdata->use_hash) { 2296 crypto_unregister_ahashes(algs_sha1_md5_sha256, 2297 ARRAY_SIZE(algs_sha1_md5_sha256)); 2298 2299 pdata->res->end -= 0x300; 2300 tasklet_kill(&pdata->hash_tasklet); 2301 pdata->use_hash = false; 2302 } 2303 2304 clk_disable_unprepare(pdata->pclk); 2305 2306 clk_disable_unprepare(pdata->clk); 2307 s5p_dev = NULL; 2308 } 2309 2310 static struct platform_driver s5p_aes_crypto = { 2311 .probe = s5p_aes_probe, 2312 .remove = s5p_aes_remove, 2313 .driver = { 2314 .name = "s5p-secss", 2315 .of_match_table = s5p_sss_dt_match, 2316 }, 2317 }; 2318 2319 module_platform_driver(s5p_aes_crypto); 2320 2321 MODULE_DESCRIPTION("S5PV210 AES hw acceleration support."); 2322 MODULE_LICENSE("GPL v2"); 2323 MODULE_AUTHOR("Vladimir Zapolskiy <vzapolskiy@gmail.com>"); 2324 MODULE_AUTHOR("Kamil Konieczny <k.konieczny@partner.samsung.com>"); 2325