1 /* 2 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #ifndef _REGS_V5_H_ 15 #define _REGS_V5_H_ 16 17 #include <linux/bitops.h> 18 19 #define REG_VERSION 0x000 20 #define REG_STATUS 0x100 21 #define REG_STATUS2 0x104 22 #define REG_ENGINES_AVAIL 0x108 23 #define REG_FIFO_SIZES 0x10c 24 #define REG_SEG_SIZE 0x110 25 #define REG_GOPROC 0x120 26 #define REG_ENCR_SEG_CFG 0x200 27 #define REG_ENCR_SEG_SIZE 0x204 28 #define REG_ENCR_SEG_START 0x208 29 #define REG_CNTR0_IV0 0x20c 30 #define REG_CNTR1_IV1 0x210 31 #define REG_CNTR2_IV2 0x214 32 #define REG_CNTR3_IV3 0x218 33 #define REG_CNTR_MASK 0x21C 34 #define REG_ENCR_CCM_INT_CNTR0 0x220 35 #define REG_ENCR_CCM_INT_CNTR1 0x224 36 #define REG_ENCR_CCM_INT_CNTR2 0x228 37 #define REG_ENCR_CCM_INT_CNTR3 0x22c 38 #define REG_ENCR_XTS_DU_SIZE 0x230 39 #define REG_CNTR_MASK2 0x234 40 #define REG_CNTR_MASK1 0x238 41 #define REG_CNTR_MASK0 0x23c 42 #define REG_AUTH_SEG_CFG 0x300 43 #define REG_AUTH_SEG_SIZE 0x304 44 #define REG_AUTH_SEG_START 0x308 45 #define REG_AUTH_IV0 0x310 46 #define REG_AUTH_IV1 0x314 47 #define REG_AUTH_IV2 0x318 48 #define REG_AUTH_IV3 0x31c 49 #define REG_AUTH_IV4 0x320 50 #define REG_AUTH_IV5 0x324 51 #define REG_AUTH_IV6 0x328 52 #define REG_AUTH_IV7 0x32c 53 #define REG_AUTH_IV8 0x330 54 #define REG_AUTH_IV9 0x334 55 #define REG_AUTH_IV10 0x338 56 #define REG_AUTH_IV11 0x33c 57 #define REG_AUTH_IV12 0x340 58 #define REG_AUTH_IV13 0x344 59 #define REG_AUTH_IV14 0x348 60 #define REG_AUTH_IV15 0x34c 61 #define REG_AUTH_INFO_NONCE0 0x350 62 #define REG_AUTH_INFO_NONCE1 0x354 63 #define REG_AUTH_INFO_NONCE2 0x358 64 #define REG_AUTH_INFO_NONCE3 0x35c 65 #define REG_AUTH_BYTECNT0 0x390 66 #define REG_AUTH_BYTECNT1 0x394 67 #define REG_AUTH_BYTECNT2 0x398 68 #define REG_AUTH_BYTECNT3 0x39c 69 #define REG_AUTH_EXP_MAC0 0x3a0 70 #define REG_AUTH_EXP_MAC1 0x3a4 71 #define REG_AUTH_EXP_MAC2 0x3a8 72 #define REG_AUTH_EXP_MAC3 0x3ac 73 #define REG_AUTH_EXP_MAC4 0x3b0 74 #define REG_AUTH_EXP_MAC5 0x3b4 75 #define REG_AUTH_EXP_MAC6 0x3b8 76 #define REG_AUTH_EXP_MAC7 0x3bc 77 #define REG_CONFIG 0x400 78 #define REG_GOPROC_QC_KEY 0x1000 79 #define REG_GOPROC_OEM_KEY 0x2000 80 #define REG_ENCR_KEY0 0x3000 81 #define REG_ENCR_KEY1 0x3004 82 #define REG_ENCR_KEY2 0x3008 83 #define REG_ENCR_KEY3 0x300c 84 #define REG_ENCR_KEY4 0x3010 85 #define REG_ENCR_KEY5 0x3014 86 #define REG_ENCR_KEY6 0x3018 87 #define REG_ENCR_KEY7 0x301c 88 #define REG_ENCR_XTS_KEY0 0x3020 89 #define REG_ENCR_XTS_KEY1 0x3024 90 #define REG_ENCR_XTS_KEY2 0x3028 91 #define REG_ENCR_XTS_KEY3 0x302c 92 #define REG_ENCR_XTS_KEY4 0x3030 93 #define REG_ENCR_XTS_KEY5 0x3034 94 #define REG_ENCR_XTS_KEY6 0x3038 95 #define REG_ENCR_XTS_KEY7 0x303c 96 #define REG_AUTH_KEY0 0x3040 97 #define REG_AUTH_KEY1 0x3044 98 #define REG_AUTH_KEY2 0x3048 99 #define REG_AUTH_KEY3 0x304c 100 #define REG_AUTH_KEY4 0x3050 101 #define REG_AUTH_KEY5 0x3054 102 #define REG_AUTH_KEY6 0x3058 103 #define REG_AUTH_KEY7 0x305c 104 #define REG_AUTH_KEY8 0x3060 105 #define REG_AUTH_KEY9 0x3064 106 #define REG_AUTH_KEY10 0x3068 107 #define REG_AUTH_KEY11 0x306c 108 #define REG_AUTH_KEY12 0x3070 109 #define REG_AUTH_KEY13 0x3074 110 #define REG_AUTH_KEY14 0x3078 111 #define REG_AUTH_KEY15 0x307c 112 113 /* Register bits - REG_VERSION */ 114 #define CORE_STEP_REV_SHIFT 0 115 #define CORE_STEP_REV_MASK GENMASK(15, 0) 116 #define CORE_MINOR_REV_SHIFT 16 117 #define CORE_MINOR_REV_MASK GENMASK(23, 16) 118 #define CORE_MAJOR_REV_SHIFT 24 119 #define CORE_MAJOR_REV_MASK GENMASK(31, 24) 120 121 /* Register bits - REG_STATUS */ 122 #define MAC_FAILED_SHIFT 31 123 #define DOUT_SIZE_AVAIL_SHIFT 26 124 #define DOUT_SIZE_AVAIL_MASK GENMASK(30, 26) 125 #define DIN_SIZE_AVAIL_SHIFT 21 126 #define DIN_SIZE_AVAIL_MASK GENMASK(25, 21) 127 #define HSD_ERR_SHIFT 20 128 #define ACCESS_VIOL_SHIFT 19 129 #define PIPE_ACTIVE_ERR_SHIFT 18 130 #define CFG_CHNG_ERR_SHIFT 17 131 #define DOUT_ERR_SHIFT 16 132 #define DIN_ERR_SHIFT 15 133 #define AXI_ERR_SHIFT 14 134 #define CRYPTO_STATE_SHIFT 10 135 #define CRYPTO_STATE_MASK GENMASK(13, 10) 136 #define ENCR_BUSY_SHIFT 9 137 #define AUTH_BUSY_SHIFT 8 138 #define DOUT_INTR_SHIFT 7 139 #define DIN_INTR_SHIFT 6 140 #define OP_DONE_INTR_SHIFT 5 141 #define ERR_INTR_SHIFT 4 142 #define DOUT_RDY_SHIFT 3 143 #define DIN_RDY_SHIFT 2 144 #define OPERATION_DONE_SHIFT 1 145 #define SW_ERR_SHIFT 0 146 147 /* Register bits - REG_STATUS2 */ 148 #define AXI_EXTRA_SHIFT 1 149 #define LOCKED_SHIFT 2 150 151 /* Register bits - REG_CONFIG */ 152 #define REQ_SIZE_SHIFT 17 153 #define REQ_SIZE_MASK GENMASK(20, 17) 154 #define REQ_SIZE_ENUM_1_BEAT 0 155 #define REQ_SIZE_ENUM_2_BEAT 1 156 #define REQ_SIZE_ENUM_3_BEAT 2 157 #define REQ_SIZE_ENUM_4_BEAT 3 158 #define REQ_SIZE_ENUM_5_BEAT 4 159 #define REQ_SIZE_ENUM_6_BEAT 5 160 #define REQ_SIZE_ENUM_7_BEAT 6 161 #define REQ_SIZE_ENUM_8_BEAT 7 162 #define REQ_SIZE_ENUM_9_BEAT 8 163 #define REQ_SIZE_ENUM_10_BEAT 9 164 #define REQ_SIZE_ENUM_11_BEAT 10 165 #define REQ_SIZE_ENUM_12_BEAT 11 166 #define REQ_SIZE_ENUM_13_BEAT 12 167 #define REQ_SIZE_ENUM_14_BEAT 13 168 #define REQ_SIZE_ENUM_15_BEAT 14 169 #define REQ_SIZE_ENUM_16_BEAT 15 170 171 #define MAX_QUEUED_REQ_SHIFT 14 172 #define MAX_QUEUED_REQ_MASK GENMASK(24, 16) 173 #define ENUM_1_QUEUED_REQS 0 174 #define ENUM_2_QUEUED_REQS 1 175 #define ENUM_3_QUEUED_REQS 2 176 177 #define IRQ_ENABLES_SHIFT 10 178 #define IRQ_ENABLES_MASK GENMASK(13, 10) 179 180 #define LITTLE_ENDIAN_MODE_SHIFT 9 181 #define PIPE_SET_SELECT_SHIFT 5 182 #define PIPE_SET_SELECT_MASK GENMASK(8, 5) 183 184 #define HIGH_SPD_EN_N_SHIFT 4 185 #define MASK_DOUT_INTR_SHIFT 3 186 #define MASK_DIN_INTR_SHIFT 2 187 #define MASK_OP_DONE_INTR_SHIFT 1 188 #define MASK_ERR_INTR_SHIFT 0 189 190 /* Register bits - REG_AUTH_SEG_CFG */ 191 #define COMP_EXP_MAC_SHIFT 24 192 #define COMP_EXP_MAC_DISABLED 0 193 #define COMP_EXP_MAC_ENABLED 1 194 195 #define F9_DIRECTION_SHIFT 23 196 #define F9_DIRECTION_UPLINK 0 197 #define F9_DIRECTION_DOWNLINK 1 198 199 #define AUTH_NONCE_NUM_WORDS_SHIFT 20 200 #define AUTH_NONCE_NUM_WORDS_MASK GENMASK(22, 20) 201 202 #define USE_PIPE_KEY_AUTH_SHIFT 19 203 #define USE_HW_KEY_AUTH_SHIFT 18 204 #define AUTH_FIRST_SHIFT 17 205 #define AUTH_LAST_SHIFT 16 206 207 #define AUTH_POS_SHIFT 14 208 #define AUTH_POS_MASK GENMASK(15, 14) 209 #define AUTH_POS_BEFORE 0 210 #define AUTH_POS_AFTER 1 211 212 #define AUTH_SIZE_SHIFT 9 213 #define AUTH_SIZE_MASK GENMASK(13, 9) 214 #define AUTH_SIZE_SHA1 0 215 #define AUTH_SIZE_SHA256 1 216 #define AUTH_SIZE_ENUM_1_BYTES 0 217 #define AUTH_SIZE_ENUM_2_BYTES 1 218 #define AUTH_SIZE_ENUM_3_BYTES 2 219 #define AUTH_SIZE_ENUM_4_BYTES 3 220 #define AUTH_SIZE_ENUM_5_BYTES 4 221 #define AUTH_SIZE_ENUM_6_BYTES 5 222 #define AUTH_SIZE_ENUM_7_BYTES 6 223 #define AUTH_SIZE_ENUM_8_BYTES 7 224 #define AUTH_SIZE_ENUM_9_BYTES 8 225 #define AUTH_SIZE_ENUM_10_BYTES 9 226 #define AUTH_SIZE_ENUM_11_BYTES 10 227 #define AUTH_SIZE_ENUM_12_BYTES 11 228 #define AUTH_SIZE_ENUM_13_BYTES 12 229 #define AUTH_SIZE_ENUM_14_BYTES 13 230 #define AUTH_SIZE_ENUM_15_BYTES 14 231 #define AUTH_SIZE_ENUM_16_BYTES 15 232 233 #define AUTH_MODE_SHIFT 6 234 #define AUTH_MODE_MASK GENMASK(8, 6) 235 #define AUTH_MODE_HASH 0 236 #define AUTH_MODE_HMAC 1 237 #define AUTH_MODE_CCM 0 238 #define AUTH_MODE_CMAC 1 239 240 #define AUTH_KEY_SIZE_SHIFT 3 241 #define AUTH_KEY_SIZE_MASK GENMASK(5, 3) 242 #define AUTH_KEY_SZ_AES128 0 243 #define AUTH_KEY_SZ_AES256 2 244 245 #define AUTH_ALG_SHIFT 0 246 #define AUTH_ALG_MASK GENMASK(2, 0) 247 #define AUTH_ALG_NONE 0 248 #define AUTH_ALG_SHA 1 249 #define AUTH_ALG_AES 2 250 #define AUTH_ALG_KASUMI 3 251 #define AUTH_ALG_SNOW3G 4 252 #define AUTH_ALG_ZUC 5 253 254 /* Register bits - REG_ENCR_XTS_DU_SIZE */ 255 #define ENCR_XTS_DU_SIZE_SHIFT 0 256 #define ENCR_XTS_DU_SIZE_MASK GENMASK(19, 0) 257 258 /* Register bits - REG_ENCR_SEG_CFG */ 259 #define F8_KEYSTREAM_ENABLE_SHIFT 17 260 #define F8_KEYSTREAM_DISABLED 0 261 #define F8_KEYSTREAM_ENABLED 1 262 263 #define F8_DIRECTION_SHIFT 16 264 #define F8_DIRECTION_UPLINK 0 265 #define F8_DIRECTION_DOWNLINK 1 266 267 #define USE_PIPE_KEY_ENCR_SHIFT 15 268 #define USE_PIPE_KEY_ENCR_ENABLED 1 269 #define USE_KEY_REGISTERS 0 270 271 #define USE_HW_KEY_ENCR_SHIFT 14 272 #define USE_KEY_REG 0 273 #define USE_HW_KEY 1 274 275 #define LAST_CCM_SHIFT 13 276 #define LAST_CCM_XFR 1 277 #define INTERM_CCM_XFR 0 278 279 #define CNTR_ALG_SHIFT 11 280 #define CNTR_ALG_MASK GENMASK(12, 11) 281 #define CNTR_ALG_NIST 0 282 283 #define ENCODE_SHIFT 10 284 285 #define ENCR_MODE_SHIFT 6 286 #define ENCR_MODE_MASK GENMASK(9, 6) 287 #define ENCR_MODE_ECB 0 288 #define ENCR_MODE_CBC 1 289 #define ENCR_MODE_CTR 2 290 #define ENCR_MODE_XTS 3 291 #define ENCR_MODE_CCM 4 292 293 #define ENCR_KEY_SZ_SHIFT 3 294 #define ENCR_KEY_SZ_MASK GENMASK(5, 3) 295 #define ENCR_KEY_SZ_DES 0 296 #define ENCR_KEY_SZ_3DES 1 297 #define ENCR_KEY_SZ_AES128 0 298 #define ENCR_KEY_SZ_AES256 2 299 300 #define ENCR_ALG_SHIFT 0 301 #define ENCR_ALG_MASK GENMASK(2, 0) 302 #define ENCR_ALG_NONE 0 303 #define ENCR_ALG_DES 1 304 #define ENCR_ALG_AES 2 305 #define ENCR_ALG_KASUMI 4 306 #define ENCR_ALG_SNOW_3G 5 307 #define ENCR_ALG_ZUC 6 308 309 /* Register bits - REG_GOPROC */ 310 #define GO_SHIFT 0 311 #define CLR_CNTXT_SHIFT 1 312 #define RESULTS_DUMP_SHIFT 2 313 314 /* Register bits - REG_ENGINES_AVAIL */ 315 #define ENCR_AES_SEL_SHIFT 0 316 #define DES_SEL_SHIFT 1 317 #define ENCR_SNOW3G_SEL_SHIFT 2 318 #define ENCR_KASUMI_SEL_SHIFT 3 319 #define SHA_SEL_SHIFT 4 320 #define SHA512_SEL_SHIFT 5 321 #define AUTH_AES_SEL_SHIFT 6 322 #define AUTH_SNOW3G_SEL_SHIFT 7 323 #define AUTH_KASUMI_SEL_SHIFT 8 324 #define BAM_PIPE_SETS_SHIFT 9 325 #define BAM_PIPE_SETS_MASK GENMASK(12, 9) 326 #define AXI_WR_BEATS_SHIFT 13 327 #define AXI_WR_BEATS_MASK GENMASK(18, 13) 328 #define AXI_RD_BEATS_SHIFT 19 329 #define AXI_RD_BEATS_MASK GENMASK(24, 19) 330 #define ENCR_ZUC_SEL_SHIFT 26 331 #define AUTH_ZUC_SEL_SHIFT 27 332 #define ZUC_ENABLE_SHIFT 28 333 334 #endif /* _REGS_V5_H_ */ 335