1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2010-2014, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/cleanup.h> 7 #include <linux/clk.h> 8 #include <linux/device.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/interconnect.h> 11 #include <linux/interrupt.h> 12 #include <linux/module.h> 13 #include <linux/mod_devicetable.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/types.h> 18 #include <crypto/algapi.h> 19 #include <crypto/internal/hash.h> 20 21 #include "core.h" 22 #include "cipher.h" 23 #include "sha.h" 24 #include "aead.h" 25 26 #define QCE_QUEUE_LENGTH 1 27 28 #define QCE_DEFAULT_MEM_BANDWIDTH 393600 29 30 static const struct qce_algo_ops *qce_ops[] = { 31 #ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER 32 &skcipher_ops, 33 #endif 34 #ifdef CONFIG_CRYPTO_DEV_QCE_SHA 35 &ahash_ops, 36 #endif 37 #ifdef CONFIG_CRYPTO_DEV_QCE_AEAD 38 &aead_ops, 39 #endif 40 }; 41 42 static void qce_unregister_algs(void *data) 43 { 44 const struct qce_algo_ops *ops; 45 struct qce_device *qce = data; 46 int i; 47 48 for (i = 0; i < ARRAY_SIZE(qce_ops); i++) { 49 ops = qce_ops[i]; 50 ops->unregister_algs(qce); 51 } 52 } 53 54 static int devm_qce_register_algs(struct qce_device *qce) 55 { 56 const struct qce_algo_ops *ops; 57 int i, ret; 58 59 for (i = 0; i < ARRAY_SIZE(qce_ops); i++) { 60 ops = qce_ops[i]; 61 ret = ops->register_algs(qce); 62 if (ret) { 63 while (i--) 64 qce_ops[i]->unregister_algs(qce); 65 return ret; 66 } 67 } 68 69 return devm_add_action_or_reset(qce->dev, qce_unregister_algs, qce); 70 } 71 72 static int qce_handle_request(struct crypto_async_request *async_req) 73 { 74 int i; 75 const struct qce_algo_ops *ops; 76 u32 type = crypto_tfm_alg_type(async_req->tfm); 77 78 for (i = 0; i < ARRAY_SIZE(qce_ops); i++) { 79 ops = qce_ops[i]; 80 if (type == ops->type) 81 return ops->async_req_handle(async_req); 82 } 83 84 return -EINVAL; 85 } 86 87 static int qce_handle_queue(struct qce_device *qce, 88 struct crypto_async_request *req) 89 { 90 struct crypto_async_request *async_req, *backlog; 91 int ret, err; 92 93 PM_RUNTIME_ACQUIRE_AUTOSUSPEND(qce->dev, pm); 94 ret = PM_RUNTIME_ACQUIRE_ERR(&pm); 95 if (ret) 96 return ret; 97 98 scoped_guard(mutex, &qce->lock) { 99 if (req) 100 ret = crypto_enqueue_request(&qce->queue, req); 101 102 /* busy, do not dequeue request */ 103 if (qce->req) 104 return ret; 105 106 backlog = crypto_get_backlog(&qce->queue); 107 async_req = crypto_dequeue_request(&qce->queue); 108 if (async_req) 109 qce->req = async_req; 110 } 111 112 if (!async_req) 113 return ret; 114 115 if (backlog) { 116 scoped_guard(mutex, &qce->lock) 117 crypto_request_complete(backlog, -EINPROGRESS); 118 } 119 120 err = qce_handle_request(async_req); 121 if (err) { 122 qce->result = err; 123 schedule_work(&qce->done_work); 124 } 125 126 return ret; 127 } 128 129 static void qce_req_done_work(struct work_struct *work) 130 { 131 struct qce_device *qce = container_of(work, struct qce_device, 132 done_work); 133 struct crypto_async_request *req; 134 135 scoped_guard(mutex, &qce->lock) { 136 req = qce->req; 137 qce->req = NULL; 138 } 139 140 if (req) 141 crypto_request_complete(req, qce->result); 142 143 qce_handle_queue(qce, NULL); 144 } 145 146 static int qce_async_request_enqueue(struct qce_device *qce, 147 struct crypto_async_request *req) 148 { 149 return qce_handle_queue(qce, req); 150 } 151 152 static void qce_async_request_done(struct qce_device *qce, int ret) 153 { 154 qce->result = ret; 155 schedule_work(&qce->done_work); 156 } 157 158 static int qce_check_version(struct qce_device *qce) 159 { 160 u32 major, minor, step; 161 162 qce_get_version(qce, &major, &minor, &step); 163 164 /* 165 * the driver does not support v5 with minor 0 because it has special 166 * alignment requirements. 167 */ 168 if (major == 5 && minor == 0) 169 return -ENODEV; 170 171 qce->burst_size = QCE_BAM_BURST_SIZE; 172 173 /* 174 * Rx and tx pipes are treated as a pair inside CE. 175 * Pipe pair number depends on the actual BAM dma pipe 176 * that is used for transfers. The BAM dma pipes are passed 177 * from the device tree and used to derive the pipe pair 178 * id in the CE driver as follows. 179 * BAM dma pipes(rx, tx) CE pipe pair id 180 * 0,1 0 181 * 2,3 1 182 * 4,5 2 183 * 6,7 3 184 * ... 185 */ 186 qce->pipe_pair_id = qce->dma.rxchan->chan_id >> 1; 187 188 dev_dbg(qce->dev, "Crypto device found, version %d.%d.%d\n", 189 major, minor, step); 190 191 return 0; 192 } 193 194 static int qce_crypto_probe(struct platform_device *pdev) 195 { 196 struct device *dev = &pdev->dev; 197 struct qce_device *qce; 198 int ret; 199 200 qce = devm_kzalloc(dev, sizeof(*qce), GFP_KERNEL); 201 if (!qce) 202 return -ENOMEM; 203 204 qce->dev = dev; 205 platform_set_drvdata(pdev, qce); 206 207 qce->base = devm_platform_ioremap_resource(pdev, 0); 208 if (IS_ERR(qce->base)) 209 return PTR_ERR(qce->base); 210 211 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 212 if (ret < 0) 213 return ret; 214 215 qce->core = devm_clk_get_optional(qce->dev, "core"); 216 if (IS_ERR(qce->core)) 217 return PTR_ERR(qce->core); 218 219 qce->iface = devm_clk_get_optional(qce->dev, "iface"); 220 if (IS_ERR(qce->iface)) 221 return PTR_ERR(qce->iface); 222 223 qce->bus = devm_clk_get_optional(qce->dev, "bus"); 224 if (IS_ERR(qce->bus)) 225 return PTR_ERR(qce->bus); 226 227 qce->mem_path = devm_of_icc_get(dev, "memory"); 228 if (IS_ERR(qce->mem_path)) 229 return PTR_ERR(qce->mem_path); 230 231 /* 232 * Enable runtime PM after clocks and ICC path are acquired so that 233 * the resume callback can enable clocks and apply the ICC bandwidth 234 * vote before any hardware access takes place. 235 */ 236 ret = devm_pm_runtime_enable(dev); 237 if (ret) 238 return ret; 239 240 PM_RUNTIME_ACQUIRE_AUTOSUSPEND(dev, pm); 241 ret = PM_RUNTIME_ACQUIRE_ERR(&pm); 242 if (ret) 243 return ret; 244 245 ret = devm_qce_dma_request(qce->dev, &qce->dma); 246 if (ret) 247 return ret; 248 249 ret = qce_check_version(qce); 250 if (ret) 251 return ret; 252 253 ret = devm_mutex_init(qce->dev, &qce->lock); 254 if (ret) 255 return ret; 256 257 INIT_WORK(&qce->done_work, qce_req_done_work); 258 crypto_init_queue(&qce->queue, QCE_QUEUE_LENGTH); 259 260 qce->async_req_enqueue = qce_async_request_enqueue; 261 qce->async_req_done = qce_async_request_done; 262 263 ret = devm_qce_register_algs(qce); 264 if (ret) 265 return ret; 266 267 /* Configure autosuspend after successful init */ 268 pm_runtime_set_autosuspend_delay(dev, 100); 269 pm_runtime_use_autosuspend(dev); 270 pm_runtime_mark_last_busy(dev); 271 272 return 0; 273 } 274 275 static int qce_runtime_suspend(struct device *dev) 276 { 277 struct qce_device *qce = dev_get_drvdata(dev); 278 int ret; 279 280 clk_disable_unprepare(qce->core); 281 clk_disable_unprepare(qce->iface); 282 clk_disable_unprepare(qce->bus); 283 284 ret = icc_set_bw(qce->mem_path, 0, 0); 285 if (ret) { 286 clk_prepare_enable(qce->bus); 287 clk_prepare_enable(qce->iface); 288 clk_prepare_enable(qce->core); 289 return ret; 290 } 291 292 return 0; 293 } 294 295 static int qce_runtime_resume(struct device *dev) 296 { 297 struct qce_device *qce = dev_get_drvdata(dev); 298 int ret; 299 300 ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, 301 QCE_DEFAULT_MEM_BANDWIDTH); 302 if (ret) 303 return ret; 304 305 ret = clk_prepare_enable(qce->core); 306 if (ret) 307 goto err_core; 308 309 ret = clk_prepare_enable(qce->iface); 310 if (ret) 311 goto err_iface; 312 313 ret = clk_prepare_enable(qce->bus); 314 if (ret) 315 goto err_bus; 316 317 return 0; 318 319 err_bus: 320 clk_disable_unprepare(qce->iface); 321 err_iface: 322 clk_disable_unprepare(qce->core); 323 err_core: 324 icc_set_bw(qce->mem_path, 0, 0); 325 return ret; 326 } 327 328 static const struct dev_pm_ops qce_crypto_pm_ops = { 329 RUNTIME_PM_OPS(qce_runtime_suspend, qce_runtime_resume, NULL) 330 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 331 }; 332 333 static const struct of_device_id qce_crypto_of_match[] = { 334 { .compatible = "qcom,crypto-v5.1", }, 335 { .compatible = "qcom,crypto-v5.4", }, 336 { .compatible = "qcom,qce", }, 337 {} 338 }; 339 MODULE_DEVICE_TABLE(of, qce_crypto_of_match); 340 341 static struct platform_driver qce_crypto_driver = { 342 .probe = qce_crypto_probe, 343 .driver = { 344 .name = KBUILD_MODNAME, 345 .of_match_table = qce_crypto_of_match, 346 .pm = pm_ptr(&qce_crypto_pm_ops), 347 }, 348 }; 349 module_platform_driver(qce_crypto_driver); 350 351 MODULE_LICENSE("GPL v2"); 352 MODULE_DESCRIPTION("Qualcomm crypto engine driver"); 353 MODULE_ALIAS("platform:" KBUILD_MODNAME); 354 MODULE_AUTHOR("The Linux Foundation"); 355