1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2010-2014, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/device.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/interconnect.h> 10 #include <linux/interrupt.h> 11 #include <linux/module.h> 12 #include <linux/mod_devicetable.h> 13 #include <linux/platform_device.h> 14 #include <linux/spinlock.h> 15 #include <linux/types.h> 16 #include <crypto/algapi.h> 17 #include <crypto/internal/hash.h> 18 19 #include "core.h" 20 #include "cipher.h" 21 #include "sha.h" 22 #include "aead.h" 23 24 #define QCE_MAJOR_VERSION5 0x05 25 #define QCE_QUEUE_LENGTH 1 26 27 #define QCE_DEFAULT_MEM_BANDWIDTH 393600 28 29 static const struct qce_algo_ops *qce_ops[] = { 30 #ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER 31 &skcipher_ops, 32 #endif 33 #ifdef CONFIG_CRYPTO_DEV_QCE_SHA 34 &ahash_ops, 35 #endif 36 #ifdef CONFIG_CRYPTO_DEV_QCE_AEAD 37 &aead_ops, 38 #endif 39 }; 40 41 static void qce_unregister_algs(void *data) 42 { 43 const struct qce_algo_ops *ops; 44 struct qce_device *qce = data; 45 int i; 46 47 for (i = 0; i < ARRAY_SIZE(qce_ops); i++) { 48 ops = qce_ops[i]; 49 ops->unregister_algs(qce); 50 } 51 } 52 53 static int devm_qce_register_algs(struct qce_device *qce) 54 { 55 const struct qce_algo_ops *ops; 56 int i, j, ret = -ENODEV; 57 58 for (i = 0; i < ARRAY_SIZE(qce_ops); i++) { 59 ops = qce_ops[i]; 60 ret = ops->register_algs(qce); 61 if (ret) { 62 for (j = i - 1; j >= 0; j--) 63 ops->unregister_algs(qce); 64 return ret; 65 } 66 } 67 68 return devm_add_action_or_reset(qce->dev, qce_unregister_algs, qce); 69 } 70 71 static int qce_handle_request(struct crypto_async_request *async_req) 72 { 73 int ret = -EINVAL, i; 74 const struct qce_algo_ops *ops; 75 u32 type = crypto_tfm_alg_type(async_req->tfm); 76 77 for (i = 0; i < ARRAY_SIZE(qce_ops); i++) { 78 ops = qce_ops[i]; 79 if (type != ops->type) 80 continue; 81 ret = ops->async_req_handle(async_req); 82 break; 83 } 84 85 return ret; 86 } 87 88 static int qce_handle_queue(struct qce_device *qce, 89 struct crypto_async_request *req) 90 { 91 struct crypto_async_request *async_req, *backlog; 92 unsigned long flags; 93 int ret = 0, err; 94 95 spin_lock_irqsave(&qce->lock, flags); 96 97 if (req) 98 ret = crypto_enqueue_request(&qce->queue, req); 99 100 /* busy, do not dequeue request */ 101 if (qce->req) { 102 spin_unlock_irqrestore(&qce->lock, flags); 103 return ret; 104 } 105 106 backlog = crypto_get_backlog(&qce->queue); 107 async_req = crypto_dequeue_request(&qce->queue); 108 if (async_req) 109 qce->req = async_req; 110 111 spin_unlock_irqrestore(&qce->lock, flags); 112 113 if (!async_req) 114 return ret; 115 116 if (backlog) { 117 spin_lock_bh(&qce->lock); 118 crypto_request_complete(backlog, -EINPROGRESS); 119 spin_unlock_bh(&qce->lock); 120 } 121 122 err = qce_handle_request(async_req); 123 if (err) { 124 qce->result = err; 125 schedule_work(&qce->done_work); 126 } 127 128 return ret; 129 } 130 131 static void qce_req_done_work(struct work_struct *work) 132 { 133 struct qce_device *qce = container_of(work, struct qce_device, 134 done_work); 135 struct crypto_async_request *req; 136 unsigned long flags; 137 138 spin_lock_irqsave(&qce->lock, flags); 139 req = qce->req; 140 qce->req = NULL; 141 spin_unlock_irqrestore(&qce->lock, flags); 142 143 if (req) 144 crypto_request_complete(req, qce->result); 145 146 qce_handle_queue(qce, NULL); 147 } 148 149 static int qce_async_request_enqueue(struct qce_device *qce, 150 struct crypto_async_request *req) 151 { 152 return qce_handle_queue(qce, req); 153 } 154 155 static void qce_async_request_done(struct qce_device *qce, int ret) 156 { 157 qce->result = ret; 158 schedule_work(&qce->done_work); 159 } 160 161 static int qce_check_version(struct qce_device *qce) 162 { 163 u32 major, minor, step; 164 165 qce_get_version(qce, &major, &minor, &step); 166 167 /* 168 * the driver does not support v5 with minor 0 because it has special 169 * alignment requirements. 170 */ 171 if (major != QCE_MAJOR_VERSION5 || minor == 0) 172 return -ENODEV; 173 174 qce->burst_size = QCE_BAM_BURST_SIZE; 175 176 /* 177 * Rx and tx pipes are treated as a pair inside CE. 178 * Pipe pair number depends on the actual BAM dma pipe 179 * that is used for transfers. The BAM dma pipes are passed 180 * from the device tree and used to derive the pipe pair 181 * id in the CE driver as follows. 182 * BAM dma pipes(rx, tx) CE pipe pair id 183 * 0,1 0 184 * 2,3 1 185 * 4,5 2 186 * 6,7 3 187 * ... 188 */ 189 qce->pipe_pair_id = qce->dma.rxchan->chan_id >> 1; 190 191 dev_dbg(qce->dev, "Crypto device found, version %d.%d.%d\n", 192 major, minor, step); 193 194 return 0; 195 } 196 197 static int qce_crypto_probe(struct platform_device *pdev) 198 { 199 struct device *dev = &pdev->dev; 200 struct qce_device *qce; 201 int ret; 202 203 qce = devm_kzalloc(dev, sizeof(*qce), GFP_KERNEL); 204 if (!qce) 205 return -ENOMEM; 206 207 qce->dev = dev; 208 platform_set_drvdata(pdev, qce); 209 210 qce->base = devm_platform_ioremap_resource(pdev, 0); 211 if (IS_ERR(qce->base)) 212 return PTR_ERR(qce->base); 213 214 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 215 if (ret < 0) 216 return ret; 217 218 qce->core = devm_clk_get_optional_enabled(qce->dev, "core"); 219 if (IS_ERR(qce->core)) 220 return PTR_ERR(qce->core); 221 222 qce->iface = devm_clk_get_optional_enabled(qce->dev, "iface"); 223 if (IS_ERR(qce->iface)) 224 return PTR_ERR(qce->iface); 225 226 qce->bus = devm_clk_get_optional_enabled(qce->dev, "bus"); 227 if (IS_ERR(qce->bus)) 228 return PTR_ERR(qce->bus); 229 230 qce->mem_path = devm_of_icc_get(qce->dev, "memory"); 231 if (IS_ERR(qce->mem_path)) 232 return PTR_ERR(qce->mem_path); 233 234 ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH); 235 if (ret) 236 return ret; 237 238 ret = devm_qce_dma_request(qce->dev, &qce->dma); 239 if (ret) 240 return ret; 241 242 ret = qce_check_version(qce); 243 if (ret) 244 return ret; 245 246 spin_lock_init(&qce->lock); 247 INIT_WORK(&qce->done_work, qce_req_done_work); 248 crypto_init_queue(&qce->queue, QCE_QUEUE_LENGTH); 249 250 qce->async_req_enqueue = qce_async_request_enqueue; 251 qce->async_req_done = qce_async_request_done; 252 253 return devm_qce_register_algs(qce); 254 } 255 256 static const struct of_device_id qce_crypto_of_match[] = { 257 { .compatible = "qcom,crypto-v5.1", }, 258 { .compatible = "qcom,crypto-v5.4", }, 259 { .compatible = "qcom,qce", }, 260 {} 261 }; 262 MODULE_DEVICE_TABLE(of, qce_crypto_of_match); 263 264 static struct platform_driver qce_crypto_driver = { 265 .probe = qce_crypto_probe, 266 .driver = { 267 .name = KBUILD_MODNAME, 268 .of_match_table = qce_crypto_of_match, 269 }, 270 }; 271 module_platform_driver(qce_crypto_driver); 272 273 MODULE_LICENSE("GPL v2"); 274 MODULE_DESCRIPTION("Qualcomm crypto engine driver"); 275 MODULE_ALIAS("platform:" KBUILD_MODNAME); 276 MODULE_AUTHOR("The Linux Foundation"); 277