1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2010-2014, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/cleanup.h> 7 #include <linux/clk.h> 8 #include <linux/device.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/interconnect.h> 11 #include <linux/interrupt.h> 12 #include <linux/module.h> 13 #include <linux/mod_devicetable.h> 14 #include <linux/platform_device.h> 15 #include <linux/types.h> 16 #include <crypto/algapi.h> 17 #include <crypto/internal/hash.h> 18 19 #include "core.h" 20 #include "cipher.h" 21 #include "sha.h" 22 #include "aead.h" 23 24 #define QCE_QUEUE_LENGTH 1 25 26 #define QCE_DEFAULT_MEM_BANDWIDTH 393600 27 28 static const struct qce_algo_ops *qce_ops[] = { 29 #ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER 30 &skcipher_ops, 31 #endif 32 #ifdef CONFIG_CRYPTO_DEV_QCE_SHA 33 &ahash_ops, 34 #endif 35 #ifdef CONFIG_CRYPTO_DEV_QCE_AEAD 36 &aead_ops, 37 #endif 38 }; 39 40 static void qce_unregister_algs(void *data) 41 { 42 const struct qce_algo_ops *ops; 43 struct qce_device *qce = data; 44 int i; 45 46 for (i = 0; i < ARRAY_SIZE(qce_ops); i++) { 47 ops = qce_ops[i]; 48 ops->unregister_algs(qce); 49 } 50 } 51 52 static int devm_qce_register_algs(struct qce_device *qce) 53 { 54 const struct qce_algo_ops *ops; 55 int i, j, ret = -ENODEV; 56 57 for (i = 0; i < ARRAY_SIZE(qce_ops); i++) { 58 ops = qce_ops[i]; 59 ret = ops->register_algs(qce); 60 if (ret) { 61 for (j = i - 1; j >= 0; j--) 62 ops->unregister_algs(qce); 63 return ret; 64 } 65 } 66 67 return devm_add_action_or_reset(qce->dev, qce_unregister_algs, qce); 68 } 69 70 static int qce_handle_request(struct crypto_async_request *async_req) 71 { 72 int ret = -EINVAL, i; 73 const struct qce_algo_ops *ops; 74 u32 type = crypto_tfm_alg_type(async_req->tfm); 75 76 for (i = 0; i < ARRAY_SIZE(qce_ops); i++) { 77 ops = qce_ops[i]; 78 if (type != ops->type) 79 continue; 80 ret = ops->async_req_handle(async_req); 81 break; 82 } 83 84 return ret; 85 } 86 87 static int qce_handle_queue(struct qce_device *qce, 88 struct crypto_async_request *req) 89 { 90 struct crypto_async_request *async_req, *backlog; 91 int ret = 0, err; 92 93 scoped_guard(mutex, &qce->lock) { 94 if (req) 95 ret = crypto_enqueue_request(&qce->queue, req); 96 97 /* busy, do not dequeue request */ 98 if (qce->req) 99 return ret; 100 101 backlog = crypto_get_backlog(&qce->queue); 102 async_req = crypto_dequeue_request(&qce->queue); 103 if (async_req) 104 qce->req = async_req; 105 } 106 107 if (!async_req) 108 return ret; 109 110 if (backlog) { 111 scoped_guard(mutex, &qce->lock) 112 crypto_request_complete(backlog, -EINPROGRESS); 113 } 114 115 err = qce_handle_request(async_req); 116 if (err) { 117 qce->result = err; 118 schedule_work(&qce->done_work); 119 } 120 121 return ret; 122 } 123 124 static void qce_req_done_work(struct work_struct *work) 125 { 126 struct qce_device *qce = container_of(work, struct qce_device, 127 done_work); 128 struct crypto_async_request *req; 129 130 scoped_guard(mutex, &qce->lock) { 131 req = qce->req; 132 qce->req = NULL; 133 } 134 135 if (req) 136 crypto_request_complete(req, qce->result); 137 138 qce_handle_queue(qce, NULL); 139 } 140 141 static int qce_async_request_enqueue(struct qce_device *qce, 142 struct crypto_async_request *req) 143 { 144 return qce_handle_queue(qce, req); 145 } 146 147 static void qce_async_request_done(struct qce_device *qce, int ret) 148 { 149 qce->result = ret; 150 schedule_work(&qce->done_work); 151 } 152 153 static int qce_check_version(struct qce_device *qce) 154 { 155 u32 major, minor, step; 156 157 qce_get_version(qce, &major, &minor, &step); 158 159 /* 160 * the driver does not support v5 with minor 0 because it has special 161 * alignment requirements. 162 */ 163 if (major == 5 && minor == 0) 164 return -ENODEV; 165 166 qce->burst_size = QCE_BAM_BURST_SIZE; 167 168 /* 169 * Rx and tx pipes are treated as a pair inside CE. 170 * Pipe pair number depends on the actual BAM dma pipe 171 * that is used for transfers. The BAM dma pipes are passed 172 * from the device tree and used to derive the pipe pair 173 * id in the CE driver as follows. 174 * BAM dma pipes(rx, tx) CE pipe pair id 175 * 0,1 0 176 * 2,3 1 177 * 4,5 2 178 * 6,7 3 179 * ... 180 */ 181 qce->pipe_pair_id = qce->dma.rxchan->chan_id >> 1; 182 183 dev_dbg(qce->dev, "Crypto device found, version %d.%d.%d\n", 184 major, minor, step); 185 186 return 0; 187 } 188 189 static int qce_crypto_probe(struct platform_device *pdev) 190 { 191 struct device *dev = &pdev->dev; 192 struct qce_device *qce; 193 int ret; 194 195 qce = devm_kzalloc(dev, sizeof(*qce), GFP_KERNEL); 196 if (!qce) 197 return -ENOMEM; 198 199 qce->dev = dev; 200 platform_set_drvdata(pdev, qce); 201 202 qce->base = devm_platform_ioremap_resource(pdev, 0); 203 if (IS_ERR(qce->base)) 204 return PTR_ERR(qce->base); 205 206 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 207 if (ret < 0) 208 return ret; 209 210 qce->core = devm_clk_get_optional_enabled(qce->dev, "core"); 211 if (IS_ERR(qce->core)) 212 return PTR_ERR(qce->core); 213 214 qce->iface = devm_clk_get_optional_enabled(qce->dev, "iface"); 215 if (IS_ERR(qce->iface)) 216 return PTR_ERR(qce->iface); 217 218 qce->bus = devm_clk_get_optional_enabled(qce->dev, "bus"); 219 if (IS_ERR(qce->bus)) 220 return PTR_ERR(qce->bus); 221 222 qce->mem_path = devm_of_icc_get(qce->dev, "memory"); 223 if (IS_ERR(qce->mem_path)) 224 return PTR_ERR(qce->mem_path); 225 226 ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH); 227 if (ret) 228 return ret; 229 230 ret = devm_qce_dma_request(qce->dev, &qce->dma); 231 if (ret) 232 return ret; 233 234 ret = qce_check_version(qce); 235 if (ret) 236 return ret; 237 238 ret = devm_mutex_init(qce->dev, &qce->lock); 239 if (ret) 240 return ret; 241 242 INIT_WORK(&qce->done_work, qce_req_done_work); 243 crypto_init_queue(&qce->queue, QCE_QUEUE_LENGTH); 244 245 qce->async_req_enqueue = qce_async_request_enqueue; 246 qce->async_req_done = qce_async_request_done; 247 248 return devm_qce_register_algs(qce); 249 } 250 251 static const struct of_device_id qce_crypto_of_match[] = { 252 { .compatible = "qcom,crypto-v5.1", }, 253 { .compatible = "qcom,crypto-v5.4", }, 254 { .compatible = "qcom,qce", }, 255 {} 256 }; 257 MODULE_DEVICE_TABLE(of, qce_crypto_of_match); 258 259 static struct platform_driver qce_crypto_driver = { 260 .probe = qce_crypto_probe, 261 .driver = { 262 .name = KBUILD_MODNAME, 263 .of_match_table = qce_crypto_of_match, 264 }, 265 }; 266 module_platform_driver(qce_crypto_driver); 267 268 MODULE_LICENSE("GPL v2"); 269 MODULE_DESCRIPTION("Qualcomm crypto engine driver"); 270 MODULE_ALIAS("platform:" KBUILD_MODNAME); 271 MODULE_AUTHOR("The Linux Foundation"); 272