1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2010-2014, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/cleanup.h> 7 #include <linux/clk.h> 8 #include <linux/device.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/interconnect.h> 11 #include <linux/interrupt.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/types.h> 15 #include <crypto/algapi.h> 16 #include <crypto/internal/hash.h> 17 18 #include "core.h" 19 #include "cipher.h" 20 #include "sha.h" 21 #include "aead.h" 22 23 #define QCE_QUEUE_LENGTH 1 24 25 #define QCE_DEFAULT_MEM_BANDWIDTH 393600 26 27 static const struct qce_algo_ops *qce_ops[] = { 28 #ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER 29 &skcipher_ops, 30 #endif 31 #ifdef CONFIG_CRYPTO_DEV_QCE_SHA 32 &ahash_ops, 33 #endif 34 #ifdef CONFIG_CRYPTO_DEV_QCE_AEAD 35 &aead_ops, 36 #endif 37 }; 38 39 static void qce_unregister_algs(void *data) 40 { 41 const struct qce_algo_ops *ops; 42 struct qce_device *qce = data; 43 int i; 44 45 for (i = 0; i < ARRAY_SIZE(qce_ops); i++) { 46 ops = qce_ops[i]; 47 ops->unregister_algs(qce); 48 } 49 } 50 51 static int devm_qce_register_algs(struct qce_device *qce) 52 { 53 const struct qce_algo_ops *ops; 54 int i, j, ret = -ENODEV; 55 56 for (i = 0; i < ARRAY_SIZE(qce_ops); i++) { 57 ops = qce_ops[i]; 58 ret = ops->register_algs(qce); 59 if (ret) { 60 for (j = i - 1; j >= 0; j--) 61 ops->unregister_algs(qce); 62 return ret; 63 } 64 } 65 66 return devm_add_action_or_reset(qce->dev, qce_unregister_algs, qce); 67 } 68 69 static int qce_handle_request(struct crypto_async_request *async_req) 70 { 71 int ret = -EINVAL, i; 72 const struct qce_algo_ops *ops; 73 u32 type = crypto_tfm_alg_type(async_req->tfm); 74 75 for (i = 0; i < ARRAY_SIZE(qce_ops); i++) { 76 ops = qce_ops[i]; 77 if (type != ops->type) 78 continue; 79 ret = ops->async_req_handle(async_req); 80 break; 81 } 82 83 return ret; 84 } 85 86 static int qce_handle_queue(struct qce_device *qce, 87 struct crypto_async_request *req) 88 { 89 struct crypto_async_request *async_req, *backlog; 90 int ret = 0, err; 91 92 scoped_guard(mutex, &qce->lock) { 93 if (req) 94 ret = crypto_enqueue_request(&qce->queue, req); 95 96 /* busy, do not dequeue request */ 97 if (qce->req) 98 return ret; 99 100 backlog = crypto_get_backlog(&qce->queue); 101 async_req = crypto_dequeue_request(&qce->queue); 102 if (async_req) 103 qce->req = async_req; 104 } 105 106 if (!async_req) 107 return ret; 108 109 if (backlog) { 110 scoped_guard(mutex, &qce->lock) 111 crypto_request_complete(backlog, -EINPROGRESS); 112 } 113 114 err = qce_handle_request(async_req); 115 if (err) { 116 qce->result = err; 117 schedule_work(&qce->done_work); 118 } 119 120 return ret; 121 } 122 123 static void qce_req_done_work(struct work_struct *work) 124 { 125 struct qce_device *qce = container_of(work, struct qce_device, 126 done_work); 127 struct crypto_async_request *req; 128 129 scoped_guard(mutex, &qce->lock) { 130 req = qce->req; 131 qce->req = NULL; 132 } 133 134 if (req) 135 crypto_request_complete(req, qce->result); 136 137 qce_handle_queue(qce, NULL); 138 } 139 140 static int qce_async_request_enqueue(struct qce_device *qce, 141 struct crypto_async_request *req) 142 { 143 return qce_handle_queue(qce, req); 144 } 145 146 static void qce_async_request_done(struct qce_device *qce, int ret) 147 { 148 qce->result = ret; 149 schedule_work(&qce->done_work); 150 } 151 152 static int qce_check_version(struct qce_device *qce) 153 { 154 u32 major, minor, step; 155 156 qce_get_version(qce, &major, &minor, &step); 157 158 /* 159 * the driver does not support v5 with minor 0 because it has special 160 * alignment requirements. 161 */ 162 if (major == 5 && minor == 0) 163 return -ENODEV; 164 165 qce->burst_size = QCE_BAM_BURST_SIZE; 166 167 /* 168 * Rx and tx pipes are treated as a pair inside CE. 169 * Pipe pair number depends on the actual BAM dma pipe 170 * that is used for transfers. The BAM dma pipes are passed 171 * from the device tree and used to derive the pipe pair 172 * id in the CE driver as follows. 173 * BAM dma pipes(rx, tx) CE pipe pair id 174 * 0,1 0 175 * 2,3 1 176 * 4,5 2 177 * 6,7 3 178 * ... 179 */ 180 qce->pipe_pair_id = qce->dma.rxchan->chan_id >> 1; 181 182 dev_dbg(qce->dev, "Crypto device found, version %d.%d.%d\n", 183 major, minor, step); 184 185 return 0; 186 } 187 188 static int qce_crypto_probe(struct platform_device *pdev) 189 { 190 struct device *dev = &pdev->dev; 191 struct qce_device *qce; 192 int ret; 193 194 qce = devm_kzalloc(dev, sizeof(*qce), GFP_KERNEL); 195 if (!qce) 196 return -ENOMEM; 197 198 qce->dev = dev; 199 platform_set_drvdata(pdev, qce); 200 201 qce->base = devm_platform_ioremap_resource(pdev, 0); 202 if (IS_ERR(qce->base)) 203 return PTR_ERR(qce->base); 204 205 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 206 if (ret < 0) 207 return ret; 208 209 qce->core = devm_clk_get_optional_enabled(qce->dev, "core"); 210 if (IS_ERR(qce->core)) 211 return PTR_ERR(qce->core); 212 213 qce->iface = devm_clk_get_optional_enabled(qce->dev, "iface"); 214 if (IS_ERR(qce->iface)) 215 return PTR_ERR(qce->iface); 216 217 qce->bus = devm_clk_get_optional_enabled(qce->dev, "bus"); 218 if (IS_ERR(qce->bus)) 219 return PTR_ERR(qce->bus); 220 221 qce->mem_path = devm_of_icc_get(qce->dev, "memory"); 222 if (IS_ERR(qce->mem_path)) 223 return PTR_ERR(qce->mem_path); 224 225 ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH); 226 if (ret) 227 return ret; 228 229 ret = devm_qce_dma_request(qce->dev, &qce->dma); 230 if (ret) 231 return ret; 232 233 ret = qce_check_version(qce); 234 if (ret) 235 return ret; 236 237 ret = devm_mutex_init(qce->dev, &qce->lock); 238 if (ret) 239 return ret; 240 241 INIT_WORK(&qce->done_work, qce_req_done_work); 242 crypto_init_queue(&qce->queue, QCE_QUEUE_LENGTH); 243 244 qce->async_req_enqueue = qce_async_request_enqueue; 245 qce->async_req_done = qce_async_request_done; 246 247 return devm_qce_register_algs(qce); 248 } 249 250 static const struct of_device_id qce_crypto_of_match[] = { 251 { .compatible = "qcom,crypto-v5.1", }, 252 { .compatible = "qcom,crypto-v5.4", }, 253 { .compatible = "qcom,qce", }, 254 {} 255 }; 256 MODULE_DEVICE_TABLE(of, qce_crypto_of_match); 257 258 static struct platform_driver qce_crypto_driver = { 259 .probe = qce_crypto_probe, 260 .driver = { 261 .name = KBUILD_MODNAME, 262 .of_match_table = qce_crypto_of_match, 263 }, 264 }; 265 module_platform_driver(qce_crypto_driver); 266 267 MODULE_LICENSE("GPL v2"); 268 MODULE_DESCRIPTION("Qualcomm crypto engine driver"); 269 MODULE_ALIAS("platform:" KBUILD_MODNAME); 270 MODULE_AUTHOR("The Linux Foundation"); 271