1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <crypto/internal/hash.h> 7 #include <linux/err.h> 8 #include <linux/interrupt.h> 9 #include <linux/types.h> 10 #include <crypto/scatterwalk.h> 11 #include <crypto/sha2.h> 12 13 #include "cipher.h" 14 #include "common.h" 15 #include "core.h" 16 #include "regs-v5.h" 17 #include "sha.h" 18 #include "aead.h" 19 20 static inline u32 qce_read(struct qce_device *qce, u32 offset) 21 { 22 return readl(qce->base + offset); 23 } 24 25 static inline void qce_write(struct qce_device *qce, u32 offset, u32 val) 26 { 27 writel(val, qce->base + offset); 28 } 29 30 static inline void qce_write_array(struct qce_device *qce, u32 offset, 31 const u32 *val, unsigned int len) 32 { 33 int i; 34 35 for (i = 0; i < len; i++) 36 qce_write(qce, offset + i * sizeof(u32), val[i]); 37 } 38 39 static inline void 40 qce_clear_array(struct qce_device *qce, u32 offset, unsigned int len) 41 { 42 int i; 43 44 for (i = 0; i < len; i++) 45 qce_write(qce, offset + i * sizeof(u32), 0); 46 } 47 48 static u32 qce_config_reg(struct qce_device *qce, int little) 49 { 50 u32 beats = (qce->burst_size >> 3) - 1; 51 u32 pipe_pair = qce->pipe_pair_id; 52 u32 config; 53 54 config = (beats << REQ_SIZE_SHIFT) & REQ_SIZE_MASK; 55 config |= BIT(MASK_DOUT_INTR_SHIFT) | BIT(MASK_DIN_INTR_SHIFT) | 56 BIT(MASK_OP_DONE_INTR_SHIFT) | BIT(MASK_ERR_INTR_SHIFT); 57 config |= (pipe_pair << PIPE_SET_SELECT_SHIFT) & PIPE_SET_SELECT_MASK; 58 config &= ~HIGH_SPD_EN_N_SHIFT; 59 60 if (little) 61 config |= BIT(LITTLE_ENDIAN_MODE_SHIFT); 62 63 return config; 64 } 65 66 void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len) 67 { 68 __be32 *d = dst; 69 const u8 *s = src; 70 unsigned int n; 71 72 n = len / sizeof(u32); 73 for (; n > 0; n--) { 74 *d = cpu_to_be32p((const __u32 *) s); 75 s += sizeof(__u32); 76 d++; 77 } 78 } 79 80 static void qce_setup_config(struct qce_device *qce) 81 { 82 u32 config; 83 84 /* get big endianness */ 85 config = qce_config_reg(qce, 0); 86 87 /* clear status */ 88 qce_write(qce, REG_STATUS, 0); 89 qce_write(qce, REG_CONFIG, config); 90 } 91 92 static inline void qce_crypto_go(struct qce_device *qce, bool result_dump) 93 { 94 if (result_dump) 95 qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT)); 96 else 97 qce_write(qce, REG_GOPROC, BIT(GO_SHIFT)); 98 } 99 100 #if defined(CONFIG_CRYPTO_DEV_QCE_SHA) || defined(CONFIG_CRYPTO_DEV_QCE_AEAD) 101 static u32 qce_auth_cfg(unsigned long flags, u32 key_size, u32 auth_size) 102 { 103 u32 cfg = 0; 104 105 if (IS_CCM(flags) || IS_CMAC(flags)) 106 cfg |= AUTH_ALG_AES << AUTH_ALG_SHIFT; 107 else 108 cfg |= AUTH_ALG_SHA << AUTH_ALG_SHIFT; 109 110 if (IS_CCM(flags) || IS_CMAC(flags)) { 111 if (key_size == AES_KEYSIZE_128) 112 cfg |= AUTH_KEY_SZ_AES128 << AUTH_KEY_SIZE_SHIFT; 113 else if (key_size == AES_KEYSIZE_256) 114 cfg |= AUTH_KEY_SZ_AES256 << AUTH_KEY_SIZE_SHIFT; 115 } 116 117 if (IS_SHA256(flags) || IS_SHA256_HMAC(flags)) 118 cfg |= AUTH_SIZE_SHA256 << AUTH_SIZE_SHIFT; 119 else if (IS_CMAC(flags)) 120 cfg |= AUTH_SIZE_ENUM_16_BYTES << AUTH_SIZE_SHIFT; 121 else if (IS_CCM(flags)) 122 cfg |= (auth_size - 1) << AUTH_SIZE_SHIFT; 123 124 if (IS_SHA256(flags)) 125 cfg |= AUTH_MODE_HASH << AUTH_MODE_SHIFT; 126 else if (IS_SHA256_HMAC(flags)) 127 cfg |= AUTH_MODE_HMAC << AUTH_MODE_SHIFT; 128 else if (IS_CCM(flags)) 129 cfg |= AUTH_MODE_CCM << AUTH_MODE_SHIFT; 130 else if (IS_CMAC(flags)) 131 cfg |= AUTH_MODE_CMAC << AUTH_MODE_SHIFT; 132 133 if (IS_SHA(flags) || IS_SHA_HMAC(flags)) 134 cfg |= AUTH_POS_BEFORE << AUTH_POS_SHIFT; 135 136 if (IS_CCM(flags)) 137 cfg |= QCE_MAX_NONCE_WORDS << AUTH_NONCE_NUM_WORDS_SHIFT; 138 139 return cfg; 140 } 141 #endif 142 143 #ifdef CONFIG_CRYPTO_DEV_QCE_SHA 144 static int qce_setup_regs_ahash(struct crypto_async_request *async_req) 145 { 146 struct ahash_request *req = ahash_request_cast(async_req); 147 struct crypto_ahash *ahash = __crypto_ahash_cast(async_req->tfm); 148 struct qce_sha_reqctx *rctx = ahash_request_ctx_dma(req); 149 struct qce_alg_template *tmpl = to_ahash_tmpl(async_req->tfm); 150 struct qce_device *qce = tmpl->qce; 151 unsigned int digestsize = crypto_ahash_digestsize(ahash); 152 unsigned int blocksize = crypto_tfm_alg_blocksize(async_req->tfm); 153 __be32 auth[SHA256_DIGEST_SIZE / sizeof(__be32)] = {0}; 154 __be32 mackey[QCE_SHA_HMAC_KEY_SIZE / sizeof(__be32)] = {0}; 155 u32 auth_cfg = 0, config; 156 unsigned int iv_words; 157 158 /* if not the last, the size has to be on the block boundary */ 159 if (!rctx->last_blk && req->nbytes % blocksize) 160 return -EINVAL; 161 162 qce_setup_config(qce); 163 164 if (IS_CMAC(rctx->flags)) { 165 qce_write(qce, REG_AUTH_SEG_CFG, 0); 166 qce_write(qce, REG_ENCR_SEG_CFG, 0); 167 qce_write(qce, REG_ENCR_SEG_SIZE, 0); 168 qce_clear_array(qce, REG_AUTH_IV0, 16); 169 qce_clear_array(qce, REG_AUTH_KEY0, 16); 170 qce_clear_array(qce, REG_AUTH_BYTECNT0, 4); 171 172 auth_cfg = qce_auth_cfg(rctx->flags, rctx->authklen, digestsize); 173 } 174 175 if (IS_SHA_HMAC(rctx->flags) || IS_CMAC(rctx->flags)) { 176 u32 authkey_words = rctx->authklen / sizeof(u32); 177 178 qce_cpu_to_be32p_array(mackey, rctx->authkey, rctx->authklen); 179 qce_write_array(qce, REG_AUTH_KEY0, (u32 *)mackey, 180 authkey_words); 181 } 182 183 if (IS_CMAC(rctx->flags)) 184 goto go_proc; 185 186 if (rctx->first_blk) 187 memcpy(auth, rctx->digest, digestsize); 188 else 189 qce_cpu_to_be32p_array(auth, rctx->digest, digestsize); 190 191 iv_words = 8; 192 qce_write_array(qce, REG_AUTH_IV0, (u32 *)auth, iv_words); 193 194 if (rctx->first_blk) 195 qce_clear_array(qce, REG_AUTH_BYTECNT0, 4); 196 else 197 qce_write_array(qce, REG_AUTH_BYTECNT0, 198 (u32 *)rctx->byte_count, 2); 199 200 auth_cfg = qce_auth_cfg(rctx->flags, 0, digestsize); 201 202 if (rctx->last_blk) 203 auth_cfg |= BIT(AUTH_LAST_SHIFT); 204 else 205 auth_cfg &= ~BIT(AUTH_LAST_SHIFT); 206 207 if (rctx->first_blk) 208 auth_cfg |= BIT(AUTH_FIRST_SHIFT); 209 else 210 auth_cfg &= ~BIT(AUTH_FIRST_SHIFT); 211 212 go_proc: 213 qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg); 214 qce_write(qce, REG_AUTH_SEG_SIZE, req->nbytes); 215 qce_write(qce, REG_AUTH_SEG_START, 0); 216 qce_write(qce, REG_ENCR_SEG_CFG, 0); 217 qce_write(qce, REG_SEG_SIZE, req->nbytes); 218 219 /* get little endianness */ 220 config = qce_config_reg(qce, 1); 221 qce_write(qce, REG_CONFIG, config); 222 223 qce_crypto_go(qce, true); 224 225 return 0; 226 } 227 #endif 228 229 #if defined(CONFIG_CRYPTO_DEV_QCE_SKCIPHER) || defined(CONFIG_CRYPTO_DEV_QCE_AEAD) 230 static u32 qce_encr_cfg(unsigned long flags, u32 aes_key_size) 231 { 232 u32 cfg = 0; 233 234 if (IS_AES(flags)) { 235 if (aes_key_size == AES_KEYSIZE_128) 236 cfg |= ENCR_KEY_SZ_AES128 << ENCR_KEY_SZ_SHIFT; 237 else if (aes_key_size == AES_KEYSIZE_256) 238 cfg |= ENCR_KEY_SZ_AES256 << ENCR_KEY_SZ_SHIFT; 239 } 240 241 if (IS_AES(flags)) 242 cfg |= ENCR_ALG_AES << ENCR_ALG_SHIFT; 243 244 switch (flags & QCE_MODE_MASK) { 245 case QCE_MODE_CBC: 246 cfg |= ENCR_MODE_CBC << ENCR_MODE_SHIFT; 247 break; 248 case QCE_MODE_CTR: 249 cfg |= ENCR_MODE_CTR << ENCR_MODE_SHIFT; 250 break; 251 case QCE_MODE_XTS: 252 cfg |= ENCR_MODE_XTS << ENCR_MODE_SHIFT; 253 break; 254 case QCE_MODE_CCM: 255 cfg |= ENCR_MODE_CCM << ENCR_MODE_SHIFT; 256 cfg |= LAST_CCM_XFR << LAST_CCM_SHIFT; 257 break; 258 default: 259 return ~0; 260 } 261 262 return cfg; 263 } 264 #endif 265 266 #ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER 267 static void qce_xts_swapiv(__be32 *dst, const u8 *src, unsigned int ivsize) 268 { 269 u8 swap[QCE_AES_IV_LENGTH] = {0}; 270 unsigned int i, offset; 271 272 if (ivsize > QCE_AES_IV_LENGTH) 273 return; 274 275 offset = QCE_AES_IV_LENGTH - ivsize; 276 277 /* Reverse and right-align IV bytes. */ 278 for (i = 0; i < ivsize; i++) 279 swap[offset + i] = src[ivsize - 1 - i]; 280 281 qce_cpu_to_be32p_array(dst, swap, QCE_AES_IV_LENGTH); 282 } 283 284 static void qce_xtskey(struct qce_device *qce, const u8 *enckey, 285 unsigned int enckeylen, unsigned int cryptlen) 286 { 287 u32 xtskey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(u32)] = {0}; 288 unsigned int xtsklen = enckeylen / (2 * sizeof(u32)); 289 290 qce_cpu_to_be32p_array((__be32 *)xtskey, enckey + enckeylen / 2, 291 enckeylen / 2); 292 qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen); 293 294 /* Set data unit size to cryptlen. Anything else causes 295 * crypto engine to return back incorrect results. 296 */ 297 qce_write(qce, REG_ENCR_XTS_DU_SIZE, cryptlen); 298 } 299 300 static int qce_setup_regs_skcipher(struct crypto_async_request *async_req) 301 { 302 struct skcipher_request *req = skcipher_request_cast(async_req); 303 struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req); 304 struct qce_cipher_ctx *ctx = crypto_tfm_ctx(async_req->tfm); 305 struct qce_alg_template *tmpl = to_cipher_tmpl(crypto_skcipher_reqtfm(req)); 306 struct qce_device *qce = tmpl->qce; 307 __be32 enckey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(__be32)] = {0}; 308 __be32 enciv[QCE_MAX_IV_SIZE / sizeof(__be32)] = {0}; 309 unsigned int enckey_words, enciv_words; 310 unsigned int keylen; 311 u32 encr_cfg = 0, auth_cfg = 0, config; 312 unsigned int ivsize = rctx->ivsize; 313 unsigned long flags = rctx->flags; 314 315 qce_setup_config(qce); 316 317 if (IS_XTS(flags)) 318 keylen = ctx->enc_keylen / 2; 319 else 320 keylen = ctx->enc_keylen; 321 322 qce_cpu_to_be32p_array(enckey, ctx->enc_key, keylen); 323 enckey_words = keylen / sizeof(u32); 324 325 qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg); 326 327 encr_cfg = qce_encr_cfg(flags, keylen); 328 329 if (IS_AES(flags)) { 330 if (IS_XTS(flags)) 331 qce_xtskey(qce, ctx->enc_key, ctx->enc_keylen, 332 rctx->cryptlen); 333 enciv_words = 4; 334 } else { 335 return -EINVAL; 336 } 337 338 qce_write_array(qce, REG_ENCR_KEY0, (u32 *)enckey, enckey_words); 339 340 if (IS_XTS(flags)) 341 qce_xts_swapiv(enciv, rctx->iv, ivsize); 342 else 343 qce_cpu_to_be32p_array(enciv, rctx->iv, ivsize); 344 345 qce_write_array(qce, REG_CNTR0_IV0, (u32 *)enciv, enciv_words); 346 347 if (IS_ENCRYPT(flags)) 348 encr_cfg |= BIT(ENCODE_SHIFT); 349 350 qce_write(qce, REG_ENCR_SEG_CFG, encr_cfg); 351 qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen); 352 qce_write(qce, REG_ENCR_SEG_START, 0); 353 354 if (IS_CTR(flags)) { 355 qce_write(qce, REG_CNTR_MASK, ~0); 356 qce_write(qce, REG_CNTR_MASK0, ~0); 357 qce_write(qce, REG_CNTR_MASK1, ~0); 358 qce_write(qce, REG_CNTR_MASK2, ~0); 359 } 360 361 qce_write(qce, REG_SEG_SIZE, rctx->cryptlen); 362 363 /* get little endianness */ 364 config = qce_config_reg(qce, 1); 365 qce_write(qce, REG_CONFIG, config); 366 367 qce_crypto_go(qce, true); 368 369 return 0; 370 } 371 #endif 372 373 #ifdef CONFIG_CRYPTO_DEV_QCE_AEAD 374 static const u32 std_iv_sha256[SHA256_DIGEST_SIZE / sizeof(u32)] = { 375 SHA256_H0, SHA256_H1, SHA256_H2, SHA256_H3, 376 SHA256_H4, SHA256_H5, SHA256_H6, SHA256_H7 377 }; 378 379 static unsigned int qce_be32_to_cpu_array(u32 *dst, const u8 *src, unsigned int len) 380 { 381 u32 *d = dst; 382 const u8 *s = src; 383 unsigned int n; 384 385 n = len / sizeof(u32); 386 for (; n > 0; n--) { 387 *d = be32_to_cpup((const __be32 *)s); 388 s += sizeof(u32); 389 d++; 390 } 391 return DIV_ROUND_UP(len, sizeof(u32)); 392 } 393 394 static int qce_setup_regs_aead(struct crypto_async_request *async_req) 395 { 396 struct aead_request *req = aead_request_cast(async_req); 397 struct qce_aead_reqctx *rctx = aead_request_ctx_dma(req); 398 struct qce_aead_ctx *ctx = crypto_tfm_ctx(async_req->tfm); 399 struct qce_alg_template *tmpl = to_aead_tmpl(crypto_aead_reqtfm(req)); 400 struct qce_device *qce = tmpl->qce; 401 u32 enckey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(u32)] = {0}; 402 u32 enciv[QCE_MAX_IV_SIZE / sizeof(u32)] = {0}; 403 u32 authkey[QCE_SHA_HMAC_KEY_SIZE / sizeof(u32)] = {0}; 404 u32 authiv[SHA256_DIGEST_SIZE / sizeof(u32)] = {0}; 405 u32 authnonce[QCE_MAX_NONCE / sizeof(u32)] = {0}; 406 unsigned int enc_keylen = ctx->enc_keylen; 407 unsigned int auth_keylen = ctx->auth_keylen; 408 unsigned int enc_ivsize = rctx->ivsize; 409 unsigned int auth_ivsize = 0; 410 unsigned int enckey_words, enciv_words; 411 unsigned int authkey_words, authiv_words, authnonce_words; 412 unsigned long flags = rctx->flags; 413 u32 encr_cfg, auth_cfg, config, totallen; 414 u32 iv_last_word; 415 416 qce_setup_config(qce); 417 418 /* Write encryption key */ 419 enckey_words = qce_be32_to_cpu_array(enckey, ctx->enc_key, enc_keylen); 420 qce_write_array(qce, REG_ENCR_KEY0, enckey, enckey_words); 421 422 /* Write encryption iv */ 423 enciv_words = qce_be32_to_cpu_array(enciv, rctx->iv, enc_ivsize); 424 qce_write_array(qce, REG_CNTR0_IV0, enciv, enciv_words); 425 426 if (IS_CCM(rctx->flags)) { 427 iv_last_word = enciv[enciv_words - 1]; 428 qce_write(qce, REG_CNTR3_IV3, iv_last_word + 1); 429 qce_write_array(qce, REG_ENCR_CCM_INT_CNTR0, (u32 *)enciv, enciv_words); 430 qce_write(qce, REG_CNTR_MASK, ~0); 431 qce_write(qce, REG_CNTR_MASK0, ~0); 432 qce_write(qce, REG_CNTR_MASK1, ~0); 433 qce_write(qce, REG_CNTR_MASK2, ~0); 434 } 435 436 /* Clear authentication IV and KEY registers of previous values */ 437 qce_clear_array(qce, REG_AUTH_IV0, 16); 438 qce_clear_array(qce, REG_AUTH_KEY0, 16); 439 440 /* Clear byte count */ 441 qce_clear_array(qce, REG_AUTH_BYTECNT0, 4); 442 443 /* Write authentication key */ 444 authkey_words = qce_be32_to_cpu_array(authkey, ctx->auth_key, auth_keylen); 445 qce_write_array(qce, REG_AUTH_KEY0, (u32 *)authkey, authkey_words); 446 447 /* Write initial authentication IV only for HMAC algorithms */ 448 if (IS_SHA_HMAC(rctx->flags)) { 449 /* Write default authentication iv */ 450 auth_ivsize = SHA256_DIGEST_SIZE; 451 memcpy(authiv, std_iv_sha256, auth_ivsize); 452 authiv_words = auth_ivsize / sizeof(u32); 453 qce_write_array(qce, REG_AUTH_IV0, (u32 *)authiv, authiv_words); 454 } else if (IS_CCM(rctx->flags)) { 455 /* Write nonce for CCM algorithms */ 456 authnonce_words = qce_be32_to_cpu_array(authnonce, rctx->ccm_nonce, QCE_MAX_NONCE); 457 qce_write_array(qce, REG_AUTH_INFO_NONCE0, authnonce, authnonce_words); 458 } 459 460 /* Set up ENCR_SEG_CFG */ 461 encr_cfg = qce_encr_cfg(flags, enc_keylen); 462 if (IS_ENCRYPT(flags)) 463 encr_cfg |= BIT(ENCODE_SHIFT); 464 qce_write(qce, REG_ENCR_SEG_CFG, encr_cfg); 465 466 /* Set up AUTH_SEG_CFG */ 467 auth_cfg = qce_auth_cfg(rctx->flags, auth_keylen, ctx->authsize); 468 auth_cfg |= BIT(AUTH_LAST_SHIFT); 469 auth_cfg |= BIT(AUTH_FIRST_SHIFT); 470 if (IS_ENCRYPT(flags)) { 471 if (IS_CCM(rctx->flags)) 472 auth_cfg |= AUTH_POS_BEFORE << AUTH_POS_SHIFT; 473 else 474 auth_cfg |= AUTH_POS_AFTER << AUTH_POS_SHIFT; 475 } else { 476 if (IS_CCM(rctx->flags)) 477 auth_cfg |= AUTH_POS_AFTER << AUTH_POS_SHIFT; 478 else 479 auth_cfg |= AUTH_POS_BEFORE << AUTH_POS_SHIFT; 480 } 481 qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg); 482 483 totallen = rctx->cryptlen + rctx->assoclen; 484 485 /* Set the encryption size and start offset */ 486 if (IS_CCM(rctx->flags) && IS_DECRYPT(rctx->flags)) 487 qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen + ctx->authsize); 488 else 489 qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen); 490 qce_write(qce, REG_ENCR_SEG_START, rctx->assoclen & 0xffff); 491 492 /* Set the authentication size and start offset */ 493 qce_write(qce, REG_AUTH_SEG_SIZE, totallen); 494 qce_write(qce, REG_AUTH_SEG_START, 0); 495 496 /* Write total length */ 497 if (IS_CCM(rctx->flags) && IS_DECRYPT(rctx->flags)) 498 qce_write(qce, REG_SEG_SIZE, totallen + ctx->authsize); 499 else 500 qce_write(qce, REG_SEG_SIZE, totallen); 501 502 /* get little endianness */ 503 config = qce_config_reg(qce, 1); 504 qce_write(qce, REG_CONFIG, config); 505 506 /* Start the process */ 507 qce_crypto_go(qce, !IS_CCM(flags)); 508 509 return 0; 510 } 511 #endif 512 513 int qce_start(struct crypto_async_request *async_req, u32 type) 514 { 515 switch (type) { 516 #ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER 517 case CRYPTO_ALG_TYPE_SKCIPHER: 518 return qce_setup_regs_skcipher(async_req); 519 #endif 520 #ifdef CONFIG_CRYPTO_DEV_QCE_SHA 521 case CRYPTO_ALG_TYPE_AHASH: 522 return qce_setup_regs_ahash(async_req); 523 #endif 524 #ifdef CONFIG_CRYPTO_DEV_QCE_AEAD 525 case CRYPTO_ALG_TYPE_AEAD: 526 return qce_setup_regs_aead(async_req); 527 #endif 528 default: 529 return -EINVAL; 530 } 531 } 532 533 #define STATUS_ERRORS \ 534 (BIT(SW_ERR_SHIFT) | BIT(AXI_ERR_SHIFT) | BIT(HSD_ERR_SHIFT)) 535 536 int qce_check_status(struct qce_device *qce, u32 *status) 537 { 538 int ret = 0; 539 540 *status = qce_read(qce, REG_STATUS); 541 542 /* 543 * Don't use result dump status. The operation may not be complete. 544 * Instead, use the status we just read from device. In case, we need to 545 * use result_status from result dump the result_status needs to be byte 546 * swapped, since we set the device to little endian. 547 */ 548 if (*status & STATUS_ERRORS || !(*status & BIT(OPERATION_DONE_SHIFT))) 549 ret = -ENXIO; 550 else if (*status & BIT(MAC_FAILED_SHIFT)) 551 ret = -EBADMSG; 552 553 return ret; 554 } 555 556 void qce_get_version(struct qce_device *qce, u32 *major, u32 *minor, u32 *step) 557 { 558 u32 val; 559 560 val = qce_read(qce, REG_VERSION); 561 *major = (val & CORE_MAJOR_REV_MASK) >> CORE_MAJOR_REV_SHIFT; 562 *minor = (val & CORE_MINOR_REV_MASK) >> CORE_MINOR_REV_SHIFT; 563 *step = (val & CORE_STEP_REV_MASK) >> CORE_STEP_REV_SHIFT; 564 } 565