1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Cryptographic API. 4 * 5 * Support for OMAP SHA1/MD5 HW acceleration. 6 * 7 * Copyright (c) 2010 Nokia Corporation 8 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> 9 * Copyright (c) 2011 Texas Instruments Incorporated 10 * 11 * Some ideas are from old omap-sha1-md5.c driver. 12 */ 13 14 #define pr_fmt(fmt) "%s: " fmt, __func__ 15 16 #include <linux/err.h> 17 #include <linux/device.h> 18 #include <linux/module.h> 19 #include <linux/init.h> 20 #include <linux/errno.h> 21 #include <linux/interrupt.h> 22 #include <linux/kernel.h> 23 #include <linux/irq.h> 24 #include <linux/io.h> 25 #include <linux/platform_device.h> 26 #include <linux/scatterlist.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/dmaengine.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/of.h> 31 #include <linux/of_device.h> 32 #include <linux/of_address.h> 33 #include <linux/of_irq.h> 34 #include <linux/delay.h> 35 #include <linux/crypto.h> 36 #include <crypto/scatterwalk.h> 37 #include <crypto/algapi.h> 38 #include <crypto/sha.h> 39 #include <crypto/hash.h> 40 #include <crypto/hmac.h> 41 #include <crypto/internal/hash.h> 42 43 #define MD5_DIGEST_SIZE 16 44 45 #define SHA_REG_IDIGEST(dd, x) ((dd)->pdata->idigest_ofs + ((x)*0x04)) 46 #define SHA_REG_DIN(dd, x) ((dd)->pdata->din_ofs + ((x) * 0x04)) 47 #define SHA_REG_DIGCNT(dd) ((dd)->pdata->digcnt_ofs) 48 49 #define SHA_REG_ODIGEST(dd, x) ((dd)->pdata->odigest_ofs + (x * 0x04)) 50 51 #define SHA_REG_CTRL 0x18 52 #define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5) 53 #define SHA_REG_CTRL_CLOSE_HASH (1 << 4) 54 #define SHA_REG_CTRL_ALGO_CONST (1 << 3) 55 #define SHA_REG_CTRL_ALGO (1 << 2) 56 #define SHA_REG_CTRL_INPUT_READY (1 << 1) 57 #define SHA_REG_CTRL_OUTPUT_READY (1 << 0) 58 59 #define SHA_REG_REV(dd) ((dd)->pdata->rev_ofs) 60 61 #define SHA_REG_MASK(dd) ((dd)->pdata->mask_ofs) 62 #define SHA_REG_MASK_DMA_EN (1 << 3) 63 #define SHA_REG_MASK_IT_EN (1 << 2) 64 #define SHA_REG_MASK_SOFTRESET (1 << 1) 65 #define SHA_REG_AUTOIDLE (1 << 0) 66 67 #define SHA_REG_SYSSTATUS(dd) ((dd)->pdata->sysstatus_ofs) 68 #define SHA_REG_SYSSTATUS_RESETDONE (1 << 0) 69 70 #define SHA_REG_MODE(dd) ((dd)->pdata->mode_ofs) 71 #define SHA_REG_MODE_HMAC_OUTER_HASH (1 << 7) 72 #define SHA_REG_MODE_HMAC_KEY_PROC (1 << 5) 73 #define SHA_REG_MODE_CLOSE_HASH (1 << 4) 74 #define SHA_REG_MODE_ALGO_CONSTANT (1 << 3) 75 76 #define SHA_REG_MODE_ALGO_MASK (7 << 0) 77 #define SHA_REG_MODE_ALGO_MD5_128 (0 << 1) 78 #define SHA_REG_MODE_ALGO_SHA1_160 (1 << 1) 79 #define SHA_REG_MODE_ALGO_SHA2_224 (2 << 1) 80 #define SHA_REG_MODE_ALGO_SHA2_256 (3 << 1) 81 #define SHA_REG_MODE_ALGO_SHA2_384 (1 << 0) 82 #define SHA_REG_MODE_ALGO_SHA2_512 (3 << 0) 83 84 #define SHA_REG_LENGTH(dd) ((dd)->pdata->length_ofs) 85 86 #define SHA_REG_IRQSTATUS 0x118 87 #define SHA_REG_IRQSTATUS_CTX_RDY (1 << 3) 88 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2) 89 #define SHA_REG_IRQSTATUS_INPUT_RDY (1 << 1) 90 #define SHA_REG_IRQSTATUS_OUTPUT_RDY (1 << 0) 91 92 #define SHA_REG_IRQENA 0x11C 93 #define SHA_REG_IRQENA_CTX_RDY (1 << 3) 94 #define SHA_REG_IRQENA_PARTHASH_RDY (1 << 2) 95 #define SHA_REG_IRQENA_INPUT_RDY (1 << 1) 96 #define SHA_REG_IRQENA_OUTPUT_RDY (1 << 0) 97 98 #define DEFAULT_TIMEOUT_INTERVAL HZ 99 100 #define DEFAULT_AUTOSUSPEND_DELAY 1000 101 102 /* mostly device flags */ 103 #define FLAGS_BUSY 0 104 #define FLAGS_FINAL 1 105 #define FLAGS_DMA_ACTIVE 2 106 #define FLAGS_OUTPUT_READY 3 107 #define FLAGS_INIT 4 108 #define FLAGS_CPU 5 109 #define FLAGS_DMA_READY 6 110 #define FLAGS_AUTO_XOR 7 111 #define FLAGS_BE32_SHA1 8 112 #define FLAGS_SGS_COPIED 9 113 #define FLAGS_SGS_ALLOCED 10 114 #define FLAGS_HUGE 11 115 116 /* context flags */ 117 #define FLAGS_FINUP 16 118 119 #define FLAGS_MODE_SHIFT 18 120 #define FLAGS_MODE_MASK (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT) 121 #define FLAGS_MODE_MD5 (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT) 122 #define FLAGS_MODE_SHA1 (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT) 123 #define FLAGS_MODE_SHA224 (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT) 124 #define FLAGS_MODE_SHA256 (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT) 125 #define FLAGS_MODE_SHA384 (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT) 126 #define FLAGS_MODE_SHA512 (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT) 127 128 #define FLAGS_HMAC 21 129 #define FLAGS_ERROR 22 130 131 #define OP_UPDATE 1 132 #define OP_FINAL 2 133 134 #define OMAP_ALIGN_MASK (sizeof(u32)-1) 135 #define OMAP_ALIGNED __attribute__((aligned(sizeof(u32)))) 136 137 #define BUFLEN SHA512_BLOCK_SIZE 138 #define OMAP_SHA_DMA_THRESHOLD 256 139 140 #define OMAP_SHA_MAX_DMA_LEN (1024 * 2048) 141 142 struct omap_sham_dev; 143 144 struct omap_sham_reqctx { 145 struct omap_sham_dev *dd; 146 unsigned long flags; 147 unsigned long op; 148 149 u8 digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED; 150 size_t digcnt; 151 size_t bufcnt; 152 size_t buflen; 153 154 /* walk state */ 155 struct scatterlist *sg; 156 struct scatterlist sgl[2]; 157 int offset; /* offset in current sg */ 158 int sg_len; 159 unsigned int total; /* total request */ 160 161 u8 buffer[] OMAP_ALIGNED; 162 }; 163 164 struct omap_sham_hmac_ctx { 165 struct crypto_shash *shash; 166 u8 ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED; 167 u8 opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED; 168 }; 169 170 struct omap_sham_ctx { 171 struct omap_sham_dev *dd; 172 173 unsigned long flags; 174 175 /* fallback stuff */ 176 struct crypto_shash *fallback; 177 178 struct omap_sham_hmac_ctx base[]; 179 }; 180 181 #define OMAP_SHAM_QUEUE_LENGTH 10 182 183 struct omap_sham_algs_info { 184 struct ahash_alg *algs_list; 185 unsigned int size; 186 unsigned int registered; 187 }; 188 189 struct omap_sham_pdata { 190 struct omap_sham_algs_info *algs_info; 191 unsigned int algs_info_size; 192 unsigned long flags; 193 int digest_size; 194 195 void (*copy_hash)(struct ahash_request *req, int out); 196 void (*write_ctrl)(struct omap_sham_dev *dd, size_t length, 197 int final, int dma); 198 void (*trigger)(struct omap_sham_dev *dd, size_t length); 199 int (*poll_irq)(struct omap_sham_dev *dd); 200 irqreturn_t (*intr_hdlr)(int irq, void *dev_id); 201 202 u32 odigest_ofs; 203 u32 idigest_ofs; 204 u32 din_ofs; 205 u32 digcnt_ofs; 206 u32 rev_ofs; 207 u32 mask_ofs; 208 u32 sysstatus_ofs; 209 u32 mode_ofs; 210 u32 length_ofs; 211 212 u32 major_mask; 213 u32 major_shift; 214 u32 minor_mask; 215 u32 minor_shift; 216 }; 217 218 struct omap_sham_dev { 219 struct list_head list; 220 unsigned long phys_base; 221 struct device *dev; 222 void __iomem *io_base; 223 int irq; 224 spinlock_t lock; 225 int err; 226 struct dma_chan *dma_lch; 227 struct tasklet_struct done_task; 228 u8 polling_mode; 229 u8 xmit_buf[BUFLEN] OMAP_ALIGNED; 230 231 unsigned long flags; 232 int fallback_sz; 233 struct crypto_queue queue; 234 struct ahash_request *req; 235 236 const struct omap_sham_pdata *pdata; 237 }; 238 239 struct omap_sham_drv { 240 struct list_head dev_list; 241 spinlock_t lock; 242 unsigned long flags; 243 }; 244 245 static struct omap_sham_drv sham = { 246 .dev_list = LIST_HEAD_INIT(sham.dev_list), 247 .lock = __SPIN_LOCK_UNLOCKED(sham.lock), 248 }; 249 250 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset) 251 { 252 return __raw_readl(dd->io_base + offset); 253 } 254 255 static inline void omap_sham_write(struct omap_sham_dev *dd, 256 u32 offset, u32 value) 257 { 258 __raw_writel(value, dd->io_base + offset); 259 } 260 261 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address, 262 u32 value, u32 mask) 263 { 264 u32 val; 265 266 val = omap_sham_read(dd, address); 267 val &= ~mask; 268 val |= value; 269 omap_sham_write(dd, address, val); 270 } 271 272 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit) 273 { 274 unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL; 275 276 while (!(omap_sham_read(dd, offset) & bit)) { 277 if (time_is_before_jiffies(timeout)) 278 return -ETIMEDOUT; 279 } 280 281 return 0; 282 } 283 284 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out) 285 { 286 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 287 struct omap_sham_dev *dd = ctx->dd; 288 u32 *hash = (u32 *)ctx->digest; 289 int i; 290 291 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) { 292 if (out) 293 hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i)); 294 else 295 omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]); 296 } 297 } 298 299 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out) 300 { 301 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 302 struct omap_sham_dev *dd = ctx->dd; 303 int i; 304 305 if (ctx->flags & BIT(FLAGS_HMAC)) { 306 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req); 307 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); 308 struct omap_sham_hmac_ctx *bctx = tctx->base; 309 u32 *opad = (u32 *)bctx->opad; 310 311 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) { 312 if (out) 313 opad[i] = omap_sham_read(dd, 314 SHA_REG_ODIGEST(dd, i)); 315 else 316 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i), 317 opad[i]); 318 } 319 } 320 321 omap_sham_copy_hash_omap2(req, out); 322 } 323 324 static void omap_sham_copy_ready_hash(struct ahash_request *req) 325 { 326 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 327 u32 *in = (u32 *)ctx->digest; 328 u32 *hash = (u32 *)req->result; 329 int i, d, big_endian = 0; 330 331 if (!hash) 332 return; 333 334 switch (ctx->flags & FLAGS_MODE_MASK) { 335 case FLAGS_MODE_MD5: 336 d = MD5_DIGEST_SIZE / sizeof(u32); 337 break; 338 case FLAGS_MODE_SHA1: 339 /* OMAP2 SHA1 is big endian */ 340 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags)) 341 big_endian = 1; 342 d = SHA1_DIGEST_SIZE / sizeof(u32); 343 break; 344 case FLAGS_MODE_SHA224: 345 d = SHA224_DIGEST_SIZE / sizeof(u32); 346 break; 347 case FLAGS_MODE_SHA256: 348 d = SHA256_DIGEST_SIZE / sizeof(u32); 349 break; 350 case FLAGS_MODE_SHA384: 351 d = SHA384_DIGEST_SIZE / sizeof(u32); 352 break; 353 case FLAGS_MODE_SHA512: 354 d = SHA512_DIGEST_SIZE / sizeof(u32); 355 break; 356 default: 357 d = 0; 358 } 359 360 if (big_endian) 361 for (i = 0; i < d; i++) 362 hash[i] = be32_to_cpu(in[i]); 363 else 364 for (i = 0; i < d; i++) 365 hash[i] = le32_to_cpu(in[i]); 366 } 367 368 static int omap_sham_hw_init(struct omap_sham_dev *dd) 369 { 370 int err; 371 372 err = pm_runtime_get_sync(dd->dev); 373 if (err < 0) { 374 dev_err(dd->dev, "failed to get sync: %d\n", err); 375 return err; 376 } 377 378 if (!test_bit(FLAGS_INIT, &dd->flags)) { 379 set_bit(FLAGS_INIT, &dd->flags); 380 dd->err = 0; 381 } 382 383 return 0; 384 } 385 386 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length, 387 int final, int dma) 388 { 389 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 390 u32 val = length << 5, mask; 391 392 if (likely(ctx->digcnt)) 393 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt); 394 395 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 396 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0), 397 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN); 398 /* 399 * Setting ALGO_CONST only for the first iteration 400 * and CLOSE_HASH only for the last one. 401 */ 402 if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1) 403 val |= SHA_REG_CTRL_ALGO; 404 if (!ctx->digcnt) 405 val |= SHA_REG_CTRL_ALGO_CONST; 406 if (final) 407 val |= SHA_REG_CTRL_CLOSE_HASH; 408 409 mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH | 410 SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH; 411 412 omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask); 413 } 414 415 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length) 416 { 417 } 418 419 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd) 420 { 421 return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY); 422 } 423 424 static int get_block_size(struct omap_sham_reqctx *ctx) 425 { 426 int d; 427 428 switch (ctx->flags & FLAGS_MODE_MASK) { 429 case FLAGS_MODE_MD5: 430 case FLAGS_MODE_SHA1: 431 d = SHA1_BLOCK_SIZE; 432 break; 433 case FLAGS_MODE_SHA224: 434 case FLAGS_MODE_SHA256: 435 d = SHA256_BLOCK_SIZE; 436 break; 437 case FLAGS_MODE_SHA384: 438 case FLAGS_MODE_SHA512: 439 d = SHA512_BLOCK_SIZE; 440 break; 441 default: 442 d = 0; 443 } 444 445 return d; 446 } 447 448 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset, 449 u32 *value, int count) 450 { 451 for (; count--; value++, offset += 4) 452 omap_sham_write(dd, offset, *value); 453 } 454 455 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length, 456 int final, int dma) 457 { 458 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 459 u32 val, mask; 460 461 /* 462 * Setting ALGO_CONST only for the first iteration and 463 * CLOSE_HASH only for the last one. Note that flags mode bits 464 * correspond to algorithm encoding in mode register. 465 */ 466 val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT); 467 if (!ctx->digcnt) { 468 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req); 469 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); 470 struct omap_sham_hmac_ctx *bctx = tctx->base; 471 int bs, nr_dr; 472 473 val |= SHA_REG_MODE_ALGO_CONSTANT; 474 475 if (ctx->flags & BIT(FLAGS_HMAC)) { 476 bs = get_block_size(ctx); 477 nr_dr = bs / (2 * sizeof(u32)); 478 val |= SHA_REG_MODE_HMAC_KEY_PROC; 479 omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0), 480 (u32 *)bctx->ipad, nr_dr); 481 omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0), 482 (u32 *)bctx->ipad + nr_dr, nr_dr); 483 ctx->digcnt += bs; 484 } 485 } 486 487 if (final) { 488 val |= SHA_REG_MODE_CLOSE_HASH; 489 490 if (ctx->flags & BIT(FLAGS_HMAC)) 491 val |= SHA_REG_MODE_HMAC_OUTER_HASH; 492 } 493 494 mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH | 495 SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH | 496 SHA_REG_MODE_HMAC_KEY_PROC; 497 498 dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags); 499 omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask); 500 omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY); 501 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 502 SHA_REG_MASK_IT_EN | 503 (dma ? SHA_REG_MASK_DMA_EN : 0), 504 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN); 505 } 506 507 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length) 508 { 509 omap_sham_write(dd, SHA_REG_LENGTH(dd), length); 510 } 511 512 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd) 513 { 514 return omap_sham_wait(dd, SHA_REG_IRQSTATUS, 515 SHA_REG_IRQSTATUS_INPUT_RDY); 516 } 517 518 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, size_t length, 519 int final) 520 { 521 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 522 int count, len32, bs32, offset = 0; 523 const u32 *buffer; 524 int mlen; 525 struct sg_mapping_iter mi; 526 527 dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n", 528 ctx->digcnt, length, final); 529 530 dd->pdata->write_ctrl(dd, length, final, 0); 531 dd->pdata->trigger(dd, length); 532 533 /* should be non-zero before next lines to disable clocks later */ 534 ctx->digcnt += length; 535 ctx->total -= length; 536 537 if (final) 538 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */ 539 540 set_bit(FLAGS_CPU, &dd->flags); 541 542 len32 = DIV_ROUND_UP(length, sizeof(u32)); 543 bs32 = get_block_size(ctx) / sizeof(u32); 544 545 sg_miter_start(&mi, ctx->sg, ctx->sg_len, 546 SG_MITER_FROM_SG | SG_MITER_ATOMIC); 547 548 mlen = 0; 549 550 while (len32) { 551 if (dd->pdata->poll_irq(dd)) 552 return -ETIMEDOUT; 553 554 for (count = 0; count < min(len32, bs32); count++, offset++) { 555 if (!mlen) { 556 sg_miter_next(&mi); 557 mlen = mi.length; 558 if (!mlen) { 559 pr_err("sg miter failure.\n"); 560 return -EINVAL; 561 } 562 offset = 0; 563 buffer = mi.addr; 564 } 565 omap_sham_write(dd, SHA_REG_DIN(dd, count), 566 buffer[offset]); 567 mlen -= 4; 568 } 569 len32 -= min(len32, bs32); 570 } 571 572 sg_miter_stop(&mi); 573 574 return -EINPROGRESS; 575 } 576 577 static void omap_sham_dma_callback(void *param) 578 { 579 struct omap_sham_dev *dd = param; 580 581 set_bit(FLAGS_DMA_READY, &dd->flags); 582 tasklet_schedule(&dd->done_task); 583 } 584 585 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, size_t length, 586 int final) 587 { 588 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 589 struct dma_async_tx_descriptor *tx; 590 struct dma_slave_config cfg; 591 int ret; 592 593 dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n", 594 ctx->digcnt, length, final); 595 596 if (!dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE)) { 597 dev_err(dd->dev, "dma_map_sg error\n"); 598 return -EINVAL; 599 } 600 601 memset(&cfg, 0, sizeof(cfg)); 602 603 cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0); 604 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 605 cfg.dst_maxburst = get_block_size(ctx) / DMA_SLAVE_BUSWIDTH_4_BYTES; 606 607 ret = dmaengine_slave_config(dd->dma_lch, &cfg); 608 if (ret) { 609 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret); 610 return ret; 611 } 612 613 tx = dmaengine_prep_slave_sg(dd->dma_lch, ctx->sg, ctx->sg_len, 614 DMA_MEM_TO_DEV, 615 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 616 617 if (!tx) { 618 dev_err(dd->dev, "prep_slave_sg failed\n"); 619 return -EINVAL; 620 } 621 622 tx->callback = omap_sham_dma_callback; 623 tx->callback_param = dd; 624 625 dd->pdata->write_ctrl(dd, length, final, 1); 626 627 ctx->digcnt += length; 628 ctx->total -= length; 629 630 if (final) 631 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */ 632 633 set_bit(FLAGS_DMA_ACTIVE, &dd->flags); 634 635 dmaengine_submit(tx); 636 dma_async_issue_pending(dd->dma_lch); 637 638 dd->pdata->trigger(dd, length); 639 640 return -EINPROGRESS; 641 } 642 643 static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx, 644 struct scatterlist *sg, int bs, int new_len) 645 { 646 int n = sg_nents(sg); 647 struct scatterlist *tmp; 648 int offset = ctx->offset; 649 650 ctx->total = new_len; 651 652 if (ctx->bufcnt) 653 n++; 654 655 ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL); 656 if (!ctx->sg) 657 return -ENOMEM; 658 659 sg_init_table(ctx->sg, n); 660 661 tmp = ctx->sg; 662 663 ctx->sg_len = 0; 664 665 if (ctx->bufcnt) { 666 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt); 667 tmp = sg_next(tmp); 668 ctx->sg_len++; 669 new_len -= ctx->bufcnt; 670 } 671 672 while (sg && new_len) { 673 int len = sg->length - offset; 674 675 if (len <= 0) { 676 offset -= sg->length; 677 sg = sg_next(sg); 678 continue; 679 } 680 681 if (new_len < len) 682 len = new_len; 683 684 if (len > 0) { 685 new_len -= len; 686 sg_set_page(tmp, sg_page(sg), len, sg->offset + offset); 687 offset = 0; 688 ctx->offset = 0; 689 ctx->sg_len++; 690 if (new_len <= 0) 691 break; 692 tmp = sg_next(tmp); 693 } 694 695 sg = sg_next(sg); 696 } 697 698 if (tmp) 699 sg_mark_end(tmp); 700 701 set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags); 702 703 ctx->offset += new_len - ctx->bufcnt; 704 ctx->bufcnt = 0; 705 706 return 0; 707 } 708 709 static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx, 710 struct scatterlist *sg, int bs, 711 unsigned int new_len) 712 { 713 int pages; 714 void *buf; 715 716 pages = get_order(new_len); 717 718 buf = (void *)__get_free_pages(GFP_ATOMIC, pages); 719 if (!buf) { 720 pr_err("Couldn't allocate pages for unaligned cases.\n"); 721 return -ENOMEM; 722 } 723 724 if (ctx->bufcnt) 725 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt); 726 727 scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset, 728 min(new_len, ctx->total) - ctx->bufcnt, 0); 729 sg_init_table(ctx->sgl, 1); 730 sg_set_buf(ctx->sgl, buf, new_len); 731 ctx->sg = ctx->sgl; 732 set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags); 733 ctx->sg_len = 1; 734 ctx->offset += new_len - ctx->bufcnt; 735 ctx->bufcnt = 0; 736 ctx->total = new_len; 737 738 return 0; 739 } 740 741 static int omap_sham_align_sgs(struct scatterlist *sg, 742 int nbytes, int bs, bool final, 743 struct omap_sham_reqctx *rctx) 744 { 745 int n = 0; 746 bool aligned = true; 747 bool list_ok = true; 748 struct scatterlist *sg_tmp = sg; 749 int new_len; 750 int offset = rctx->offset; 751 int bufcnt = rctx->bufcnt; 752 753 if (!sg || !sg->length || !nbytes) { 754 if (bufcnt) { 755 bufcnt = DIV_ROUND_UP(bufcnt, bs) * bs; 756 sg_init_table(rctx->sgl, 1); 757 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, bufcnt); 758 rctx->sg = rctx->sgl; 759 rctx->sg_len = 1; 760 } 761 762 return 0; 763 } 764 765 new_len = nbytes; 766 767 if (offset) 768 list_ok = false; 769 770 if (final) 771 new_len = DIV_ROUND_UP(new_len, bs) * bs; 772 else 773 new_len = (new_len - 1) / bs * bs; 774 775 if (!new_len) 776 return 0; 777 778 if (nbytes != new_len) 779 list_ok = false; 780 781 while (nbytes > 0 && sg_tmp) { 782 n++; 783 784 if (bufcnt) { 785 if (!IS_ALIGNED(bufcnt, bs)) { 786 aligned = false; 787 break; 788 } 789 nbytes -= bufcnt; 790 bufcnt = 0; 791 if (!nbytes) 792 list_ok = false; 793 794 continue; 795 } 796 797 #ifdef CONFIG_ZONE_DMA 798 if (page_zonenum(sg_page(sg_tmp)) != ZONE_DMA) { 799 aligned = false; 800 break; 801 } 802 #endif 803 804 if (offset < sg_tmp->length) { 805 if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) { 806 aligned = false; 807 break; 808 } 809 810 if (!IS_ALIGNED(sg_tmp->length - offset, bs)) { 811 aligned = false; 812 break; 813 } 814 } 815 816 if (offset) { 817 offset -= sg_tmp->length; 818 if (offset < 0) { 819 nbytes += offset; 820 offset = 0; 821 } 822 } else { 823 nbytes -= sg_tmp->length; 824 } 825 826 sg_tmp = sg_next(sg_tmp); 827 828 if (nbytes < 0) { 829 list_ok = false; 830 break; 831 } 832 } 833 834 if (new_len > OMAP_SHA_MAX_DMA_LEN) { 835 new_len = OMAP_SHA_MAX_DMA_LEN; 836 aligned = false; 837 } 838 839 if (!aligned) 840 return omap_sham_copy_sgs(rctx, sg, bs, new_len); 841 else if (!list_ok) 842 return omap_sham_copy_sg_lists(rctx, sg, bs, new_len); 843 844 rctx->total = new_len; 845 rctx->offset += new_len; 846 rctx->sg_len = n; 847 if (rctx->bufcnt) { 848 sg_init_table(rctx->sgl, 2); 849 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt); 850 sg_chain(rctx->sgl, 2, sg); 851 rctx->sg = rctx->sgl; 852 } else { 853 rctx->sg = sg; 854 } 855 856 return 0; 857 } 858 859 static int omap_sham_prepare_request(struct ahash_request *req, bool update) 860 { 861 struct omap_sham_reqctx *rctx = ahash_request_ctx(req); 862 int bs; 863 int ret; 864 unsigned int nbytes; 865 bool final = rctx->flags & BIT(FLAGS_FINUP); 866 int hash_later; 867 868 bs = get_block_size(rctx); 869 870 nbytes = rctx->bufcnt; 871 872 if (update) 873 nbytes += req->nbytes - rctx->offset; 874 875 dev_dbg(rctx->dd->dev, 876 "%s: nbytes=%d, bs=%d, total=%d, offset=%d, bufcnt=%d\n", 877 __func__, nbytes, bs, rctx->total, rctx->offset, 878 rctx->bufcnt); 879 880 if (!nbytes) 881 return 0; 882 883 rctx->total = nbytes; 884 885 if (update && req->nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) { 886 int len = bs - rctx->bufcnt % bs; 887 888 if (len > req->nbytes) 889 len = req->nbytes; 890 scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src, 891 0, len, 0); 892 rctx->bufcnt += len; 893 rctx->offset = len; 894 } 895 896 if (rctx->bufcnt) 897 memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt); 898 899 ret = omap_sham_align_sgs(req->src, nbytes, bs, final, rctx); 900 if (ret) 901 return ret; 902 903 hash_later = nbytes - rctx->total; 904 if (hash_later < 0) 905 hash_later = 0; 906 907 if (hash_later && hash_later <= rctx->buflen) { 908 scatterwalk_map_and_copy(rctx->buffer, 909 req->src, 910 req->nbytes - hash_later, 911 hash_later, 0); 912 913 rctx->bufcnt = hash_later; 914 } else { 915 rctx->bufcnt = 0; 916 } 917 918 if (hash_later > rctx->buflen) 919 set_bit(FLAGS_HUGE, &rctx->dd->flags); 920 921 rctx->total = min(nbytes, rctx->total); 922 923 return 0; 924 } 925 926 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd) 927 { 928 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 929 930 dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE); 931 932 clear_bit(FLAGS_DMA_ACTIVE, &dd->flags); 933 934 return 0; 935 } 936 937 static int omap_sham_init(struct ahash_request *req) 938 { 939 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 940 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); 941 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 942 struct omap_sham_dev *dd = NULL, *tmp; 943 int bs = 0; 944 945 spin_lock_bh(&sham.lock); 946 if (!tctx->dd) { 947 list_for_each_entry(tmp, &sham.dev_list, list) { 948 dd = tmp; 949 break; 950 } 951 tctx->dd = dd; 952 } else { 953 dd = tctx->dd; 954 } 955 spin_unlock_bh(&sham.lock); 956 957 ctx->dd = dd; 958 959 ctx->flags = 0; 960 961 dev_dbg(dd->dev, "init: digest size: %d\n", 962 crypto_ahash_digestsize(tfm)); 963 964 switch (crypto_ahash_digestsize(tfm)) { 965 case MD5_DIGEST_SIZE: 966 ctx->flags |= FLAGS_MODE_MD5; 967 bs = SHA1_BLOCK_SIZE; 968 break; 969 case SHA1_DIGEST_SIZE: 970 ctx->flags |= FLAGS_MODE_SHA1; 971 bs = SHA1_BLOCK_SIZE; 972 break; 973 case SHA224_DIGEST_SIZE: 974 ctx->flags |= FLAGS_MODE_SHA224; 975 bs = SHA224_BLOCK_SIZE; 976 break; 977 case SHA256_DIGEST_SIZE: 978 ctx->flags |= FLAGS_MODE_SHA256; 979 bs = SHA256_BLOCK_SIZE; 980 break; 981 case SHA384_DIGEST_SIZE: 982 ctx->flags |= FLAGS_MODE_SHA384; 983 bs = SHA384_BLOCK_SIZE; 984 break; 985 case SHA512_DIGEST_SIZE: 986 ctx->flags |= FLAGS_MODE_SHA512; 987 bs = SHA512_BLOCK_SIZE; 988 break; 989 } 990 991 ctx->bufcnt = 0; 992 ctx->digcnt = 0; 993 ctx->total = 0; 994 ctx->offset = 0; 995 ctx->buflen = BUFLEN; 996 997 if (tctx->flags & BIT(FLAGS_HMAC)) { 998 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) { 999 struct omap_sham_hmac_ctx *bctx = tctx->base; 1000 1001 memcpy(ctx->buffer, bctx->ipad, bs); 1002 ctx->bufcnt = bs; 1003 } 1004 1005 ctx->flags |= BIT(FLAGS_HMAC); 1006 } 1007 1008 return 0; 1009 1010 } 1011 1012 static int omap_sham_update_req(struct omap_sham_dev *dd) 1013 { 1014 struct ahash_request *req = dd->req; 1015 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1016 int err; 1017 bool final = (ctx->flags & BIT(FLAGS_FINUP)) && 1018 !(dd->flags & BIT(FLAGS_HUGE)); 1019 1020 dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, final: %d", 1021 ctx->total, ctx->digcnt, final); 1022 1023 if (ctx->total < get_block_size(ctx) || 1024 ctx->total < dd->fallback_sz) 1025 ctx->flags |= BIT(FLAGS_CPU); 1026 1027 if (ctx->flags & BIT(FLAGS_CPU)) 1028 err = omap_sham_xmit_cpu(dd, ctx->total, final); 1029 else 1030 err = omap_sham_xmit_dma(dd, ctx->total, final); 1031 1032 /* wait for dma completion before can take more data */ 1033 dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt); 1034 1035 return err; 1036 } 1037 1038 static int omap_sham_final_req(struct omap_sham_dev *dd) 1039 { 1040 struct ahash_request *req = dd->req; 1041 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1042 int err = 0, use_dma = 1; 1043 1044 if (dd->flags & BIT(FLAGS_HUGE)) 1045 return 0; 1046 1047 if ((ctx->total <= get_block_size(ctx)) || dd->polling_mode) 1048 /* 1049 * faster to handle last block with cpu or 1050 * use cpu when dma is not present. 1051 */ 1052 use_dma = 0; 1053 1054 if (use_dma) 1055 err = omap_sham_xmit_dma(dd, ctx->total, 1); 1056 else 1057 err = omap_sham_xmit_cpu(dd, ctx->total, 1); 1058 1059 ctx->bufcnt = 0; 1060 1061 dev_dbg(dd->dev, "final_req: err: %d\n", err); 1062 1063 return err; 1064 } 1065 1066 static int omap_sham_finish_hmac(struct ahash_request *req) 1067 { 1068 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 1069 struct omap_sham_hmac_ctx *bctx = tctx->base; 1070 int bs = crypto_shash_blocksize(bctx->shash); 1071 int ds = crypto_shash_digestsize(bctx->shash); 1072 SHASH_DESC_ON_STACK(shash, bctx->shash); 1073 1074 shash->tfm = bctx->shash; 1075 1076 return crypto_shash_init(shash) ?: 1077 crypto_shash_update(shash, bctx->opad, bs) ?: 1078 crypto_shash_finup(shash, req->result, ds, req->result); 1079 } 1080 1081 static int omap_sham_finish(struct ahash_request *req) 1082 { 1083 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1084 struct omap_sham_dev *dd = ctx->dd; 1085 int err = 0; 1086 1087 if (ctx->digcnt) { 1088 omap_sham_copy_ready_hash(req); 1089 if ((ctx->flags & BIT(FLAGS_HMAC)) && 1090 !test_bit(FLAGS_AUTO_XOR, &dd->flags)) 1091 err = omap_sham_finish_hmac(req); 1092 } 1093 1094 dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt); 1095 1096 return err; 1097 } 1098 1099 static void omap_sham_finish_req(struct ahash_request *req, int err) 1100 { 1101 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1102 struct omap_sham_dev *dd = ctx->dd; 1103 1104 if (test_bit(FLAGS_SGS_COPIED, &dd->flags)) 1105 free_pages((unsigned long)sg_virt(ctx->sg), 1106 get_order(ctx->sg->length)); 1107 1108 if (test_bit(FLAGS_SGS_ALLOCED, &dd->flags)) 1109 kfree(ctx->sg); 1110 1111 ctx->sg = NULL; 1112 1113 dd->flags &= ~(BIT(FLAGS_SGS_ALLOCED) | BIT(FLAGS_SGS_COPIED)); 1114 1115 if (dd->flags & BIT(FLAGS_HUGE)) { 1116 dd->flags &= ~(BIT(FLAGS_CPU) | BIT(FLAGS_DMA_READY) | 1117 BIT(FLAGS_OUTPUT_READY) | BIT(FLAGS_HUGE)); 1118 omap_sham_prepare_request(req, ctx->op == OP_UPDATE); 1119 if (ctx->op == OP_UPDATE || (dd->flags & BIT(FLAGS_HUGE))) { 1120 err = omap_sham_update_req(dd); 1121 if (err != -EINPROGRESS && 1122 (ctx->flags & BIT(FLAGS_FINUP))) 1123 err = omap_sham_final_req(dd); 1124 } else if (ctx->op == OP_FINAL) { 1125 omap_sham_final_req(dd); 1126 } 1127 return; 1128 } 1129 1130 if (!err) { 1131 dd->pdata->copy_hash(req, 1); 1132 if (test_bit(FLAGS_FINAL, &dd->flags)) 1133 err = omap_sham_finish(req); 1134 } else { 1135 ctx->flags |= BIT(FLAGS_ERROR); 1136 } 1137 1138 /* atomic operation is not needed here */ 1139 dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) | 1140 BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY)); 1141 1142 pm_runtime_mark_last_busy(dd->dev); 1143 pm_runtime_put_autosuspend(dd->dev); 1144 1145 ctx->offset = 0; 1146 1147 if (req->base.complete) 1148 req->base.complete(&req->base, err); 1149 } 1150 1151 static int omap_sham_handle_queue(struct omap_sham_dev *dd, 1152 struct ahash_request *req) 1153 { 1154 struct crypto_async_request *async_req, *backlog; 1155 struct omap_sham_reqctx *ctx; 1156 unsigned long flags; 1157 int err = 0, ret = 0; 1158 1159 retry: 1160 spin_lock_irqsave(&dd->lock, flags); 1161 if (req) 1162 ret = ahash_enqueue_request(&dd->queue, req); 1163 if (test_bit(FLAGS_BUSY, &dd->flags)) { 1164 spin_unlock_irqrestore(&dd->lock, flags); 1165 return ret; 1166 } 1167 backlog = crypto_get_backlog(&dd->queue); 1168 async_req = crypto_dequeue_request(&dd->queue); 1169 if (async_req) 1170 set_bit(FLAGS_BUSY, &dd->flags); 1171 spin_unlock_irqrestore(&dd->lock, flags); 1172 1173 if (!async_req) 1174 return ret; 1175 1176 if (backlog) 1177 backlog->complete(backlog, -EINPROGRESS); 1178 1179 req = ahash_request_cast(async_req); 1180 dd->req = req; 1181 ctx = ahash_request_ctx(req); 1182 1183 err = omap_sham_prepare_request(req, ctx->op == OP_UPDATE); 1184 if (err || !ctx->total) 1185 goto err1; 1186 1187 dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n", 1188 ctx->op, req->nbytes); 1189 1190 err = omap_sham_hw_init(dd); 1191 if (err) 1192 goto err1; 1193 1194 if (ctx->digcnt) 1195 /* request has changed - restore hash */ 1196 dd->pdata->copy_hash(req, 0); 1197 1198 if (ctx->op == OP_UPDATE || (dd->flags & BIT(FLAGS_HUGE))) { 1199 err = omap_sham_update_req(dd); 1200 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP))) 1201 /* no final() after finup() */ 1202 err = omap_sham_final_req(dd); 1203 } else if (ctx->op == OP_FINAL) { 1204 err = omap_sham_final_req(dd); 1205 } 1206 err1: 1207 dev_dbg(dd->dev, "exit, err: %d\n", err); 1208 1209 if (err != -EINPROGRESS) { 1210 /* done_task will not finish it, so do it here */ 1211 omap_sham_finish_req(req, err); 1212 req = NULL; 1213 1214 /* 1215 * Execute next request immediately if there is anything 1216 * in queue. 1217 */ 1218 goto retry; 1219 } 1220 1221 return ret; 1222 } 1223 1224 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op) 1225 { 1226 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1227 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 1228 struct omap_sham_dev *dd = tctx->dd; 1229 1230 ctx->op = op; 1231 1232 return omap_sham_handle_queue(dd, req); 1233 } 1234 1235 static int omap_sham_update(struct ahash_request *req) 1236 { 1237 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1238 struct omap_sham_dev *dd = ctx->dd; 1239 1240 if (!req->nbytes) 1241 return 0; 1242 1243 if (ctx->bufcnt + req->nbytes <= ctx->buflen) { 1244 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src, 1245 0, req->nbytes, 0); 1246 ctx->bufcnt += req->nbytes; 1247 return 0; 1248 } 1249 1250 if (dd->polling_mode) 1251 ctx->flags |= BIT(FLAGS_CPU); 1252 1253 return omap_sham_enqueue(req, OP_UPDATE); 1254 } 1255 1256 static int omap_sham_final_shash(struct ahash_request *req) 1257 { 1258 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 1259 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1260 int offset = 0; 1261 1262 /* 1263 * If we are running HMAC on limited hardware support, skip 1264 * the ipad in the beginning of the buffer if we are going for 1265 * software fallback algorithm. 1266 */ 1267 if (test_bit(FLAGS_HMAC, &ctx->flags) && 1268 !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags)) 1269 offset = get_block_size(ctx); 1270 1271 return crypto_shash_tfm_digest(tctx->fallback, ctx->buffer + offset, 1272 ctx->bufcnt - offset, req->result); 1273 } 1274 1275 static int omap_sham_final(struct ahash_request *req) 1276 { 1277 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1278 1279 ctx->flags |= BIT(FLAGS_FINUP); 1280 1281 if (ctx->flags & BIT(FLAGS_ERROR)) 1282 return 0; /* uncompleted hash is not needed */ 1283 1284 /* 1285 * OMAP HW accel works only with buffers >= 9. 1286 * HMAC is always >= 9 because ipad == block size. 1287 * If buffersize is less than fallback_sz, we use fallback 1288 * SW encoding, as using DMA + HW in this case doesn't provide 1289 * any benefit. 1290 */ 1291 if (!ctx->digcnt && ctx->bufcnt < ctx->dd->fallback_sz) 1292 return omap_sham_final_shash(req); 1293 else if (ctx->bufcnt) 1294 return omap_sham_enqueue(req, OP_FINAL); 1295 1296 /* copy ready hash (+ finalize hmac) */ 1297 return omap_sham_finish(req); 1298 } 1299 1300 static int omap_sham_finup(struct ahash_request *req) 1301 { 1302 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1303 int err1, err2; 1304 1305 ctx->flags |= BIT(FLAGS_FINUP); 1306 1307 err1 = omap_sham_update(req); 1308 if (err1 == -EINPROGRESS || err1 == -EBUSY) 1309 return err1; 1310 /* 1311 * final() has to be always called to cleanup resources 1312 * even if udpate() failed, except EINPROGRESS 1313 */ 1314 err2 = omap_sham_final(req); 1315 1316 return err1 ?: err2; 1317 } 1318 1319 static int omap_sham_digest(struct ahash_request *req) 1320 { 1321 return omap_sham_init(req) ?: omap_sham_finup(req); 1322 } 1323 1324 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key, 1325 unsigned int keylen) 1326 { 1327 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); 1328 struct omap_sham_hmac_ctx *bctx = tctx->base; 1329 int bs = crypto_shash_blocksize(bctx->shash); 1330 int ds = crypto_shash_digestsize(bctx->shash); 1331 struct omap_sham_dev *dd = NULL, *tmp; 1332 int err, i; 1333 1334 spin_lock_bh(&sham.lock); 1335 if (!tctx->dd) { 1336 list_for_each_entry(tmp, &sham.dev_list, list) { 1337 dd = tmp; 1338 break; 1339 } 1340 tctx->dd = dd; 1341 } else { 1342 dd = tctx->dd; 1343 } 1344 spin_unlock_bh(&sham.lock); 1345 1346 err = crypto_shash_setkey(tctx->fallback, key, keylen); 1347 if (err) 1348 return err; 1349 1350 if (keylen > bs) { 1351 err = crypto_shash_tfm_digest(bctx->shash, key, keylen, 1352 bctx->ipad); 1353 if (err) 1354 return err; 1355 keylen = ds; 1356 } else { 1357 memcpy(bctx->ipad, key, keylen); 1358 } 1359 1360 memset(bctx->ipad + keylen, 0, bs - keylen); 1361 1362 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) { 1363 memcpy(bctx->opad, bctx->ipad, bs); 1364 1365 for (i = 0; i < bs; i++) { 1366 bctx->ipad[i] ^= HMAC_IPAD_VALUE; 1367 bctx->opad[i] ^= HMAC_OPAD_VALUE; 1368 } 1369 } 1370 1371 return err; 1372 } 1373 1374 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base) 1375 { 1376 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm); 1377 const char *alg_name = crypto_tfm_alg_name(tfm); 1378 1379 /* Allocate a fallback and abort if it failed. */ 1380 tctx->fallback = crypto_alloc_shash(alg_name, 0, 1381 CRYPTO_ALG_NEED_FALLBACK); 1382 if (IS_ERR(tctx->fallback)) { 1383 pr_err("omap-sham: fallback driver '%s' " 1384 "could not be loaded.\n", alg_name); 1385 return PTR_ERR(tctx->fallback); 1386 } 1387 1388 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), 1389 sizeof(struct omap_sham_reqctx) + BUFLEN); 1390 1391 if (alg_base) { 1392 struct omap_sham_hmac_ctx *bctx = tctx->base; 1393 tctx->flags |= BIT(FLAGS_HMAC); 1394 bctx->shash = crypto_alloc_shash(alg_base, 0, 1395 CRYPTO_ALG_NEED_FALLBACK); 1396 if (IS_ERR(bctx->shash)) { 1397 pr_err("omap-sham: base driver '%s' " 1398 "could not be loaded.\n", alg_base); 1399 crypto_free_shash(tctx->fallback); 1400 return PTR_ERR(bctx->shash); 1401 } 1402 1403 } 1404 1405 return 0; 1406 } 1407 1408 static int omap_sham_cra_init(struct crypto_tfm *tfm) 1409 { 1410 return omap_sham_cra_init_alg(tfm, NULL); 1411 } 1412 1413 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm) 1414 { 1415 return omap_sham_cra_init_alg(tfm, "sha1"); 1416 } 1417 1418 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm) 1419 { 1420 return omap_sham_cra_init_alg(tfm, "sha224"); 1421 } 1422 1423 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm) 1424 { 1425 return omap_sham_cra_init_alg(tfm, "sha256"); 1426 } 1427 1428 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm) 1429 { 1430 return omap_sham_cra_init_alg(tfm, "md5"); 1431 } 1432 1433 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm) 1434 { 1435 return omap_sham_cra_init_alg(tfm, "sha384"); 1436 } 1437 1438 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm) 1439 { 1440 return omap_sham_cra_init_alg(tfm, "sha512"); 1441 } 1442 1443 static void omap_sham_cra_exit(struct crypto_tfm *tfm) 1444 { 1445 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm); 1446 1447 crypto_free_shash(tctx->fallback); 1448 tctx->fallback = NULL; 1449 1450 if (tctx->flags & BIT(FLAGS_HMAC)) { 1451 struct omap_sham_hmac_ctx *bctx = tctx->base; 1452 crypto_free_shash(bctx->shash); 1453 } 1454 } 1455 1456 static int omap_sham_export(struct ahash_request *req, void *out) 1457 { 1458 struct omap_sham_reqctx *rctx = ahash_request_ctx(req); 1459 1460 memcpy(out, rctx, sizeof(*rctx) + rctx->bufcnt); 1461 1462 return 0; 1463 } 1464 1465 static int omap_sham_import(struct ahash_request *req, const void *in) 1466 { 1467 struct omap_sham_reqctx *rctx = ahash_request_ctx(req); 1468 const struct omap_sham_reqctx *ctx_in = in; 1469 1470 memcpy(rctx, in, sizeof(*rctx) + ctx_in->bufcnt); 1471 1472 return 0; 1473 } 1474 1475 static struct ahash_alg algs_sha1_md5[] = { 1476 { 1477 .init = omap_sham_init, 1478 .update = omap_sham_update, 1479 .final = omap_sham_final, 1480 .finup = omap_sham_finup, 1481 .digest = omap_sham_digest, 1482 .halg.digestsize = SHA1_DIGEST_SIZE, 1483 .halg.base = { 1484 .cra_name = "sha1", 1485 .cra_driver_name = "omap-sha1", 1486 .cra_priority = 400, 1487 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1488 CRYPTO_ALG_ASYNC | 1489 CRYPTO_ALG_NEED_FALLBACK, 1490 .cra_blocksize = SHA1_BLOCK_SIZE, 1491 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1492 .cra_alignmask = OMAP_ALIGN_MASK, 1493 .cra_module = THIS_MODULE, 1494 .cra_init = omap_sham_cra_init, 1495 .cra_exit = omap_sham_cra_exit, 1496 } 1497 }, 1498 { 1499 .init = omap_sham_init, 1500 .update = omap_sham_update, 1501 .final = omap_sham_final, 1502 .finup = omap_sham_finup, 1503 .digest = omap_sham_digest, 1504 .halg.digestsize = MD5_DIGEST_SIZE, 1505 .halg.base = { 1506 .cra_name = "md5", 1507 .cra_driver_name = "omap-md5", 1508 .cra_priority = 400, 1509 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1510 CRYPTO_ALG_ASYNC | 1511 CRYPTO_ALG_NEED_FALLBACK, 1512 .cra_blocksize = SHA1_BLOCK_SIZE, 1513 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1514 .cra_alignmask = OMAP_ALIGN_MASK, 1515 .cra_module = THIS_MODULE, 1516 .cra_init = omap_sham_cra_init, 1517 .cra_exit = omap_sham_cra_exit, 1518 } 1519 }, 1520 { 1521 .init = omap_sham_init, 1522 .update = omap_sham_update, 1523 .final = omap_sham_final, 1524 .finup = omap_sham_finup, 1525 .digest = omap_sham_digest, 1526 .setkey = omap_sham_setkey, 1527 .halg.digestsize = SHA1_DIGEST_SIZE, 1528 .halg.base = { 1529 .cra_name = "hmac(sha1)", 1530 .cra_driver_name = "omap-hmac-sha1", 1531 .cra_priority = 400, 1532 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1533 CRYPTO_ALG_ASYNC | 1534 CRYPTO_ALG_NEED_FALLBACK, 1535 .cra_blocksize = SHA1_BLOCK_SIZE, 1536 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1537 sizeof(struct omap_sham_hmac_ctx), 1538 .cra_alignmask = OMAP_ALIGN_MASK, 1539 .cra_module = THIS_MODULE, 1540 .cra_init = omap_sham_cra_sha1_init, 1541 .cra_exit = omap_sham_cra_exit, 1542 } 1543 }, 1544 { 1545 .init = omap_sham_init, 1546 .update = omap_sham_update, 1547 .final = omap_sham_final, 1548 .finup = omap_sham_finup, 1549 .digest = omap_sham_digest, 1550 .setkey = omap_sham_setkey, 1551 .halg.digestsize = MD5_DIGEST_SIZE, 1552 .halg.base = { 1553 .cra_name = "hmac(md5)", 1554 .cra_driver_name = "omap-hmac-md5", 1555 .cra_priority = 400, 1556 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1557 CRYPTO_ALG_ASYNC | 1558 CRYPTO_ALG_NEED_FALLBACK, 1559 .cra_blocksize = SHA1_BLOCK_SIZE, 1560 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1561 sizeof(struct omap_sham_hmac_ctx), 1562 .cra_alignmask = OMAP_ALIGN_MASK, 1563 .cra_module = THIS_MODULE, 1564 .cra_init = omap_sham_cra_md5_init, 1565 .cra_exit = omap_sham_cra_exit, 1566 } 1567 } 1568 }; 1569 1570 /* OMAP4 has some algs in addition to what OMAP2 has */ 1571 static struct ahash_alg algs_sha224_sha256[] = { 1572 { 1573 .init = omap_sham_init, 1574 .update = omap_sham_update, 1575 .final = omap_sham_final, 1576 .finup = omap_sham_finup, 1577 .digest = omap_sham_digest, 1578 .halg.digestsize = SHA224_DIGEST_SIZE, 1579 .halg.base = { 1580 .cra_name = "sha224", 1581 .cra_driver_name = "omap-sha224", 1582 .cra_priority = 400, 1583 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1584 CRYPTO_ALG_ASYNC | 1585 CRYPTO_ALG_NEED_FALLBACK, 1586 .cra_blocksize = SHA224_BLOCK_SIZE, 1587 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1588 .cra_alignmask = OMAP_ALIGN_MASK, 1589 .cra_module = THIS_MODULE, 1590 .cra_init = omap_sham_cra_init, 1591 .cra_exit = omap_sham_cra_exit, 1592 } 1593 }, 1594 { 1595 .init = omap_sham_init, 1596 .update = omap_sham_update, 1597 .final = omap_sham_final, 1598 .finup = omap_sham_finup, 1599 .digest = omap_sham_digest, 1600 .halg.digestsize = SHA256_DIGEST_SIZE, 1601 .halg.base = { 1602 .cra_name = "sha256", 1603 .cra_driver_name = "omap-sha256", 1604 .cra_priority = 400, 1605 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1606 CRYPTO_ALG_ASYNC | 1607 CRYPTO_ALG_NEED_FALLBACK, 1608 .cra_blocksize = SHA256_BLOCK_SIZE, 1609 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1610 .cra_alignmask = OMAP_ALIGN_MASK, 1611 .cra_module = THIS_MODULE, 1612 .cra_init = omap_sham_cra_init, 1613 .cra_exit = omap_sham_cra_exit, 1614 } 1615 }, 1616 { 1617 .init = omap_sham_init, 1618 .update = omap_sham_update, 1619 .final = omap_sham_final, 1620 .finup = omap_sham_finup, 1621 .digest = omap_sham_digest, 1622 .setkey = omap_sham_setkey, 1623 .halg.digestsize = SHA224_DIGEST_SIZE, 1624 .halg.base = { 1625 .cra_name = "hmac(sha224)", 1626 .cra_driver_name = "omap-hmac-sha224", 1627 .cra_priority = 400, 1628 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1629 CRYPTO_ALG_ASYNC | 1630 CRYPTO_ALG_NEED_FALLBACK, 1631 .cra_blocksize = SHA224_BLOCK_SIZE, 1632 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1633 sizeof(struct omap_sham_hmac_ctx), 1634 .cra_alignmask = OMAP_ALIGN_MASK, 1635 .cra_module = THIS_MODULE, 1636 .cra_init = omap_sham_cra_sha224_init, 1637 .cra_exit = omap_sham_cra_exit, 1638 } 1639 }, 1640 { 1641 .init = omap_sham_init, 1642 .update = omap_sham_update, 1643 .final = omap_sham_final, 1644 .finup = omap_sham_finup, 1645 .digest = omap_sham_digest, 1646 .setkey = omap_sham_setkey, 1647 .halg.digestsize = SHA256_DIGEST_SIZE, 1648 .halg.base = { 1649 .cra_name = "hmac(sha256)", 1650 .cra_driver_name = "omap-hmac-sha256", 1651 .cra_priority = 400, 1652 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1653 CRYPTO_ALG_ASYNC | 1654 CRYPTO_ALG_NEED_FALLBACK, 1655 .cra_blocksize = SHA256_BLOCK_SIZE, 1656 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1657 sizeof(struct omap_sham_hmac_ctx), 1658 .cra_alignmask = OMAP_ALIGN_MASK, 1659 .cra_module = THIS_MODULE, 1660 .cra_init = omap_sham_cra_sha256_init, 1661 .cra_exit = omap_sham_cra_exit, 1662 } 1663 }, 1664 }; 1665 1666 static struct ahash_alg algs_sha384_sha512[] = { 1667 { 1668 .init = omap_sham_init, 1669 .update = omap_sham_update, 1670 .final = omap_sham_final, 1671 .finup = omap_sham_finup, 1672 .digest = omap_sham_digest, 1673 .halg.digestsize = SHA384_DIGEST_SIZE, 1674 .halg.base = { 1675 .cra_name = "sha384", 1676 .cra_driver_name = "omap-sha384", 1677 .cra_priority = 400, 1678 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1679 CRYPTO_ALG_ASYNC | 1680 CRYPTO_ALG_NEED_FALLBACK, 1681 .cra_blocksize = SHA384_BLOCK_SIZE, 1682 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1683 .cra_alignmask = OMAP_ALIGN_MASK, 1684 .cra_module = THIS_MODULE, 1685 .cra_init = omap_sham_cra_init, 1686 .cra_exit = omap_sham_cra_exit, 1687 } 1688 }, 1689 { 1690 .init = omap_sham_init, 1691 .update = omap_sham_update, 1692 .final = omap_sham_final, 1693 .finup = omap_sham_finup, 1694 .digest = omap_sham_digest, 1695 .halg.digestsize = SHA512_DIGEST_SIZE, 1696 .halg.base = { 1697 .cra_name = "sha512", 1698 .cra_driver_name = "omap-sha512", 1699 .cra_priority = 400, 1700 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1701 CRYPTO_ALG_ASYNC | 1702 CRYPTO_ALG_NEED_FALLBACK, 1703 .cra_blocksize = SHA512_BLOCK_SIZE, 1704 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1705 .cra_alignmask = OMAP_ALIGN_MASK, 1706 .cra_module = THIS_MODULE, 1707 .cra_init = omap_sham_cra_init, 1708 .cra_exit = omap_sham_cra_exit, 1709 } 1710 }, 1711 { 1712 .init = omap_sham_init, 1713 .update = omap_sham_update, 1714 .final = omap_sham_final, 1715 .finup = omap_sham_finup, 1716 .digest = omap_sham_digest, 1717 .setkey = omap_sham_setkey, 1718 .halg.digestsize = SHA384_DIGEST_SIZE, 1719 .halg.base = { 1720 .cra_name = "hmac(sha384)", 1721 .cra_driver_name = "omap-hmac-sha384", 1722 .cra_priority = 400, 1723 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1724 CRYPTO_ALG_ASYNC | 1725 CRYPTO_ALG_NEED_FALLBACK, 1726 .cra_blocksize = SHA384_BLOCK_SIZE, 1727 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1728 sizeof(struct omap_sham_hmac_ctx), 1729 .cra_alignmask = OMAP_ALIGN_MASK, 1730 .cra_module = THIS_MODULE, 1731 .cra_init = omap_sham_cra_sha384_init, 1732 .cra_exit = omap_sham_cra_exit, 1733 } 1734 }, 1735 { 1736 .init = omap_sham_init, 1737 .update = omap_sham_update, 1738 .final = omap_sham_final, 1739 .finup = omap_sham_finup, 1740 .digest = omap_sham_digest, 1741 .setkey = omap_sham_setkey, 1742 .halg.digestsize = SHA512_DIGEST_SIZE, 1743 .halg.base = { 1744 .cra_name = "hmac(sha512)", 1745 .cra_driver_name = "omap-hmac-sha512", 1746 .cra_priority = 400, 1747 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1748 CRYPTO_ALG_ASYNC | 1749 CRYPTO_ALG_NEED_FALLBACK, 1750 .cra_blocksize = SHA512_BLOCK_SIZE, 1751 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1752 sizeof(struct omap_sham_hmac_ctx), 1753 .cra_alignmask = OMAP_ALIGN_MASK, 1754 .cra_module = THIS_MODULE, 1755 .cra_init = omap_sham_cra_sha512_init, 1756 .cra_exit = omap_sham_cra_exit, 1757 } 1758 }, 1759 }; 1760 1761 static void omap_sham_done_task(unsigned long data) 1762 { 1763 struct omap_sham_dev *dd = (struct omap_sham_dev *)data; 1764 int err = 0; 1765 1766 dev_dbg(dd->dev, "%s: flags=%lx\n", __func__, dd->flags); 1767 1768 if (!test_bit(FLAGS_BUSY, &dd->flags)) { 1769 omap_sham_handle_queue(dd, NULL); 1770 return; 1771 } 1772 1773 if (test_bit(FLAGS_CPU, &dd->flags)) { 1774 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) 1775 goto finish; 1776 } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) { 1777 if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) { 1778 omap_sham_update_dma_stop(dd); 1779 if (dd->err) { 1780 err = dd->err; 1781 goto finish; 1782 } 1783 } 1784 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) { 1785 /* hash or semi-hash ready */ 1786 clear_bit(FLAGS_DMA_READY, &dd->flags); 1787 goto finish; 1788 } 1789 } 1790 1791 return; 1792 1793 finish: 1794 dev_dbg(dd->dev, "update done: err: %d\n", err); 1795 /* finish curent request */ 1796 omap_sham_finish_req(dd->req, err); 1797 1798 /* If we are not busy, process next req */ 1799 if (!test_bit(FLAGS_BUSY, &dd->flags)) 1800 omap_sham_handle_queue(dd, NULL); 1801 } 1802 1803 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd) 1804 { 1805 if (!test_bit(FLAGS_BUSY, &dd->flags)) { 1806 dev_warn(dd->dev, "Interrupt when no active requests.\n"); 1807 } else { 1808 set_bit(FLAGS_OUTPUT_READY, &dd->flags); 1809 tasklet_schedule(&dd->done_task); 1810 } 1811 1812 return IRQ_HANDLED; 1813 } 1814 1815 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id) 1816 { 1817 struct omap_sham_dev *dd = dev_id; 1818 1819 if (unlikely(test_bit(FLAGS_FINAL, &dd->flags))) 1820 /* final -> allow device to go to power-saving mode */ 1821 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH); 1822 1823 omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY, 1824 SHA_REG_CTRL_OUTPUT_READY); 1825 omap_sham_read(dd, SHA_REG_CTRL); 1826 1827 return omap_sham_irq_common(dd); 1828 } 1829 1830 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id) 1831 { 1832 struct omap_sham_dev *dd = dev_id; 1833 1834 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN); 1835 1836 return omap_sham_irq_common(dd); 1837 } 1838 1839 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = { 1840 { 1841 .algs_list = algs_sha1_md5, 1842 .size = ARRAY_SIZE(algs_sha1_md5), 1843 }, 1844 }; 1845 1846 static const struct omap_sham_pdata omap_sham_pdata_omap2 = { 1847 .algs_info = omap_sham_algs_info_omap2, 1848 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2), 1849 .flags = BIT(FLAGS_BE32_SHA1), 1850 .digest_size = SHA1_DIGEST_SIZE, 1851 .copy_hash = omap_sham_copy_hash_omap2, 1852 .write_ctrl = omap_sham_write_ctrl_omap2, 1853 .trigger = omap_sham_trigger_omap2, 1854 .poll_irq = omap_sham_poll_irq_omap2, 1855 .intr_hdlr = omap_sham_irq_omap2, 1856 .idigest_ofs = 0x00, 1857 .din_ofs = 0x1c, 1858 .digcnt_ofs = 0x14, 1859 .rev_ofs = 0x5c, 1860 .mask_ofs = 0x60, 1861 .sysstatus_ofs = 0x64, 1862 .major_mask = 0xf0, 1863 .major_shift = 4, 1864 .minor_mask = 0x0f, 1865 .minor_shift = 0, 1866 }; 1867 1868 #ifdef CONFIG_OF 1869 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = { 1870 { 1871 .algs_list = algs_sha1_md5, 1872 .size = ARRAY_SIZE(algs_sha1_md5), 1873 }, 1874 { 1875 .algs_list = algs_sha224_sha256, 1876 .size = ARRAY_SIZE(algs_sha224_sha256), 1877 }, 1878 }; 1879 1880 static const struct omap_sham_pdata omap_sham_pdata_omap4 = { 1881 .algs_info = omap_sham_algs_info_omap4, 1882 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4), 1883 .flags = BIT(FLAGS_AUTO_XOR), 1884 .digest_size = SHA256_DIGEST_SIZE, 1885 .copy_hash = omap_sham_copy_hash_omap4, 1886 .write_ctrl = omap_sham_write_ctrl_omap4, 1887 .trigger = omap_sham_trigger_omap4, 1888 .poll_irq = omap_sham_poll_irq_omap4, 1889 .intr_hdlr = omap_sham_irq_omap4, 1890 .idigest_ofs = 0x020, 1891 .odigest_ofs = 0x0, 1892 .din_ofs = 0x080, 1893 .digcnt_ofs = 0x040, 1894 .rev_ofs = 0x100, 1895 .mask_ofs = 0x110, 1896 .sysstatus_ofs = 0x114, 1897 .mode_ofs = 0x44, 1898 .length_ofs = 0x48, 1899 .major_mask = 0x0700, 1900 .major_shift = 8, 1901 .minor_mask = 0x003f, 1902 .minor_shift = 0, 1903 }; 1904 1905 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = { 1906 { 1907 .algs_list = algs_sha1_md5, 1908 .size = ARRAY_SIZE(algs_sha1_md5), 1909 }, 1910 { 1911 .algs_list = algs_sha224_sha256, 1912 .size = ARRAY_SIZE(algs_sha224_sha256), 1913 }, 1914 { 1915 .algs_list = algs_sha384_sha512, 1916 .size = ARRAY_SIZE(algs_sha384_sha512), 1917 }, 1918 }; 1919 1920 static const struct omap_sham_pdata omap_sham_pdata_omap5 = { 1921 .algs_info = omap_sham_algs_info_omap5, 1922 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5), 1923 .flags = BIT(FLAGS_AUTO_XOR), 1924 .digest_size = SHA512_DIGEST_SIZE, 1925 .copy_hash = omap_sham_copy_hash_omap4, 1926 .write_ctrl = omap_sham_write_ctrl_omap4, 1927 .trigger = omap_sham_trigger_omap4, 1928 .poll_irq = omap_sham_poll_irq_omap4, 1929 .intr_hdlr = omap_sham_irq_omap4, 1930 .idigest_ofs = 0x240, 1931 .odigest_ofs = 0x200, 1932 .din_ofs = 0x080, 1933 .digcnt_ofs = 0x280, 1934 .rev_ofs = 0x100, 1935 .mask_ofs = 0x110, 1936 .sysstatus_ofs = 0x114, 1937 .mode_ofs = 0x284, 1938 .length_ofs = 0x288, 1939 .major_mask = 0x0700, 1940 .major_shift = 8, 1941 .minor_mask = 0x003f, 1942 .minor_shift = 0, 1943 }; 1944 1945 static const struct of_device_id omap_sham_of_match[] = { 1946 { 1947 .compatible = "ti,omap2-sham", 1948 .data = &omap_sham_pdata_omap2, 1949 }, 1950 { 1951 .compatible = "ti,omap3-sham", 1952 .data = &omap_sham_pdata_omap2, 1953 }, 1954 { 1955 .compatible = "ti,omap4-sham", 1956 .data = &omap_sham_pdata_omap4, 1957 }, 1958 { 1959 .compatible = "ti,omap5-sham", 1960 .data = &omap_sham_pdata_omap5, 1961 }, 1962 {}, 1963 }; 1964 MODULE_DEVICE_TABLE(of, omap_sham_of_match); 1965 1966 static int omap_sham_get_res_of(struct omap_sham_dev *dd, 1967 struct device *dev, struct resource *res) 1968 { 1969 struct device_node *node = dev->of_node; 1970 int err = 0; 1971 1972 dd->pdata = of_device_get_match_data(dev); 1973 if (!dd->pdata) { 1974 dev_err(dev, "no compatible OF match\n"); 1975 err = -EINVAL; 1976 goto err; 1977 } 1978 1979 err = of_address_to_resource(node, 0, res); 1980 if (err < 0) { 1981 dev_err(dev, "can't translate OF node address\n"); 1982 err = -EINVAL; 1983 goto err; 1984 } 1985 1986 dd->irq = irq_of_parse_and_map(node, 0); 1987 if (!dd->irq) { 1988 dev_err(dev, "can't translate OF irq value\n"); 1989 err = -EINVAL; 1990 goto err; 1991 } 1992 1993 err: 1994 return err; 1995 } 1996 #else 1997 static const struct of_device_id omap_sham_of_match[] = { 1998 {}, 1999 }; 2000 2001 static int omap_sham_get_res_of(struct omap_sham_dev *dd, 2002 struct device *dev, struct resource *res) 2003 { 2004 return -EINVAL; 2005 } 2006 #endif 2007 2008 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd, 2009 struct platform_device *pdev, struct resource *res) 2010 { 2011 struct device *dev = &pdev->dev; 2012 struct resource *r; 2013 int err = 0; 2014 2015 /* Get the base address */ 2016 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2017 if (!r) { 2018 dev_err(dev, "no MEM resource info\n"); 2019 err = -ENODEV; 2020 goto err; 2021 } 2022 memcpy(res, r, sizeof(*res)); 2023 2024 /* Get the IRQ */ 2025 dd->irq = platform_get_irq(pdev, 0); 2026 if (dd->irq < 0) { 2027 err = dd->irq; 2028 goto err; 2029 } 2030 2031 /* Only OMAP2/3 can be non-DT */ 2032 dd->pdata = &omap_sham_pdata_omap2; 2033 2034 err: 2035 return err; 2036 } 2037 2038 static ssize_t fallback_show(struct device *dev, struct device_attribute *attr, 2039 char *buf) 2040 { 2041 struct omap_sham_dev *dd = dev_get_drvdata(dev); 2042 2043 return sprintf(buf, "%d\n", dd->fallback_sz); 2044 } 2045 2046 static ssize_t fallback_store(struct device *dev, struct device_attribute *attr, 2047 const char *buf, size_t size) 2048 { 2049 struct omap_sham_dev *dd = dev_get_drvdata(dev); 2050 ssize_t status; 2051 long value; 2052 2053 status = kstrtol(buf, 0, &value); 2054 if (status) 2055 return status; 2056 2057 /* HW accelerator only works with buffers > 9 */ 2058 if (value < 9) { 2059 dev_err(dev, "minimum fallback size 9\n"); 2060 return -EINVAL; 2061 } 2062 2063 dd->fallback_sz = value; 2064 2065 return size; 2066 } 2067 2068 static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr, 2069 char *buf) 2070 { 2071 struct omap_sham_dev *dd = dev_get_drvdata(dev); 2072 2073 return sprintf(buf, "%d\n", dd->queue.max_qlen); 2074 } 2075 2076 static ssize_t queue_len_store(struct device *dev, 2077 struct device_attribute *attr, const char *buf, 2078 size_t size) 2079 { 2080 struct omap_sham_dev *dd = dev_get_drvdata(dev); 2081 ssize_t status; 2082 long value; 2083 unsigned long flags; 2084 2085 status = kstrtol(buf, 0, &value); 2086 if (status) 2087 return status; 2088 2089 if (value < 1) 2090 return -EINVAL; 2091 2092 /* 2093 * Changing the queue size in fly is safe, if size becomes smaller 2094 * than current size, it will just not accept new entries until 2095 * it has shrank enough. 2096 */ 2097 spin_lock_irqsave(&dd->lock, flags); 2098 dd->queue.max_qlen = value; 2099 spin_unlock_irqrestore(&dd->lock, flags); 2100 2101 return size; 2102 } 2103 2104 static DEVICE_ATTR_RW(queue_len); 2105 static DEVICE_ATTR_RW(fallback); 2106 2107 static struct attribute *omap_sham_attrs[] = { 2108 &dev_attr_queue_len.attr, 2109 &dev_attr_fallback.attr, 2110 NULL, 2111 }; 2112 2113 static struct attribute_group omap_sham_attr_group = { 2114 .attrs = omap_sham_attrs, 2115 }; 2116 2117 static int omap_sham_probe(struct platform_device *pdev) 2118 { 2119 struct omap_sham_dev *dd; 2120 struct device *dev = &pdev->dev; 2121 struct resource res; 2122 dma_cap_mask_t mask; 2123 int err, i, j; 2124 u32 rev; 2125 2126 dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL); 2127 if (dd == NULL) { 2128 dev_err(dev, "unable to alloc data struct.\n"); 2129 err = -ENOMEM; 2130 goto data_err; 2131 } 2132 dd->dev = dev; 2133 platform_set_drvdata(pdev, dd); 2134 2135 INIT_LIST_HEAD(&dd->list); 2136 spin_lock_init(&dd->lock); 2137 tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd); 2138 crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH); 2139 2140 err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) : 2141 omap_sham_get_res_pdev(dd, pdev, &res); 2142 if (err) 2143 goto data_err; 2144 2145 dd->io_base = devm_ioremap_resource(dev, &res); 2146 if (IS_ERR(dd->io_base)) { 2147 err = PTR_ERR(dd->io_base); 2148 goto data_err; 2149 } 2150 dd->phys_base = res.start; 2151 2152 err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr, 2153 IRQF_TRIGGER_NONE, dev_name(dev), dd); 2154 if (err) { 2155 dev_err(dev, "unable to request irq %d, err = %d\n", 2156 dd->irq, err); 2157 goto data_err; 2158 } 2159 2160 dma_cap_zero(mask); 2161 dma_cap_set(DMA_SLAVE, mask); 2162 2163 dd->dma_lch = dma_request_chan(dev, "rx"); 2164 if (IS_ERR(dd->dma_lch)) { 2165 err = PTR_ERR(dd->dma_lch); 2166 if (err == -EPROBE_DEFER) 2167 goto data_err; 2168 2169 dd->polling_mode = 1; 2170 dev_dbg(dev, "using polling mode instead of dma\n"); 2171 } 2172 2173 dd->flags |= dd->pdata->flags; 2174 2175 pm_runtime_use_autosuspend(dev); 2176 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY); 2177 2178 dd->fallback_sz = OMAP_SHA_DMA_THRESHOLD; 2179 2180 pm_runtime_enable(dev); 2181 pm_runtime_irq_safe(dev); 2182 2183 err = pm_runtime_get_sync(dev); 2184 if (err < 0) { 2185 dev_err(dev, "failed to get sync: %d\n", err); 2186 goto err_pm; 2187 } 2188 2189 rev = omap_sham_read(dd, SHA_REG_REV(dd)); 2190 pm_runtime_put_sync(&pdev->dev); 2191 2192 dev_info(dev, "hw accel on OMAP rev %u.%u\n", 2193 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift, 2194 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift); 2195 2196 spin_lock(&sham.lock); 2197 list_add_tail(&dd->list, &sham.dev_list); 2198 spin_unlock(&sham.lock); 2199 2200 for (i = 0; i < dd->pdata->algs_info_size; i++) { 2201 for (j = 0; j < dd->pdata->algs_info[i].size; j++) { 2202 struct ahash_alg *alg; 2203 2204 alg = &dd->pdata->algs_info[i].algs_list[j]; 2205 alg->export = omap_sham_export; 2206 alg->import = omap_sham_import; 2207 alg->halg.statesize = sizeof(struct omap_sham_reqctx) + 2208 BUFLEN; 2209 err = crypto_register_ahash(alg); 2210 if (err) 2211 goto err_algs; 2212 2213 dd->pdata->algs_info[i].registered++; 2214 } 2215 } 2216 2217 err = sysfs_create_group(&dev->kobj, &omap_sham_attr_group); 2218 if (err) { 2219 dev_err(dev, "could not create sysfs device attrs\n"); 2220 goto err_algs; 2221 } 2222 2223 return 0; 2224 2225 err_algs: 2226 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 2227 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 2228 crypto_unregister_ahash( 2229 &dd->pdata->algs_info[i].algs_list[j]); 2230 err_pm: 2231 pm_runtime_disable(dev); 2232 if (!dd->polling_mode) 2233 dma_release_channel(dd->dma_lch); 2234 data_err: 2235 dev_err(dev, "initialization failed.\n"); 2236 2237 return err; 2238 } 2239 2240 static int omap_sham_remove(struct platform_device *pdev) 2241 { 2242 struct omap_sham_dev *dd; 2243 int i, j; 2244 2245 dd = platform_get_drvdata(pdev); 2246 if (!dd) 2247 return -ENODEV; 2248 spin_lock(&sham.lock); 2249 list_del(&dd->list); 2250 spin_unlock(&sham.lock); 2251 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 2252 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 2253 crypto_unregister_ahash( 2254 &dd->pdata->algs_info[i].algs_list[j]); 2255 tasklet_kill(&dd->done_task); 2256 pm_runtime_disable(&pdev->dev); 2257 2258 if (!dd->polling_mode) 2259 dma_release_channel(dd->dma_lch); 2260 2261 sysfs_remove_group(&dd->dev->kobj, &omap_sham_attr_group); 2262 2263 return 0; 2264 } 2265 2266 #ifdef CONFIG_PM_SLEEP 2267 static int omap_sham_suspend(struct device *dev) 2268 { 2269 pm_runtime_put_sync(dev); 2270 return 0; 2271 } 2272 2273 static int omap_sham_resume(struct device *dev) 2274 { 2275 int err = pm_runtime_get_sync(dev); 2276 if (err < 0) { 2277 dev_err(dev, "failed to get sync: %d\n", err); 2278 return err; 2279 } 2280 return 0; 2281 } 2282 #endif 2283 2284 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume); 2285 2286 static struct platform_driver omap_sham_driver = { 2287 .probe = omap_sham_probe, 2288 .remove = omap_sham_remove, 2289 .driver = { 2290 .name = "omap-sham", 2291 .pm = &omap_sham_pm_ops, 2292 .of_match_table = omap_sham_of_match, 2293 }, 2294 }; 2295 2296 module_platform_driver(omap_sham_driver); 2297 2298 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support."); 2299 MODULE_LICENSE("GPL v2"); 2300 MODULE_AUTHOR("Dmitry Kasatkin"); 2301 MODULE_ALIAS("platform:omap-sham"); 2302