1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Cryptographic API. 4 * 5 * Support for OMAP SHA1/MD5 HW acceleration. 6 * 7 * Copyright (c) 2010 Nokia Corporation 8 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> 9 * Copyright (c) 2011 Texas Instruments Incorporated 10 * 11 * Some ideas are from old omap-sha1-md5.c driver. 12 */ 13 14 #define pr_fmt(fmt) "%s: " fmt, __func__ 15 16 #include <crypto/engine.h> 17 #include <crypto/hmac.h> 18 #include <crypto/internal/hash.h> 19 #include <crypto/scatterwalk.h> 20 #include <crypto/sha1.h> 21 #include <crypto/sha2.h> 22 #include <linux/err.h> 23 #include <linux/device.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/dmaengine.h> 26 #include <linux/init.h> 27 #include <linux/interrupt.h> 28 #include <linux/io.h> 29 #include <linux/irq.h> 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/of.h> 33 #include <linux/platform_device.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/scatterlist.h> 36 #include <linux/slab.h> 37 #include <linux/string.h> 38 #include <linux/sysfs.h> 39 #include <linux/workqueue.h> 40 41 #define MD5_DIGEST_SIZE 16 42 43 #define SHA_REG_IDIGEST(dd, x) ((dd)->pdata->idigest_ofs + ((x)*0x04)) 44 #define SHA_REG_DIN(dd, x) ((dd)->pdata->din_ofs + ((x) * 0x04)) 45 #define SHA_REG_DIGCNT(dd) ((dd)->pdata->digcnt_ofs) 46 47 #define SHA_REG_ODIGEST(dd, x) ((dd)->pdata->odigest_ofs + (x * 0x04)) 48 49 #define SHA_REG_CTRL 0x18 50 #define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5) 51 #define SHA_REG_CTRL_CLOSE_HASH (1 << 4) 52 #define SHA_REG_CTRL_ALGO_CONST (1 << 3) 53 #define SHA_REG_CTRL_ALGO (1 << 2) 54 #define SHA_REG_CTRL_INPUT_READY (1 << 1) 55 #define SHA_REG_CTRL_OUTPUT_READY (1 << 0) 56 57 #define SHA_REG_REV(dd) ((dd)->pdata->rev_ofs) 58 59 #define SHA_REG_MASK(dd) ((dd)->pdata->mask_ofs) 60 #define SHA_REG_MASK_DMA_EN (1 << 3) 61 #define SHA_REG_MASK_IT_EN (1 << 2) 62 #define SHA_REG_MASK_SOFTRESET (1 << 1) 63 #define SHA_REG_AUTOIDLE (1 << 0) 64 65 #define SHA_REG_SYSSTATUS(dd) ((dd)->pdata->sysstatus_ofs) 66 #define SHA_REG_SYSSTATUS_RESETDONE (1 << 0) 67 68 #define SHA_REG_MODE(dd) ((dd)->pdata->mode_ofs) 69 #define SHA_REG_MODE_HMAC_OUTER_HASH (1 << 7) 70 #define SHA_REG_MODE_HMAC_KEY_PROC (1 << 5) 71 #define SHA_REG_MODE_CLOSE_HASH (1 << 4) 72 #define SHA_REG_MODE_ALGO_CONSTANT (1 << 3) 73 74 #define SHA_REG_MODE_ALGO_MASK (7 << 0) 75 #define SHA_REG_MODE_ALGO_MD5_128 (0 << 1) 76 #define SHA_REG_MODE_ALGO_SHA1_160 (1 << 1) 77 #define SHA_REG_MODE_ALGO_SHA2_224 (2 << 1) 78 #define SHA_REG_MODE_ALGO_SHA2_256 (3 << 1) 79 #define SHA_REG_MODE_ALGO_SHA2_384 (1 << 0) 80 #define SHA_REG_MODE_ALGO_SHA2_512 (3 << 0) 81 82 #define SHA_REG_LENGTH(dd) ((dd)->pdata->length_ofs) 83 84 #define SHA_REG_IRQSTATUS 0x118 85 #define SHA_REG_IRQSTATUS_CTX_RDY (1 << 3) 86 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2) 87 #define SHA_REG_IRQSTATUS_INPUT_RDY (1 << 1) 88 #define SHA_REG_IRQSTATUS_OUTPUT_RDY (1 << 0) 89 90 #define SHA_REG_IRQENA 0x11C 91 #define SHA_REG_IRQENA_CTX_RDY (1 << 3) 92 #define SHA_REG_IRQENA_PARTHASH_RDY (1 << 2) 93 #define SHA_REG_IRQENA_INPUT_RDY (1 << 1) 94 #define SHA_REG_IRQENA_OUTPUT_RDY (1 << 0) 95 96 #define DEFAULT_TIMEOUT_INTERVAL HZ 97 98 #define DEFAULT_AUTOSUSPEND_DELAY 1000 99 100 /* mostly device flags */ 101 #define FLAGS_FINAL 1 102 #define FLAGS_DMA_ACTIVE 2 103 #define FLAGS_OUTPUT_READY 3 104 #define FLAGS_CPU 5 105 #define FLAGS_DMA_READY 6 106 #define FLAGS_AUTO_XOR 7 107 #define FLAGS_BE32_SHA1 8 108 #define FLAGS_SGS_COPIED 9 109 #define FLAGS_SGS_ALLOCED 10 110 #define FLAGS_HUGE 11 111 112 /* context flags */ 113 #define FLAGS_FINUP 16 114 115 #define FLAGS_MODE_SHIFT 18 116 #define FLAGS_MODE_MASK (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT) 117 #define FLAGS_MODE_MD5 (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT) 118 #define FLAGS_MODE_SHA1 (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT) 119 #define FLAGS_MODE_SHA224 (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT) 120 #define FLAGS_MODE_SHA256 (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT) 121 #define FLAGS_MODE_SHA384 (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT) 122 #define FLAGS_MODE_SHA512 (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT) 123 124 #define FLAGS_HMAC 21 125 #define FLAGS_ERROR 22 126 127 #define OP_UPDATE 1 128 #define OP_FINAL 2 129 130 #define OMAP_ALIGN_MASK (sizeof(u32)-1) 131 #define OMAP_ALIGNED __attribute__((aligned(sizeof(u32)))) 132 133 #define BUFLEN SHA512_BLOCK_SIZE 134 #define OMAP_SHA_DMA_THRESHOLD 256 135 136 #define OMAP_SHA_MAX_DMA_LEN (1024 * 2048) 137 138 struct omap_sham_dev; 139 140 struct omap_sham_reqctx { 141 struct omap_sham_dev *dd; 142 unsigned long flags; 143 u8 op; 144 145 u8 digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED; 146 size_t digcnt; 147 size_t bufcnt; 148 149 /* walk state */ 150 struct scatterlist *sg; 151 struct scatterlist sgl[2]; 152 int offset; /* offset in current sg */ 153 int sg_len; 154 unsigned int total; /* total request */ 155 156 u8 buffer[BUFLEN] OMAP_ALIGNED; 157 }; 158 159 struct omap_sham_hmac_ctx { 160 struct crypto_shash *shash; 161 u8 ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED; 162 u8 opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED; 163 }; 164 165 struct omap_sham_ctx { 166 unsigned long flags; 167 168 /* fallback stuff */ 169 struct crypto_shash *fallback; 170 171 struct omap_sham_hmac_ctx base[]; 172 }; 173 174 #define OMAP_SHAM_QUEUE_LENGTH 10 175 176 struct omap_sham_algs_info { 177 struct ahash_engine_alg *algs_list; 178 unsigned int size; 179 unsigned int registered; 180 }; 181 182 struct omap_sham_pdata { 183 struct omap_sham_algs_info *algs_info; 184 unsigned int algs_info_size; 185 unsigned long flags; 186 int digest_size; 187 188 void (*copy_hash)(struct ahash_request *req, int out); 189 void (*write_ctrl)(struct omap_sham_dev *dd, size_t length, 190 int final, int dma); 191 void (*trigger)(struct omap_sham_dev *dd, size_t length); 192 int (*poll_irq)(struct omap_sham_dev *dd); 193 irqreturn_t (*intr_hdlr)(int irq, void *dev_id); 194 195 u32 odigest_ofs; 196 u32 idigest_ofs; 197 u32 din_ofs; 198 u32 digcnt_ofs; 199 u32 rev_ofs; 200 u32 mask_ofs; 201 u32 sysstatus_ofs; 202 u32 mode_ofs; 203 u32 length_ofs; 204 205 u32 major_mask; 206 u32 major_shift; 207 u32 minor_mask; 208 u32 minor_shift; 209 }; 210 211 struct omap_sham_dev { 212 struct list_head list; 213 unsigned long phys_base; 214 struct device *dev; 215 void __iomem *io_base; 216 int irq; 217 int err; 218 struct dma_chan *dma_lch; 219 struct work_struct done_task; 220 u8 polling_mode; 221 u8 xmit_buf[BUFLEN] OMAP_ALIGNED; 222 223 unsigned long flags; 224 int fallback_sz; 225 struct crypto_queue queue; 226 struct ahash_request *req; 227 struct crypto_engine *engine; 228 229 const struct omap_sham_pdata *pdata; 230 }; 231 232 struct omap_sham_drv { 233 struct list_head dev_list; 234 spinlock_t lock; 235 unsigned long flags; 236 }; 237 238 static struct omap_sham_drv sham = { 239 .dev_list = LIST_HEAD_INIT(sham.dev_list), 240 .lock = __SPIN_LOCK_UNLOCKED(sham.lock), 241 }; 242 243 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op); 244 static void omap_sham_finish_req(struct ahash_request *req, int err); 245 246 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset) 247 { 248 return __raw_readl(dd->io_base + offset); 249 } 250 251 static inline void omap_sham_write(struct omap_sham_dev *dd, 252 u32 offset, u32 value) 253 { 254 __raw_writel(value, dd->io_base + offset); 255 } 256 257 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address, 258 u32 value, u32 mask) 259 { 260 u32 val; 261 262 val = omap_sham_read(dd, address); 263 val &= ~mask; 264 val |= value; 265 omap_sham_write(dd, address, val); 266 } 267 268 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit) 269 { 270 unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL; 271 272 while (!(omap_sham_read(dd, offset) & bit)) { 273 if (time_is_before_jiffies(timeout)) 274 return -ETIMEDOUT; 275 } 276 277 return 0; 278 } 279 280 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out) 281 { 282 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 283 struct omap_sham_dev *dd = ctx->dd; 284 u32 *hash = (u32 *)ctx->digest; 285 int i; 286 287 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) { 288 if (out) 289 hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i)); 290 else 291 omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]); 292 } 293 } 294 295 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out) 296 { 297 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 298 struct omap_sham_dev *dd = ctx->dd; 299 int i; 300 301 if (ctx->flags & BIT(FLAGS_HMAC)) { 302 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req); 303 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); 304 struct omap_sham_hmac_ctx *bctx = tctx->base; 305 u32 *opad = (u32 *)bctx->opad; 306 307 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) { 308 if (out) 309 opad[i] = omap_sham_read(dd, 310 SHA_REG_ODIGEST(dd, i)); 311 else 312 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i), 313 opad[i]); 314 } 315 } 316 317 omap_sham_copy_hash_omap2(req, out); 318 } 319 320 static void omap_sham_copy_ready_hash(struct ahash_request *req) 321 { 322 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 323 u32 *in = (u32 *)ctx->digest; 324 u32 *hash = (u32 *)req->result; 325 int i, d, big_endian = 0; 326 327 if (!hash) 328 return; 329 330 switch (ctx->flags & FLAGS_MODE_MASK) { 331 case FLAGS_MODE_MD5: 332 d = MD5_DIGEST_SIZE / sizeof(u32); 333 break; 334 case FLAGS_MODE_SHA1: 335 /* OMAP2 SHA1 is big endian */ 336 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags)) 337 big_endian = 1; 338 d = SHA1_DIGEST_SIZE / sizeof(u32); 339 break; 340 case FLAGS_MODE_SHA224: 341 d = SHA224_DIGEST_SIZE / sizeof(u32); 342 break; 343 case FLAGS_MODE_SHA256: 344 d = SHA256_DIGEST_SIZE / sizeof(u32); 345 break; 346 case FLAGS_MODE_SHA384: 347 d = SHA384_DIGEST_SIZE / sizeof(u32); 348 break; 349 case FLAGS_MODE_SHA512: 350 d = SHA512_DIGEST_SIZE / sizeof(u32); 351 break; 352 default: 353 d = 0; 354 } 355 356 if (big_endian) 357 for (i = 0; i < d; i++) 358 put_unaligned(be32_to_cpup((__be32 *)in + i), &hash[i]); 359 else 360 for (i = 0; i < d; i++) 361 put_unaligned(le32_to_cpup((__le32 *)in + i), &hash[i]); 362 } 363 364 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length, 365 int final, int dma) 366 { 367 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 368 u32 val = length << 5, mask; 369 370 if (likely(ctx->digcnt)) 371 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt); 372 373 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 374 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0), 375 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN); 376 /* 377 * Setting ALGO_CONST only for the first iteration 378 * and CLOSE_HASH only for the last one. 379 */ 380 if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1) 381 val |= SHA_REG_CTRL_ALGO; 382 if (!ctx->digcnt) 383 val |= SHA_REG_CTRL_ALGO_CONST; 384 if (final) 385 val |= SHA_REG_CTRL_CLOSE_HASH; 386 387 mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH | 388 SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH; 389 390 omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask); 391 } 392 393 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length) 394 { 395 } 396 397 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd) 398 { 399 return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY); 400 } 401 402 static int get_block_size(struct omap_sham_reqctx *ctx) 403 { 404 int d; 405 406 switch (ctx->flags & FLAGS_MODE_MASK) { 407 case FLAGS_MODE_MD5: 408 case FLAGS_MODE_SHA1: 409 d = SHA1_BLOCK_SIZE; 410 break; 411 case FLAGS_MODE_SHA224: 412 case FLAGS_MODE_SHA256: 413 d = SHA256_BLOCK_SIZE; 414 break; 415 case FLAGS_MODE_SHA384: 416 case FLAGS_MODE_SHA512: 417 d = SHA512_BLOCK_SIZE; 418 break; 419 default: 420 d = 0; 421 } 422 423 return d; 424 } 425 426 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset, 427 u32 *value, int count) 428 { 429 for (; count--; value++, offset += 4) 430 omap_sham_write(dd, offset, *value); 431 } 432 433 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length, 434 int final, int dma) 435 { 436 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 437 u32 val, mask; 438 439 if (likely(ctx->digcnt)) 440 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt); 441 442 /* 443 * Setting ALGO_CONST only for the first iteration and 444 * CLOSE_HASH only for the last one. Note that flags mode bits 445 * correspond to algorithm encoding in mode register. 446 */ 447 val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT); 448 if (!ctx->digcnt) { 449 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req); 450 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); 451 struct omap_sham_hmac_ctx *bctx = tctx->base; 452 int bs, nr_dr; 453 454 val |= SHA_REG_MODE_ALGO_CONSTANT; 455 456 if (ctx->flags & BIT(FLAGS_HMAC)) { 457 bs = get_block_size(ctx); 458 nr_dr = bs / (2 * sizeof(u32)); 459 val |= SHA_REG_MODE_HMAC_KEY_PROC; 460 omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0), 461 (u32 *)bctx->ipad, nr_dr); 462 omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0), 463 (u32 *)bctx->ipad + nr_dr, nr_dr); 464 ctx->digcnt += bs; 465 } 466 } 467 468 if (final) { 469 val |= SHA_REG_MODE_CLOSE_HASH; 470 471 if (ctx->flags & BIT(FLAGS_HMAC)) 472 val |= SHA_REG_MODE_HMAC_OUTER_HASH; 473 } 474 475 mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH | 476 SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH | 477 SHA_REG_MODE_HMAC_KEY_PROC; 478 479 dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags); 480 omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask); 481 omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY); 482 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 483 SHA_REG_MASK_IT_EN | 484 (dma ? SHA_REG_MASK_DMA_EN : 0), 485 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN); 486 } 487 488 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length) 489 { 490 omap_sham_write(dd, SHA_REG_LENGTH(dd), length); 491 } 492 493 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd) 494 { 495 return omap_sham_wait(dd, SHA_REG_IRQSTATUS, 496 SHA_REG_IRQSTATUS_INPUT_RDY); 497 } 498 499 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, size_t length, 500 int final) 501 { 502 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 503 int count, len32, bs32, offset = 0; 504 const u32 *buffer; 505 int mlen; 506 struct sg_mapping_iter mi; 507 508 dev_dbg(dd->dev, "xmit_cpu: digcnt: %zd, length: %zd, final: %d\n", 509 ctx->digcnt, length, final); 510 511 dd->pdata->write_ctrl(dd, length, final, 0); 512 dd->pdata->trigger(dd, length); 513 514 /* should be non-zero before next lines to disable clocks later */ 515 ctx->digcnt += length; 516 ctx->total -= length; 517 518 if (final) 519 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */ 520 521 set_bit(FLAGS_CPU, &dd->flags); 522 523 len32 = DIV_ROUND_UP(length, sizeof(u32)); 524 bs32 = get_block_size(ctx) / sizeof(u32); 525 526 sg_miter_start(&mi, ctx->sg, ctx->sg_len, 527 SG_MITER_FROM_SG | SG_MITER_ATOMIC); 528 529 mlen = 0; 530 531 while (len32) { 532 if (dd->pdata->poll_irq(dd)) 533 return -ETIMEDOUT; 534 535 for (count = 0; count < min(len32, bs32); count++, offset++) { 536 if (!mlen) { 537 sg_miter_next(&mi); 538 mlen = mi.length; 539 if (!mlen) { 540 pr_err("sg miter failure.\n"); 541 return -EINVAL; 542 } 543 offset = 0; 544 buffer = mi.addr; 545 } 546 omap_sham_write(dd, SHA_REG_DIN(dd, count), 547 buffer[offset]); 548 mlen -= 4; 549 } 550 len32 -= min(len32, bs32); 551 } 552 553 sg_miter_stop(&mi); 554 555 return -EINPROGRESS; 556 } 557 558 static void omap_sham_dma_callback(void *param) 559 { 560 struct omap_sham_dev *dd = param; 561 562 set_bit(FLAGS_DMA_READY, &dd->flags); 563 queue_work(system_bh_wq, &dd->done_task); 564 } 565 566 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, size_t length, 567 int final) 568 { 569 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 570 struct dma_async_tx_descriptor *tx; 571 struct dma_slave_config cfg; 572 int ret; 573 574 dev_dbg(dd->dev, "xmit_dma: digcnt: %zd, length: %zd, final: %d\n", 575 ctx->digcnt, length, final); 576 577 if (!dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE)) { 578 dev_err(dd->dev, "dma_map_sg error\n"); 579 return -EINVAL; 580 } 581 582 memset(&cfg, 0, sizeof(cfg)); 583 584 cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0); 585 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 586 cfg.dst_maxburst = get_block_size(ctx) / DMA_SLAVE_BUSWIDTH_4_BYTES; 587 588 ret = dmaengine_slave_config(dd->dma_lch, &cfg); 589 if (ret) { 590 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret); 591 return ret; 592 } 593 594 tx = dmaengine_prep_slave_sg(dd->dma_lch, ctx->sg, ctx->sg_len, 595 DMA_MEM_TO_DEV, 596 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 597 598 if (!tx) { 599 dev_err(dd->dev, "prep_slave_sg failed\n"); 600 return -EINVAL; 601 } 602 603 tx->callback = omap_sham_dma_callback; 604 tx->callback_param = dd; 605 606 dd->pdata->write_ctrl(dd, length, final, 1); 607 608 ctx->digcnt += length; 609 ctx->total -= length; 610 611 if (final) 612 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */ 613 614 set_bit(FLAGS_DMA_ACTIVE, &dd->flags); 615 616 dmaengine_submit(tx); 617 dma_async_issue_pending(dd->dma_lch); 618 619 dd->pdata->trigger(dd, length); 620 621 return -EINPROGRESS; 622 } 623 624 static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx, 625 struct scatterlist *sg, int bs, int new_len) 626 { 627 int n = sg_nents(sg); 628 struct scatterlist *tmp; 629 int offset = ctx->offset; 630 631 ctx->total = new_len; 632 633 if (ctx->bufcnt) 634 n++; 635 636 ctx->sg = kmalloc_objs(*sg, n); 637 if (!ctx->sg) 638 return -ENOMEM; 639 640 sg_init_table(ctx->sg, n); 641 642 tmp = ctx->sg; 643 644 ctx->sg_len = 0; 645 646 if (ctx->bufcnt) { 647 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt); 648 tmp = sg_next(tmp); 649 ctx->sg_len++; 650 new_len -= ctx->bufcnt; 651 } 652 653 while (sg && new_len) { 654 int len = sg->length - offset; 655 656 if (len <= 0) { 657 offset -= sg->length; 658 sg = sg_next(sg); 659 continue; 660 } 661 662 if (new_len < len) 663 len = new_len; 664 665 if (len > 0) { 666 new_len -= len; 667 sg_set_page(tmp, sg_page(sg), len, sg->offset + offset); 668 offset = 0; 669 ctx->offset = 0; 670 ctx->sg_len++; 671 if (new_len <= 0) 672 break; 673 tmp = sg_next(tmp); 674 } 675 676 sg = sg_next(sg); 677 } 678 679 if (tmp) 680 sg_mark_end(tmp); 681 682 set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags); 683 684 ctx->offset += new_len - ctx->bufcnt; 685 ctx->bufcnt = 0; 686 687 return 0; 688 } 689 690 static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx, 691 struct scatterlist *sg, int bs, 692 unsigned int new_len) 693 { 694 int pages; 695 void *buf; 696 697 pages = get_order(new_len); 698 699 buf = (void *)__get_free_pages(GFP_ATOMIC, pages); 700 if (!buf) { 701 pr_err("Couldn't allocate pages for unaligned cases.\n"); 702 return -ENOMEM; 703 } 704 705 if (ctx->bufcnt) 706 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt); 707 708 scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset, 709 min(new_len, ctx->total) - ctx->bufcnt, 0); 710 sg_init_table(ctx->sgl, 1); 711 sg_set_buf(ctx->sgl, buf, new_len); 712 ctx->sg = ctx->sgl; 713 set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags); 714 ctx->sg_len = 1; 715 ctx->offset += new_len - ctx->bufcnt; 716 ctx->bufcnt = 0; 717 ctx->total = new_len; 718 719 return 0; 720 } 721 722 static int omap_sham_align_sgs(struct scatterlist *sg, 723 int nbytes, int bs, bool final, 724 struct omap_sham_reqctx *rctx) 725 { 726 int n = 0; 727 bool aligned = true; 728 bool list_ok = true; 729 struct scatterlist *sg_tmp = sg; 730 int new_len; 731 int offset = rctx->offset; 732 int bufcnt = rctx->bufcnt; 733 734 if (!sg || !sg->length || !nbytes) { 735 if (bufcnt) { 736 bufcnt = DIV_ROUND_UP(bufcnt, bs) * bs; 737 sg_init_table(rctx->sgl, 1); 738 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, bufcnt); 739 rctx->sg = rctx->sgl; 740 rctx->sg_len = 1; 741 } 742 743 return 0; 744 } 745 746 new_len = nbytes; 747 748 if (offset) 749 list_ok = false; 750 751 if (final) 752 new_len = DIV_ROUND_UP(new_len, bs) * bs; 753 else 754 new_len = (new_len - 1) / bs * bs; 755 756 if (!new_len) 757 return 0; 758 759 if (nbytes != new_len) 760 list_ok = false; 761 762 while (nbytes > 0 && sg_tmp) { 763 n++; 764 765 if (bufcnt) { 766 if (!IS_ALIGNED(bufcnt, bs)) { 767 aligned = false; 768 break; 769 } 770 nbytes -= bufcnt; 771 bufcnt = 0; 772 if (!nbytes) 773 list_ok = false; 774 775 continue; 776 } 777 778 #ifdef CONFIG_ZONE_DMA 779 if (page_zonenum(sg_page(sg_tmp)) != ZONE_DMA) { 780 aligned = false; 781 break; 782 } 783 #endif 784 785 if (offset < sg_tmp->length) { 786 if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) { 787 aligned = false; 788 break; 789 } 790 791 if (!IS_ALIGNED(sg_tmp->length - offset, bs)) { 792 aligned = false; 793 break; 794 } 795 } 796 797 if (offset) { 798 offset -= sg_tmp->length; 799 if (offset < 0) { 800 nbytes += offset; 801 offset = 0; 802 } 803 } else { 804 nbytes -= sg_tmp->length; 805 } 806 807 sg_tmp = sg_next(sg_tmp); 808 809 if (nbytes < 0) { 810 list_ok = false; 811 break; 812 } 813 } 814 815 if (new_len > OMAP_SHA_MAX_DMA_LEN) { 816 new_len = OMAP_SHA_MAX_DMA_LEN; 817 aligned = false; 818 } 819 820 if (!aligned) 821 return omap_sham_copy_sgs(rctx, sg, bs, new_len); 822 else if (!list_ok) 823 return omap_sham_copy_sg_lists(rctx, sg, bs, new_len); 824 825 rctx->total = new_len; 826 rctx->offset += new_len; 827 rctx->sg_len = n; 828 if (rctx->bufcnt) { 829 sg_init_table(rctx->sgl, 2); 830 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt); 831 sg_chain(rctx->sgl, 2, sg); 832 rctx->sg = rctx->sgl; 833 } else { 834 rctx->sg = sg; 835 } 836 837 return 0; 838 } 839 840 static int omap_sham_prepare_request(struct crypto_engine *engine, void *areq) 841 { 842 struct ahash_request *req = container_of(areq, struct ahash_request, 843 base); 844 struct omap_sham_reqctx *rctx = ahash_request_ctx(req); 845 int bs; 846 int ret; 847 unsigned int nbytes; 848 bool final = rctx->flags & BIT(FLAGS_FINUP); 849 bool update = rctx->op == OP_UPDATE; 850 int hash_later; 851 852 bs = get_block_size(rctx); 853 854 nbytes = rctx->bufcnt; 855 856 if (update) 857 nbytes += req->nbytes - rctx->offset; 858 859 dev_dbg(rctx->dd->dev, 860 "%s: nbytes=%d, bs=%d, total=%d, offset=%d, bufcnt=%zd\n", 861 __func__, nbytes, bs, rctx->total, rctx->offset, 862 rctx->bufcnt); 863 864 if (!nbytes) 865 return 0; 866 867 rctx->total = nbytes; 868 869 if (update && req->nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) { 870 int len = bs - rctx->bufcnt % bs; 871 872 if (len > req->nbytes) 873 len = req->nbytes; 874 scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src, 875 0, len, 0); 876 rctx->bufcnt += len; 877 rctx->offset = len; 878 } 879 880 if (rctx->bufcnt) 881 memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt); 882 883 ret = omap_sham_align_sgs(req->src, nbytes, bs, final, rctx); 884 if (ret) 885 return ret; 886 887 hash_later = nbytes - rctx->total; 888 if (hash_later < 0) 889 hash_later = 0; 890 891 if (hash_later && hash_later <= sizeof(rctx->buffer)) { 892 scatterwalk_map_and_copy(rctx->buffer, 893 req->src, 894 req->nbytes - hash_later, 895 hash_later, 0); 896 897 rctx->bufcnt = hash_later; 898 } else { 899 rctx->bufcnt = 0; 900 } 901 902 if (hash_later > sizeof(rctx->buffer)) 903 set_bit(FLAGS_HUGE, &rctx->dd->flags); 904 905 rctx->total = min(nbytes, rctx->total); 906 907 return 0; 908 } 909 910 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd) 911 { 912 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); 913 914 dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE); 915 916 clear_bit(FLAGS_DMA_ACTIVE, &dd->flags); 917 918 return 0; 919 } 920 921 static struct omap_sham_dev *omap_sham_find_dev(struct omap_sham_reqctx *ctx) 922 { 923 struct omap_sham_dev *dd; 924 925 if (ctx->dd) 926 return ctx->dd; 927 928 spin_lock_bh(&sham.lock); 929 dd = list_first_entry(&sham.dev_list, struct omap_sham_dev, list); 930 list_move_tail(&dd->list, &sham.dev_list); 931 ctx->dd = dd; 932 spin_unlock_bh(&sham.lock); 933 934 return dd; 935 } 936 937 static int omap_sham_init(struct ahash_request *req) 938 { 939 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 940 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); 941 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 942 struct omap_sham_dev *dd; 943 int bs = 0; 944 945 ctx->dd = NULL; 946 947 dd = omap_sham_find_dev(ctx); 948 if (!dd) 949 return -ENODEV; 950 951 ctx->flags = 0; 952 953 dev_dbg(dd->dev, "init: digest size: %d\n", 954 crypto_ahash_digestsize(tfm)); 955 956 switch (crypto_ahash_digestsize(tfm)) { 957 case MD5_DIGEST_SIZE: 958 ctx->flags |= FLAGS_MODE_MD5; 959 bs = SHA1_BLOCK_SIZE; 960 break; 961 case SHA1_DIGEST_SIZE: 962 ctx->flags |= FLAGS_MODE_SHA1; 963 bs = SHA1_BLOCK_SIZE; 964 break; 965 case SHA224_DIGEST_SIZE: 966 ctx->flags |= FLAGS_MODE_SHA224; 967 bs = SHA224_BLOCK_SIZE; 968 break; 969 case SHA256_DIGEST_SIZE: 970 ctx->flags |= FLAGS_MODE_SHA256; 971 bs = SHA256_BLOCK_SIZE; 972 break; 973 case SHA384_DIGEST_SIZE: 974 ctx->flags |= FLAGS_MODE_SHA384; 975 bs = SHA384_BLOCK_SIZE; 976 break; 977 case SHA512_DIGEST_SIZE: 978 ctx->flags |= FLAGS_MODE_SHA512; 979 bs = SHA512_BLOCK_SIZE; 980 break; 981 } 982 983 ctx->bufcnt = 0; 984 ctx->digcnt = 0; 985 ctx->total = 0; 986 ctx->offset = 0; 987 988 if (tctx->flags & BIT(FLAGS_HMAC)) { 989 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) { 990 struct omap_sham_hmac_ctx *bctx = tctx->base; 991 992 memcpy(ctx->buffer, bctx->ipad, bs); 993 ctx->bufcnt = bs; 994 } 995 996 ctx->flags |= BIT(FLAGS_HMAC); 997 } 998 999 return 0; 1000 1001 } 1002 1003 static int omap_sham_update_req(struct omap_sham_dev *dd) 1004 { 1005 struct ahash_request *req = dd->req; 1006 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1007 int err; 1008 bool final = (ctx->flags & BIT(FLAGS_FINUP)) && 1009 !(dd->flags & BIT(FLAGS_HUGE)); 1010 1011 dev_dbg(dd->dev, "update_req: total: %u, digcnt: %zd, final: %d", 1012 ctx->total, ctx->digcnt, final); 1013 1014 if (ctx->total < get_block_size(ctx) || 1015 ctx->total < dd->fallback_sz) 1016 ctx->flags |= BIT(FLAGS_CPU); 1017 1018 if (ctx->flags & BIT(FLAGS_CPU)) 1019 err = omap_sham_xmit_cpu(dd, ctx->total, final); 1020 else 1021 err = omap_sham_xmit_dma(dd, ctx->total, final); 1022 1023 /* wait for dma completion before can take more data */ 1024 dev_dbg(dd->dev, "update: err: %d, digcnt: %zd\n", err, ctx->digcnt); 1025 1026 return err; 1027 } 1028 1029 static int omap_sham_final_req(struct omap_sham_dev *dd) 1030 { 1031 struct ahash_request *req = dd->req; 1032 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1033 int err = 0, use_dma = 1; 1034 1035 if (dd->flags & BIT(FLAGS_HUGE)) 1036 return 0; 1037 1038 if ((ctx->total <= get_block_size(ctx)) || dd->polling_mode) 1039 /* 1040 * faster to handle last block with cpu or 1041 * use cpu when dma is not present. 1042 */ 1043 use_dma = 0; 1044 1045 if (use_dma) 1046 err = omap_sham_xmit_dma(dd, ctx->total, 1); 1047 else 1048 err = omap_sham_xmit_cpu(dd, ctx->total, 1); 1049 1050 ctx->bufcnt = 0; 1051 1052 dev_dbg(dd->dev, "final_req: err: %d\n", err); 1053 1054 return err; 1055 } 1056 1057 static int omap_sham_hash_one_req(struct crypto_engine *engine, void *areq) 1058 { 1059 struct ahash_request *req = container_of(areq, struct ahash_request, 1060 base); 1061 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1062 struct omap_sham_dev *dd = ctx->dd; 1063 int err; 1064 bool final = (ctx->flags & BIT(FLAGS_FINUP)) && 1065 !(dd->flags & BIT(FLAGS_HUGE)); 1066 1067 dev_dbg(dd->dev, "hash-one: op: %u, total: %u, digcnt: %zd, final: %d", 1068 ctx->op, ctx->total, ctx->digcnt, final); 1069 1070 err = omap_sham_prepare_request(engine, areq); 1071 if (err) 1072 return err; 1073 1074 err = pm_runtime_resume_and_get(dd->dev); 1075 if (err < 0) { 1076 dev_err(dd->dev, "failed to get sync: %d\n", err); 1077 return err; 1078 } 1079 1080 dd->err = 0; 1081 dd->req = req; 1082 1083 if (ctx->digcnt) 1084 dd->pdata->copy_hash(req, 0); 1085 1086 if (ctx->op == OP_UPDATE) 1087 err = omap_sham_update_req(dd); 1088 else if (ctx->op == OP_FINAL) 1089 err = omap_sham_final_req(dd); 1090 1091 if (err != -EINPROGRESS) 1092 omap_sham_finish_req(req, err); 1093 1094 return 0; 1095 } 1096 1097 static int omap_sham_finish_hmac(struct ahash_request *req) 1098 { 1099 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 1100 struct omap_sham_hmac_ctx *bctx = tctx->base; 1101 int bs = crypto_shash_blocksize(bctx->shash); 1102 int ds = crypto_shash_digestsize(bctx->shash); 1103 SHASH_DESC_ON_STACK(shash, bctx->shash); 1104 1105 shash->tfm = bctx->shash; 1106 1107 return crypto_shash_init(shash) ?: 1108 crypto_shash_update(shash, bctx->opad, bs) ?: 1109 crypto_shash_finup(shash, req->result, ds, req->result); 1110 } 1111 1112 static int omap_sham_finish(struct ahash_request *req) 1113 { 1114 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1115 struct omap_sham_dev *dd = ctx->dd; 1116 int err = 0; 1117 1118 if (ctx->digcnt) { 1119 omap_sham_copy_ready_hash(req); 1120 if ((ctx->flags & BIT(FLAGS_HMAC)) && 1121 !test_bit(FLAGS_AUTO_XOR, &dd->flags)) 1122 err = omap_sham_finish_hmac(req); 1123 } 1124 1125 dev_dbg(dd->dev, "digcnt: %zd, bufcnt: %zd\n", ctx->digcnt, ctx->bufcnt); 1126 1127 return err; 1128 } 1129 1130 static void omap_sham_finish_req(struct ahash_request *req, int err) 1131 { 1132 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1133 struct omap_sham_dev *dd = ctx->dd; 1134 1135 if (test_bit(FLAGS_SGS_COPIED, &dd->flags)) 1136 free_pages((unsigned long)sg_virt(ctx->sg), 1137 get_order(ctx->sg->length)); 1138 1139 if (test_bit(FLAGS_SGS_ALLOCED, &dd->flags)) 1140 kfree(ctx->sg); 1141 1142 ctx->sg = NULL; 1143 1144 dd->flags &= ~(BIT(FLAGS_SGS_ALLOCED) | BIT(FLAGS_SGS_COPIED) | 1145 BIT(FLAGS_CPU) | BIT(FLAGS_DMA_READY) | 1146 BIT(FLAGS_OUTPUT_READY)); 1147 1148 if (!err) 1149 dd->pdata->copy_hash(req, 1); 1150 1151 if (dd->flags & BIT(FLAGS_HUGE)) { 1152 /* Re-enqueue the request */ 1153 omap_sham_enqueue(req, ctx->op); 1154 return; 1155 } 1156 1157 if (!err) { 1158 if (test_bit(FLAGS_FINAL, &dd->flags)) 1159 err = omap_sham_finish(req); 1160 } else { 1161 ctx->flags |= BIT(FLAGS_ERROR); 1162 } 1163 1164 /* atomic operation is not needed here */ 1165 dd->flags &= ~(BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) | 1166 BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY)); 1167 1168 pm_runtime_put_autosuspend(dd->dev); 1169 1170 ctx->offset = 0; 1171 1172 crypto_finalize_hash_request(dd->engine, req, err); 1173 } 1174 1175 static int omap_sham_handle_queue(struct omap_sham_dev *dd, 1176 struct ahash_request *req) 1177 { 1178 return crypto_transfer_hash_request_to_engine(dd->engine, req); 1179 } 1180 1181 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op) 1182 { 1183 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1184 struct omap_sham_dev *dd = ctx->dd; 1185 1186 ctx->op = op; 1187 1188 return omap_sham_handle_queue(dd, req); 1189 } 1190 1191 static int omap_sham_update(struct ahash_request *req) 1192 { 1193 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1194 struct omap_sham_dev *dd = omap_sham_find_dev(ctx); 1195 1196 if (!req->nbytes) 1197 return 0; 1198 1199 if (ctx->bufcnt + req->nbytes <= sizeof(ctx->buffer)) { 1200 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src, 1201 0, req->nbytes, 0); 1202 ctx->bufcnt += req->nbytes; 1203 return 0; 1204 } 1205 1206 if (dd->polling_mode) 1207 ctx->flags |= BIT(FLAGS_CPU); 1208 1209 return omap_sham_enqueue(req, OP_UPDATE); 1210 } 1211 1212 static int omap_sham_final_shash(struct ahash_request *req) 1213 { 1214 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 1215 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1216 int offset = 0; 1217 1218 /* 1219 * If we are running HMAC on limited hardware support, skip 1220 * the ipad in the beginning of the buffer if we are going for 1221 * software fallback algorithm. 1222 */ 1223 if (test_bit(FLAGS_HMAC, &ctx->flags) && 1224 !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags)) 1225 offset = get_block_size(ctx); 1226 1227 return crypto_shash_tfm_digest(tctx->fallback, ctx->buffer + offset, 1228 ctx->bufcnt - offset, req->result); 1229 } 1230 1231 static int omap_sham_final(struct ahash_request *req) 1232 { 1233 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1234 1235 ctx->flags |= BIT(FLAGS_FINUP); 1236 1237 if (ctx->flags & BIT(FLAGS_ERROR)) 1238 return 0; /* uncompleted hash is not needed */ 1239 1240 /* 1241 * OMAP HW accel works only with buffers >= 9. 1242 * HMAC is always >= 9 because ipad == block size. 1243 * If buffersize is less than fallback_sz, we use fallback 1244 * SW encoding, as using DMA + HW in this case doesn't provide 1245 * any benefit. 1246 */ 1247 if (!ctx->digcnt && ctx->bufcnt < ctx->dd->fallback_sz) 1248 return omap_sham_final_shash(req); 1249 else if (ctx->bufcnt) 1250 return omap_sham_enqueue(req, OP_FINAL); 1251 1252 /* copy ready hash (+ finalize hmac) */ 1253 return omap_sham_finish(req); 1254 } 1255 1256 static int omap_sham_finup(struct ahash_request *req) 1257 { 1258 struct omap_sham_reqctx *ctx = ahash_request_ctx(req); 1259 int err1, err2; 1260 1261 ctx->flags |= BIT(FLAGS_FINUP); 1262 1263 err1 = omap_sham_update(req); 1264 if (err1 == -EINPROGRESS || err1 == -EBUSY) 1265 return err1; 1266 /* 1267 * final() has to be always called to cleanup resources 1268 * even if udpate() failed, except EINPROGRESS 1269 */ 1270 err2 = omap_sham_final(req); 1271 1272 return err1 ?: err2; 1273 } 1274 1275 static int omap_sham_digest(struct ahash_request *req) 1276 { 1277 return omap_sham_init(req) ?: omap_sham_finup(req); 1278 } 1279 1280 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key, 1281 unsigned int keylen) 1282 { 1283 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); 1284 struct omap_sham_hmac_ctx *bctx = tctx->base; 1285 int bs = crypto_shash_blocksize(bctx->shash); 1286 int ds = crypto_shash_digestsize(bctx->shash); 1287 int err, i; 1288 1289 err = crypto_shash_setkey(tctx->fallback, key, keylen); 1290 if (err) 1291 return err; 1292 1293 if (keylen > bs) { 1294 err = crypto_shash_tfm_digest(bctx->shash, key, keylen, 1295 bctx->ipad); 1296 if (err) 1297 return err; 1298 keylen = ds; 1299 } else { 1300 memcpy(bctx->ipad, key, keylen); 1301 } 1302 1303 memset(bctx->ipad + keylen, 0, bs - keylen); 1304 1305 if (!test_bit(FLAGS_AUTO_XOR, &sham.flags)) { 1306 memcpy(bctx->opad, bctx->ipad, bs); 1307 1308 for (i = 0; i < bs; i++) { 1309 bctx->ipad[i] ^= HMAC_IPAD_VALUE; 1310 bctx->opad[i] ^= HMAC_OPAD_VALUE; 1311 } 1312 } 1313 1314 return err; 1315 } 1316 1317 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base) 1318 { 1319 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm); 1320 const char *alg_name = crypto_tfm_alg_name(tfm); 1321 1322 /* Allocate a fallback and abort if it failed. */ 1323 tctx->fallback = crypto_alloc_shash(alg_name, 0, 1324 CRYPTO_ALG_NEED_FALLBACK); 1325 if (IS_ERR(tctx->fallback)) { 1326 pr_err("omap-sham: fallback driver '%s' " 1327 "could not be loaded.\n", alg_name); 1328 return PTR_ERR(tctx->fallback); 1329 } 1330 1331 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), 1332 sizeof(struct omap_sham_reqctx)); 1333 1334 if (alg_base) { 1335 struct omap_sham_hmac_ctx *bctx = tctx->base; 1336 tctx->flags |= BIT(FLAGS_HMAC); 1337 bctx->shash = crypto_alloc_shash(alg_base, 0, 1338 CRYPTO_ALG_NEED_FALLBACK); 1339 if (IS_ERR(bctx->shash)) { 1340 pr_err("omap-sham: base driver '%s' " 1341 "could not be loaded.\n", alg_base); 1342 crypto_free_shash(tctx->fallback); 1343 return PTR_ERR(bctx->shash); 1344 } 1345 1346 } 1347 1348 return 0; 1349 } 1350 1351 static int omap_sham_cra_init(struct crypto_tfm *tfm) 1352 { 1353 return omap_sham_cra_init_alg(tfm, NULL); 1354 } 1355 1356 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm) 1357 { 1358 return omap_sham_cra_init_alg(tfm, "sha1"); 1359 } 1360 1361 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm) 1362 { 1363 return omap_sham_cra_init_alg(tfm, "sha224"); 1364 } 1365 1366 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm) 1367 { 1368 return omap_sham_cra_init_alg(tfm, "sha256"); 1369 } 1370 1371 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm) 1372 { 1373 return omap_sham_cra_init_alg(tfm, "md5"); 1374 } 1375 1376 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm) 1377 { 1378 return omap_sham_cra_init_alg(tfm, "sha384"); 1379 } 1380 1381 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm) 1382 { 1383 return omap_sham_cra_init_alg(tfm, "sha512"); 1384 } 1385 1386 static void omap_sham_cra_exit(struct crypto_tfm *tfm) 1387 { 1388 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm); 1389 1390 crypto_free_shash(tctx->fallback); 1391 tctx->fallback = NULL; 1392 1393 if (tctx->flags & BIT(FLAGS_HMAC)) { 1394 struct omap_sham_hmac_ctx *bctx = tctx->base; 1395 crypto_free_shash(bctx->shash); 1396 } 1397 } 1398 1399 static int omap_sham_export(struct ahash_request *req, void *out) 1400 { 1401 struct omap_sham_reqctx *rctx = ahash_request_ctx(req); 1402 1403 memcpy(out, rctx, offsetof(struct omap_sham_reqctx, buffer) + 1404 rctx->bufcnt); 1405 1406 return 0; 1407 } 1408 1409 static int omap_sham_import(struct ahash_request *req, const void *in) 1410 { 1411 struct omap_sham_reqctx *rctx = ahash_request_ctx(req); 1412 const struct omap_sham_reqctx *ctx_in = in; 1413 1414 memcpy(rctx, in, offsetof(struct omap_sham_reqctx, buffer) + 1415 ctx_in->bufcnt); 1416 1417 return 0; 1418 } 1419 1420 static struct ahash_engine_alg algs_sha1_md5[] = { 1421 { 1422 .base.init = omap_sham_init, 1423 .base.update = omap_sham_update, 1424 .base.final = omap_sham_final, 1425 .base.finup = omap_sham_finup, 1426 .base.digest = omap_sham_digest, 1427 .base.halg.digestsize = SHA1_DIGEST_SIZE, 1428 .base.halg.base = { 1429 .cra_name = "sha1", 1430 .cra_driver_name = "omap-sha1", 1431 .cra_priority = 400, 1432 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1433 CRYPTO_ALG_ASYNC | 1434 CRYPTO_ALG_NEED_FALLBACK, 1435 .cra_blocksize = SHA1_BLOCK_SIZE, 1436 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1437 .cra_module = THIS_MODULE, 1438 .cra_init = omap_sham_cra_init, 1439 .cra_exit = omap_sham_cra_exit, 1440 }, 1441 .op.do_one_request = omap_sham_hash_one_req, 1442 }, 1443 { 1444 .base.init = omap_sham_init, 1445 .base.update = omap_sham_update, 1446 .base.final = omap_sham_final, 1447 .base.finup = omap_sham_finup, 1448 .base.digest = omap_sham_digest, 1449 .base.halg.digestsize = MD5_DIGEST_SIZE, 1450 .base.halg.base = { 1451 .cra_name = "md5", 1452 .cra_driver_name = "omap-md5", 1453 .cra_priority = 400, 1454 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1455 CRYPTO_ALG_ASYNC | 1456 CRYPTO_ALG_NEED_FALLBACK, 1457 .cra_blocksize = SHA1_BLOCK_SIZE, 1458 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1459 .cra_module = THIS_MODULE, 1460 .cra_init = omap_sham_cra_init, 1461 .cra_exit = omap_sham_cra_exit, 1462 }, 1463 .op.do_one_request = omap_sham_hash_one_req, 1464 }, 1465 { 1466 .base.init = omap_sham_init, 1467 .base.update = omap_sham_update, 1468 .base.final = omap_sham_final, 1469 .base.finup = omap_sham_finup, 1470 .base.digest = omap_sham_digest, 1471 .base.setkey = omap_sham_setkey, 1472 .base.halg.digestsize = SHA1_DIGEST_SIZE, 1473 .base.halg.base = { 1474 .cra_name = "hmac(sha1)", 1475 .cra_driver_name = "omap-hmac-sha1", 1476 .cra_priority = 400, 1477 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1478 CRYPTO_ALG_ASYNC | 1479 CRYPTO_ALG_NEED_FALLBACK, 1480 .cra_blocksize = SHA1_BLOCK_SIZE, 1481 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1482 sizeof(struct omap_sham_hmac_ctx), 1483 .cra_module = THIS_MODULE, 1484 .cra_init = omap_sham_cra_sha1_init, 1485 .cra_exit = omap_sham_cra_exit, 1486 }, 1487 .op.do_one_request = omap_sham_hash_one_req, 1488 }, 1489 { 1490 .base.init = omap_sham_init, 1491 .base.update = omap_sham_update, 1492 .base.final = omap_sham_final, 1493 .base.finup = omap_sham_finup, 1494 .base.digest = omap_sham_digest, 1495 .base.setkey = omap_sham_setkey, 1496 .base.halg.digestsize = MD5_DIGEST_SIZE, 1497 .base.halg.base = { 1498 .cra_name = "hmac(md5)", 1499 .cra_driver_name = "omap-hmac-md5", 1500 .cra_priority = 400, 1501 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1502 CRYPTO_ALG_ASYNC | 1503 CRYPTO_ALG_NEED_FALLBACK, 1504 .cra_blocksize = SHA1_BLOCK_SIZE, 1505 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1506 sizeof(struct omap_sham_hmac_ctx), 1507 .cra_module = THIS_MODULE, 1508 .cra_init = omap_sham_cra_md5_init, 1509 .cra_exit = omap_sham_cra_exit, 1510 }, 1511 .op.do_one_request = omap_sham_hash_one_req, 1512 } 1513 }; 1514 1515 /* OMAP4 has some algs in addition to what OMAP2 has */ 1516 static struct ahash_engine_alg algs_sha224_sha256[] = { 1517 { 1518 .base.init = omap_sham_init, 1519 .base.update = omap_sham_update, 1520 .base.final = omap_sham_final, 1521 .base.finup = omap_sham_finup, 1522 .base.digest = omap_sham_digest, 1523 .base.halg.digestsize = SHA224_DIGEST_SIZE, 1524 .base.halg.base = { 1525 .cra_name = "sha224", 1526 .cra_driver_name = "omap-sha224", 1527 .cra_priority = 400, 1528 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1529 CRYPTO_ALG_ASYNC | 1530 CRYPTO_ALG_NEED_FALLBACK, 1531 .cra_blocksize = SHA224_BLOCK_SIZE, 1532 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1533 .cra_module = THIS_MODULE, 1534 .cra_init = omap_sham_cra_init, 1535 .cra_exit = omap_sham_cra_exit, 1536 }, 1537 .op.do_one_request = omap_sham_hash_one_req, 1538 }, 1539 { 1540 .base.init = omap_sham_init, 1541 .base.update = omap_sham_update, 1542 .base.final = omap_sham_final, 1543 .base.finup = omap_sham_finup, 1544 .base.digest = omap_sham_digest, 1545 .base.halg.digestsize = SHA256_DIGEST_SIZE, 1546 .base.halg.base = { 1547 .cra_name = "sha256", 1548 .cra_driver_name = "omap-sha256", 1549 .cra_priority = 400, 1550 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1551 CRYPTO_ALG_ASYNC | 1552 CRYPTO_ALG_NEED_FALLBACK, 1553 .cra_blocksize = SHA256_BLOCK_SIZE, 1554 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1555 .cra_module = THIS_MODULE, 1556 .cra_init = omap_sham_cra_init, 1557 .cra_exit = omap_sham_cra_exit, 1558 }, 1559 .op.do_one_request = omap_sham_hash_one_req, 1560 }, 1561 { 1562 .base.init = omap_sham_init, 1563 .base.update = omap_sham_update, 1564 .base.final = omap_sham_final, 1565 .base.finup = omap_sham_finup, 1566 .base.digest = omap_sham_digest, 1567 .base.setkey = omap_sham_setkey, 1568 .base.halg.digestsize = SHA224_DIGEST_SIZE, 1569 .base.halg.base = { 1570 .cra_name = "hmac(sha224)", 1571 .cra_driver_name = "omap-hmac-sha224", 1572 .cra_priority = 400, 1573 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1574 CRYPTO_ALG_ASYNC | 1575 CRYPTO_ALG_NEED_FALLBACK, 1576 .cra_blocksize = SHA224_BLOCK_SIZE, 1577 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1578 sizeof(struct omap_sham_hmac_ctx), 1579 .cra_module = THIS_MODULE, 1580 .cra_init = omap_sham_cra_sha224_init, 1581 .cra_exit = omap_sham_cra_exit, 1582 }, 1583 .op.do_one_request = omap_sham_hash_one_req, 1584 }, 1585 { 1586 .base.init = omap_sham_init, 1587 .base.update = omap_sham_update, 1588 .base.final = omap_sham_final, 1589 .base.finup = omap_sham_finup, 1590 .base.digest = omap_sham_digest, 1591 .base.setkey = omap_sham_setkey, 1592 .base.halg.digestsize = SHA256_DIGEST_SIZE, 1593 .base.halg.base = { 1594 .cra_name = "hmac(sha256)", 1595 .cra_driver_name = "omap-hmac-sha256", 1596 .cra_priority = 400, 1597 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1598 CRYPTO_ALG_ASYNC | 1599 CRYPTO_ALG_NEED_FALLBACK, 1600 .cra_blocksize = SHA256_BLOCK_SIZE, 1601 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1602 sizeof(struct omap_sham_hmac_ctx), 1603 .cra_module = THIS_MODULE, 1604 .cra_init = omap_sham_cra_sha256_init, 1605 .cra_exit = omap_sham_cra_exit, 1606 }, 1607 .op.do_one_request = omap_sham_hash_one_req, 1608 }, 1609 }; 1610 1611 static struct ahash_engine_alg algs_sha384_sha512[] = { 1612 { 1613 .base.init = omap_sham_init, 1614 .base.update = omap_sham_update, 1615 .base.final = omap_sham_final, 1616 .base.finup = omap_sham_finup, 1617 .base.digest = omap_sham_digest, 1618 .base.halg.digestsize = SHA384_DIGEST_SIZE, 1619 .base.halg.base = { 1620 .cra_name = "sha384", 1621 .cra_driver_name = "omap-sha384", 1622 .cra_priority = 400, 1623 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1624 CRYPTO_ALG_ASYNC | 1625 CRYPTO_ALG_NEED_FALLBACK, 1626 .cra_blocksize = SHA384_BLOCK_SIZE, 1627 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1628 .cra_module = THIS_MODULE, 1629 .cra_init = omap_sham_cra_init, 1630 .cra_exit = omap_sham_cra_exit, 1631 }, 1632 .op.do_one_request = omap_sham_hash_one_req, 1633 }, 1634 { 1635 .base.init = omap_sham_init, 1636 .base.update = omap_sham_update, 1637 .base.final = omap_sham_final, 1638 .base.finup = omap_sham_finup, 1639 .base.digest = omap_sham_digest, 1640 .base.halg.digestsize = SHA512_DIGEST_SIZE, 1641 .base.halg.base = { 1642 .cra_name = "sha512", 1643 .cra_driver_name = "omap-sha512", 1644 .cra_priority = 400, 1645 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1646 CRYPTO_ALG_ASYNC | 1647 CRYPTO_ALG_NEED_FALLBACK, 1648 .cra_blocksize = SHA512_BLOCK_SIZE, 1649 .cra_ctxsize = sizeof(struct omap_sham_ctx), 1650 .cra_module = THIS_MODULE, 1651 .cra_init = omap_sham_cra_init, 1652 .cra_exit = omap_sham_cra_exit, 1653 }, 1654 .op.do_one_request = omap_sham_hash_one_req, 1655 }, 1656 { 1657 .base.init = omap_sham_init, 1658 .base.update = omap_sham_update, 1659 .base.final = omap_sham_final, 1660 .base.finup = omap_sham_finup, 1661 .base.digest = omap_sham_digest, 1662 .base.setkey = omap_sham_setkey, 1663 .base.halg.digestsize = SHA384_DIGEST_SIZE, 1664 .base.halg.base = { 1665 .cra_name = "hmac(sha384)", 1666 .cra_driver_name = "omap-hmac-sha384", 1667 .cra_priority = 400, 1668 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1669 CRYPTO_ALG_ASYNC | 1670 CRYPTO_ALG_NEED_FALLBACK, 1671 .cra_blocksize = SHA384_BLOCK_SIZE, 1672 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1673 sizeof(struct omap_sham_hmac_ctx), 1674 .cra_module = THIS_MODULE, 1675 .cra_init = omap_sham_cra_sha384_init, 1676 .cra_exit = omap_sham_cra_exit, 1677 }, 1678 .op.do_one_request = omap_sham_hash_one_req, 1679 }, 1680 { 1681 .base.init = omap_sham_init, 1682 .base.update = omap_sham_update, 1683 .base.final = omap_sham_final, 1684 .base.finup = omap_sham_finup, 1685 .base.digest = omap_sham_digest, 1686 .base.setkey = omap_sham_setkey, 1687 .base.halg.digestsize = SHA512_DIGEST_SIZE, 1688 .base.halg.base = { 1689 .cra_name = "hmac(sha512)", 1690 .cra_driver_name = "omap-hmac-sha512", 1691 .cra_priority = 400, 1692 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1693 CRYPTO_ALG_ASYNC | 1694 CRYPTO_ALG_NEED_FALLBACK, 1695 .cra_blocksize = SHA512_BLOCK_SIZE, 1696 .cra_ctxsize = sizeof(struct omap_sham_ctx) + 1697 sizeof(struct omap_sham_hmac_ctx), 1698 .cra_module = THIS_MODULE, 1699 .cra_init = omap_sham_cra_sha512_init, 1700 .cra_exit = omap_sham_cra_exit, 1701 }, 1702 .op.do_one_request = omap_sham_hash_one_req, 1703 }, 1704 }; 1705 1706 static void omap_sham_done_task(struct work_struct *t) 1707 { 1708 struct omap_sham_dev *dd = from_work(dd, t, done_task); 1709 int err = 0; 1710 1711 dev_dbg(dd->dev, "%s: flags=%lx\n", __func__, dd->flags); 1712 1713 if (test_bit(FLAGS_CPU, &dd->flags)) { 1714 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) 1715 goto finish; 1716 } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) { 1717 if (test_bit(FLAGS_DMA_ACTIVE, &dd->flags)) { 1718 omap_sham_update_dma_stop(dd); 1719 if (dd->err) { 1720 err = dd->err; 1721 goto finish; 1722 } 1723 } 1724 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) { 1725 /* hash or semi-hash ready */ 1726 clear_bit(FLAGS_DMA_READY, &dd->flags); 1727 goto finish; 1728 } 1729 } 1730 1731 return; 1732 1733 finish: 1734 dev_dbg(dd->dev, "update done: err: %d\n", err); 1735 /* finish curent request */ 1736 omap_sham_finish_req(dd->req, err); 1737 } 1738 1739 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd) 1740 { 1741 set_bit(FLAGS_OUTPUT_READY, &dd->flags); 1742 queue_work(system_bh_wq, &dd->done_task); 1743 1744 return IRQ_HANDLED; 1745 } 1746 1747 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id) 1748 { 1749 struct omap_sham_dev *dd = dev_id; 1750 1751 if (unlikely(test_bit(FLAGS_FINAL, &dd->flags))) 1752 /* final -> allow device to go to power-saving mode */ 1753 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH); 1754 1755 omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY, 1756 SHA_REG_CTRL_OUTPUT_READY); 1757 omap_sham_read(dd, SHA_REG_CTRL); 1758 1759 return omap_sham_irq_common(dd); 1760 } 1761 1762 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id) 1763 { 1764 struct omap_sham_dev *dd = dev_id; 1765 1766 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN); 1767 1768 return omap_sham_irq_common(dd); 1769 } 1770 1771 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = { 1772 { 1773 .algs_list = algs_sha1_md5, 1774 .size = ARRAY_SIZE(algs_sha1_md5), 1775 }, 1776 }; 1777 1778 static const struct omap_sham_pdata omap_sham_pdata_omap2 = { 1779 .algs_info = omap_sham_algs_info_omap2, 1780 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2), 1781 .flags = BIT(FLAGS_BE32_SHA1), 1782 .digest_size = SHA1_DIGEST_SIZE, 1783 .copy_hash = omap_sham_copy_hash_omap2, 1784 .write_ctrl = omap_sham_write_ctrl_omap2, 1785 .trigger = omap_sham_trigger_omap2, 1786 .poll_irq = omap_sham_poll_irq_omap2, 1787 .intr_hdlr = omap_sham_irq_omap2, 1788 .idigest_ofs = 0x00, 1789 .din_ofs = 0x1c, 1790 .digcnt_ofs = 0x14, 1791 .rev_ofs = 0x5c, 1792 .mask_ofs = 0x60, 1793 .sysstatus_ofs = 0x64, 1794 .major_mask = 0xf0, 1795 .major_shift = 4, 1796 .minor_mask = 0x0f, 1797 .minor_shift = 0, 1798 }; 1799 1800 #ifdef CONFIG_OF 1801 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = { 1802 { 1803 .algs_list = algs_sha1_md5, 1804 .size = ARRAY_SIZE(algs_sha1_md5), 1805 }, 1806 { 1807 .algs_list = algs_sha224_sha256, 1808 .size = ARRAY_SIZE(algs_sha224_sha256), 1809 }, 1810 }; 1811 1812 static const struct omap_sham_pdata omap_sham_pdata_omap4 = { 1813 .algs_info = omap_sham_algs_info_omap4, 1814 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4), 1815 .flags = BIT(FLAGS_AUTO_XOR), 1816 .digest_size = SHA256_DIGEST_SIZE, 1817 .copy_hash = omap_sham_copy_hash_omap4, 1818 .write_ctrl = omap_sham_write_ctrl_omap4, 1819 .trigger = omap_sham_trigger_omap4, 1820 .poll_irq = omap_sham_poll_irq_omap4, 1821 .intr_hdlr = omap_sham_irq_omap4, 1822 .idigest_ofs = 0x020, 1823 .odigest_ofs = 0x0, 1824 .din_ofs = 0x080, 1825 .digcnt_ofs = 0x040, 1826 .rev_ofs = 0x100, 1827 .mask_ofs = 0x110, 1828 .sysstatus_ofs = 0x114, 1829 .mode_ofs = 0x44, 1830 .length_ofs = 0x48, 1831 .major_mask = 0x0700, 1832 .major_shift = 8, 1833 .minor_mask = 0x003f, 1834 .minor_shift = 0, 1835 }; 1836 1837 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = { 1838 { 1839 .algs_list = algs_sha1_md5, 1840 .size = ARRAY_SIZE(algs_sha1_md5), 1841 }, 1842 { 1843 .algs_list = algs_sha224_sha256, 1844 .size = ARRAY_SIZE(algs_sha224_sha256), 1845 }, 1846 { 1847 .algs_list = algs_sha384_sha512, 1848 .size = ARRAY_SIZE(algs_sha384_sha512), 1849 }, 1850 }; 1851 1852 static const struct omap_sham_pdata omap_sham_pdata_omap5 = { 1853 .algs_info = omap_sham_algs_info_omap5, 1854 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5), 1855 .flags = BIT(FLAGS_AUTO_XOR), 1856 .digest_size = SHA512_DIGEST_SIZE, 1857 .copy_hash = omap_sham_copy_hash_omap4, 1858 .write_ctrl = omap_sham_write_ctrl_omap4, 1859 .trigger = omap_sham_trigger_omap4, 1860 .poll_irq = omap_sham_poll_irq_omap4, 1861 .intr_hdlr = omap_sham_irq_omap4, 1862 .idigest_ofs = 0x240, 1863 .odigest_ofs = 0x200, 1864 .din_ofs = 0x080, 1865 .digcnt_ofs = 0x280, 1866 .rev_ofs = 0x100, 1867 .mask_ofs = 0x110, 1868 .sysstatus_ofs = 0x114, 1869 .mode_ofs = 0x284, 1870 .length_ofs = 0x288, 1871 .major_mask = 0x0700, 1872 .major_shift = 8, 1873 .minor_mask = 0x003f, 1874 .minor_shift = 0, 1875 }; 1876 1877 static const struct of_device_id omap_sham_of_match[] = { 1878 { 1879 .compatible = "ti,omap2-sham", 1880 .data = &omap_sham_pdata_omap2, 1881 }, 1882 { 1883 .compatible = "ti,omap3-sham", 1884 .data = &omap_sham_pdata_omap2, 1885 }, 1886 { 1887 .compatible = "ti,omap4-sham", 1888 .data = &omap_sham_pdata_omap4, 1889 }, 1890 { 1891 .compatible = "ti,omap5-sham", 1892 .data = &omap_sham_pdata_omap5, 1893 }, 1894 {}, 1895 }; 1896 MODULE_DEVICE_TABLE(of, omap_sham_of_match); 1897 #endif 1898 1899 static ssize_t fallback_show(struct device *dev, struct device_attribute *attr, 1900 char *buf) 1901 { 1902 struct omap_sham_dev *dd = dev_get_drvdata(dev); 1903 1904 return sysfs_emit(buf, "%d\n", dd->fallback_sz); 1905 } 1906 1907 static ssize_t fallback_store(struct device *dev, struct device_attribute *attr, 1908 const char *buf, size_t size) 1909 { 1910 struct omap_sham_dev *dd = dev_get_drvdata(dev); 1911 ssize_t status; 1912 long value; 1913 1914 status = kstrtol(buf, 0, &value); 1915 if (status) 1916 return status; 1917 1918 /* HW accelerator only works with buffers > 9 */ 1919 if (value < 9) { 1920 dev_err(dev, "minimum fallback size 9\n"); 1921 return -EINVAL; 1922 } 1923 1924 dd->fallback_sz = value; 1925 1926 return size; 1927 } 1928 1929 static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr, 1930 char *buf) 1931 { 1932 struct omap_sham_dev *dd = dev_get_drvdata(dev); 1933 1934 return sysfs_emit(buf, "%d\n", dd->queue.max_qlen); 1935 } 1936 1937 static ssize_t queue_len_store(struct device *dev, 1938 struct device_attribute *attr, const char *buf, 1939 size_t size) 1940 { 1941 struct omap_sham_dev *dd = dev_get_drvdata(dev); 1942 ssize_t status; 1943 long value; 1944 1945 status = kstrtol(buf, 0, &value); 1946 if (status) 1947 return status; 1948 1949 if (value < 1) 1950 return -EINVAL; 1951 1952 /* 1953 * Changing the queue size in fly is safe, if size becomes smaller 1954 * than current size, it will just not accept new entries until 1955 * it has shrank enough. 1956 */ 1957 dd->queue.max_qlen = value; 1958 1959 return size; 1960 } 1961 1962 static DEVICE_ATTR_RW(queue_len); 1963 static DEVICE_ATTR_RW(fallback); 1964 1965 static struct attribute *omap_sham_attrs[] = { 1966 &dev_attr_queue_len.attr, 1967 &dev_attr_fallback.attr, 1968 NULL, 1969 }; 1970 ATTRIBUTE_GROUPS(omap_sham); 1971 1972 static void omap_sham_unregister_algs(const struct omap_sham_pdata *pdata) 1973 { 1974 struct omap_sham_algs_info *alg_info; 1975 int i; 1976 1977 for (i = pdata->algs_info_size - 1; i >= 0; i--) { 1978 alg_info = &pdata->algs_info[i]; 1979 1980 crypto_engine_unregister_ahashes(alg_info->algs_list, 1981 alg_info->registered); 1982 alg_info->registered = 0; 1983 } 1984 } 1985 1986 static int omap_sham_probe(struct platform_device *pdev) 1987 { 1988 struct omap_sham_dev *dd; 1989 struct device *dev = &pdev->dev; 1990 void __iomem *io_base; 1991 struct resource *res; 1992 dma_cap_mask_t mask; 1993 int err, i, j, irq; 1994 u32 rev; 1995 1996 io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1997 if (IS_ERR(io_base)) 1998 return PTR_ERR(io_base); 1999 2000 irq = platform_get_irq(pdev, 0); 2001 if (irq < 0) 2002 return irq; 2003 2004 dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL); 2005 if (dd == NULL) { 2006 dev_err(dev, "unable to alloc data struct.\n"); 2007 err = -ENOMEM; 2008 goto data_err; 2009 } 2010 dd->dev = dev; 2011 platform_set_drvdata(pdev, dd); 2012 2013 INIT_LIST_HEAD(&dd->list); 2014 INIT_WORK(&dd->done_task, omap_sham_done_task); 2015 crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH); 2016 2017 dd->pdata = device_get_match_data(dev); 2018 if (!dd->pdata) 2019 dd->pdata = &omap_sham_pdata_omap2; 2020 2021 dd->irq = irq; 2022 dd->io_base = io_base; 2023 dd->phys_base = res->start; 2024 2025 err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr, 2026 IRQF_TRIGGER_NONE, dev_name(dev), dd); 2027 if (err) 2028 goto data_err; 2029 2030 dma_cap_zero(mask); 2031 dma_cap_set(DMA_SLAVE, mask); 2032 2033 dd->dma_lch = dma_request_chan(dev, "rx"); 2034 if (IS_ERR(dd->dma_lch)) { 2035 err = PTR_ERR(dd->dma_lch); 2036 if (err == -EPROBE_DEFER) 2037 goto data_err; 2038 2039 dd->polling_mode = 1; 2040 dev_dbg(dev, "using polling mode instead of dma\n"); 2041 } 2042 2043 dd->flags |= dd->pdata->flags; 2044 sham.flags |= dd->pdata->flags; 2045 2046 pm_runtime_use_autosuspend(dev); 2047 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY); 2048 2049 dd->fallback_sz = OMAP_SHA_DMA_THRESHOLD; 2050 2051 pm_runtime_enable(dev); 2052 2053 err = pm_runtime_resume_and_get(dev); 2054 if (err < 0) { 2055 dev_err(dev, "failed to get sync: %d\n", err); 2056 goto err_pm; 2057 } 2058 2059 rev = omap_sham_read(dd, SHA_REG_REV(dd)); 2060 pm_runtime_put_sync(&pdev->dev); 2061 2062 dev_info(dev, "hw accel on OMAP rev %u.%u\n", 2063 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift, 2064 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift); 2065 2066 spin_lock_bh(&sham.lock); 2067 list_add_tail(&dd->list, &sham.dev_list); 2068 spin_unlock_bh(&sham.lock); 2069 2070 dd->engine = crypto_engine_alloc_init(dev, 1); 2071 if (!dd->engine) { 2072 err = -ENOMEM; 2073 goto err_engine; 2074 } 2075 2076 err = crypto_engine_start(dd->engine); 2077 if (err) 2078 goto err_engine_start; 2079 2080 for (i = 0; i < dd->pdata->algs_info_size; i++) { 2081 if (dd->pdata->algs_info[i].registered) 2082 break; 2083 2084 for (j = 0; j < dd->pdata->algs_info[i].size; j++) { 2085 struct ahash_engine_alg *ealg; 2086 struct ahash_alg *alg; 2087 2088 ealg = &dd->pdata->algs_info[i].algs_list[j]; 2089 alg = &ealg->base; 2090 alg->export = omap_sham_export; 2091 alg->import = omap_sham_import; 2092 alg->halg.statesize = sizeof(struct omap_sham_reqctx); 2093 err = crypto_engine_register_ahash(ealg); 2094 if (err) 2095 goto err_algs; 2096 2097 dd->pdata->algs_info[i].registered++; 2098 } 2099 } 2100 2101 return 0; 2102 2103 err_algs: 2104 omap_sham_unregister_algs(dd->pdata); 2105 err_engine_start: 2106 crypto_engine_exit(dd->engine); 2107 err_engine: 2108 spin_lock_bh(&sham.lock); 2109 list_del(&dd->list); 2110 spin_unlock_bh(&sham.lock); 2111 err_pm: 2112 pm_runtime_dont_use_autosuspend(dev); 2113 pm_runtime_disable(dev); 2114 if (!dd->polling_mode) 2115 dma_release_channel(dd->dma_lch); 2116 data_err: 2117 dev_err(dev, "initialization failed.\n"); 2118 2119 return err; 2120 } 2121 2122 static void omap_sham_remove(struct platform_device *pdev) 2123 { 2124 struct omap_sham_dev *dd; 2125 2126 dd = platform_get_drvdata(pdev); 2127 2128 spin_lock_bh(&sham.lock); 2129 list_del(&dd->list); 2130 spin_unlock_bh(&sham.lock); 2131 omap_sham_unregister_algs(dd->pdata); 2132 cancel_work_sync(&dd->done_task); 2133 pm_runtime_dont_use_autosuspend(&pdev->dev); 2134 pm_runtime_disable(&pdev->dev); 2135 2136 if (!dd->polling_mode) 2137 dma_release_channel(dd->dma_lch); 2138 } 2139 2140 static struct platform_driver omap_sham_driver = { 2141 .probe = omap_sham_probe, 2142 .remove = omap_sham_remove, 2143 .driver = { 2144 .name = "omap-sham", 2145 .of_match_table = of_match_ptr(omap_sham_of_match), 2146 .dev_groups = omap_sham_groups, 2147 }, 2148 }; 2149 2150 module_platform_driver(omap_sham_driver); 2151 2152 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support."); 2153 MODULE_LICENSE("GPL v2"); 2154 MODULE_AUTHOR("Dmitry Kasatkin"); 2155 MODULE_ALIAS("platform:omap-sham"); 2156