1 /* 2 * Support for OMAP DES and Triple DES HW acceleration. 3 * 4 * Copyright (c) 2013 Texas Instruments Incorporated 5 * Author: Joel Fernandes <joelf@ti.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as published 9 * by the Free Software Foundation. 10 * 11 */ 12 13 #define pr_fmt(fmt) "%s: " fmt, __func__ 14 15 #ifdef DEBUG 16 #define prn(num) printk(#num "=%d\n", num) 17 #define prx(num) printk(#num "=%x\n", num) 18 #else 19 #define prn(num) do { } while (0) 20 #define prx(num) do { } while (0) 21 #endif 22 23 #include <linux/err.h> 24 #include <linux/module.h> 25 #include <linux/init.h> 26 #include <linux/errno.h> 27 #include <linux/kernel.h> 28 #include <linux/platform_device.h> 29 #include <linux/scatterlist.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/dmaengine.h> 32 #include <linux/omap-dma.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/of.h> 35 #include <linux/of_device.h> 36 #include <linux/of_address.h> 37 #include <linux/io.h> 38 #include <linux/crypto.h> 39 #include <linux/interrupt.h> 40 #include <crypto/scatterwalk.h> 41 #include <crypto/des.h> 42 43 #define DST_MAXBURST 2 44 45 #define DES_BLOCK_WORDS (DES_BLOCK_SIZE >> 2) 46 47 #define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset) 48 49 #define DES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \ 50 ((x ^ 0x01) * 0x04)) 51 52 #define DES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04)) 53 54 #define DES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs) 55 #define DES_REG_CTRL_CBC BIT(4) 56 #define DES_REG_CTRL_TDES BIT(3) 57 #define DES_REG_CTRL_DIRECTION BIT(2) 58 #define DES_REG_CTRL_INPUT_READY BIT(1) 59 #define DES_REG_CTRL_OUTPUT_READY BIT(0) 60 61 #define DES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04)) 62 63 #define DES_REG_REV(dd) ((dd)->pdata->rev_ofs) 64 65 #define DES_REG_MASK(dd) ((dd)->pdata->mask_ofs) 66 67 #define DES_REG_LENGTH_N(x) (0x24 + ((x) * 0x04)) 68 69 #define DES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs) 70 #define DES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs) 71 #define DES_REG_IRQ_DATA_IN BIT(1) 72 #define DES_REG_IRQ_DATA_OUT BIT(2) 73 74 #define FLAGS_MODE_MASK 0x000f 75 #define FLAGS_ENCRYPT BIT(0) 76 #define FLAGS_CBC BIT(1) 77 #define FLAGS_INIT BIT(4) 78 #define FLAGS_BUSY BIT(6) 79 80 struct omap_des_ctx { 81 struct omap_des_dev *dd; 82 83 int keylen; 84 u32 key[(3 * DES_KEY_SIZE) / sizeof(u32)]; 85 unsigned long flags; 86 }; 87 88 struct omap_des_reqctx { 89 unsigned long mode; 90 }; 91 92 #define OMAP_DES_QUEUE_LENGTH 1 93 #define OMAP_DES_CACHE_SIZE 0 94 95 struct omap_des_algs_info { 96 struct crypto_alg *algs_list; 97 unsigned int size; 98 unsigned int registered; 99 }; 100 101 struct omap_des_pdata { 102 struct omap_des_algs_info *algs_info; 103 unsigned int algs_info_size; 104 105 void (*trigger)(struct omap_des_dev *dd, int length); 106 107 u32 key_ofs; 108 u32 iv_ofs; 109 u32 ctrl_ofs; 110 u32 data_ofs; 111 u32 rev_ofs; 112 u32 mask_ofs; 113 u32 irq_enable_ofs; 114 u32 irq_status_ofs; 115 116 u32 dma_enable_in; 117 u32 dma_enable_out; 118 u32 dma_start; 119 120 u32 major_mask; 121 u32 major_shift; 122 u32 minor_mask; 123 u32 minor_shift; 124 }; 125 126 struct omap_des_dev { 127 struct list_head list; 128 unsigned long phys_base; 129 void __iomem *io_base; 130 struct omap_des_ctx *ctx; 131 struct device *dev; 132 unsigned long flags; 133 int err; 134 135 /* spinlock used for queues */ 136 spinlock_t lock; 137 struct crypto_queue queue; 138 139 struct tasklet_struct done_task; 140 struct tasklet_struct queue_task; 141 142 struct ablkcipher_request *req; 143 /* 144 * total is used by PIO mode for book keeping so introduce 145 * variable total_save as need it to calc page_order 146 */ 147 size_t total; 148 size_t total_save; 149 150 struct scatterlist *in_sg; 151 struct scatterlist *out_sg; 152 153 /* Buffers for copying for unaligned cases */ 154 struct scatterlist in_sgl; 155 struct scatterlist out_sgl; 156 struct scatterlist *orig_out; 157 int sgs_copied; 158 159 struct scatter_walk in_walk; 160 struct scatter_walk out_walk; 161 int dma_in; 162 struct dma_chan *dma_lch_in; 163 int dma_out; 164 struct dma_chan *dma_lch_out; 165 int in_sg_len; 166 int out_sg_len; 167 int pio_only; 168 const struct omap_des_pdata *pdata; 169 }; 170 171 /* keep registered devices data here */ 172 static LIST_HEAD(dev_list); 173 static DEFINE_SPINLOCK(list_lock); 174 175 #ifdef DEBUG 176 #define omap_des_read(dd, offset) \ 177 ({ \ 178 int _read_ret; \ 179 _read_ret = __raw_readl(dd->io_base + offset); \ 180 pr_err("omap_des_read(" #offset "=%#x)= %#x\n", \ 181 offset, _read_ret); \ 182 _read_ret; \ 183 }) 184 #else 185 static inline u32 omap_des_read(struct omap_des_dev *dd, u32 offset) 186 { 187 return __raw_readl(dd->io_base + offset); 188 } 189 #endif 190 191 #ifdef DEBUG 192 #define omap_des_write(dd, offset, value) \ 193 do { \ 194 pr_err("omap_des_write(" #offset "=%#x) value=%#x\n", \ 195 offset, value); \ 196 __raw_writel(value, dd->io_base + offset); \ 197 } while (0) 198 #else 199 static inline void omap_des_write(struct omap_des_dev *dd, u32 offset, 200 u32 value) 201 { 202 __raw_writel(value, dd->io_base + offset); 203 } 204 #endif 205 206 static inline void omap_des_write_mask(struct omap_des_dev *dd, u32 offset, 207 u32 value, u32 mask) 208 { 209 u32 val; 210 211 val = omap_des_read(dd, offset); 212 val &= ~mask; 213 val |= value; 214 omap_des_write(dd, offset, val); 215 } 216 217 static void omap_des_write_n(struct omap_des_dev *dd, u32 offset, 218 u32 *value, int count) 219 { 220 for (; count--; value++, offset += 4) 221 omap_des_write(dd, offset, *value); 222 } 223 224 static int omap_des_hw_init(struct omap_des_dev *dd) 225 { 226 int err; 227 228 /* 229 * clocks are enabled when request starts and disabled when finished. 230 * It may be long delays between requests. 231 * Device might go to off mode to save power. 232 */ 233 err = pm_runtime_get_sync(dd->dev); 234 if (err < 0) { 235 pm_runtime_put_noidle(dd->dev); 236 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err); 237 return err; 238 } 239 240 if (!(dd->flags & FLAGS_INIT)) { 241 dd->flags |= FLAGS_INIT; 242 dd->err = 0; 243 } 244 245 return 0; 246 } 247 248 static int omap_des_write_ctrl(struct omap_des_dev *dd) 249 { 250 unsigned int key32; 251 int i, err; 252 u32 val = 0, mask = 0; 253 254 err = omap_des_hw_init(dd); 255 if (err) 256 return err; 257 258 key32 = dd->ctx->keylen / sizeof(u32); 259 260 /* it seems a key should always be set even if it has not changed */ 261 for (i = 0; i < key32; i++) { 262 omap_des_write(dd, DES_REG_KEY(dd, i), 263 __le32_to_cpu(dd->ctx->key[i])); 264 } 265 266 if ((dd->flags & FLAGS_CBC) && dd->req->info) 267 omap_des_write_n(dd, DES_REG_IV(dd, 0), dd->req->info, 2); 268 269 if (dd->flags & FLAGS_CBC) 270 val |= DES_REG_CTRL_CBC; 271 if (dd->flags & FLAGS_ENCRYPT) 272 val |= DES_REG_CTRL_DIRECTION; 273 if (key32 == 6) 274 val |= DES_REG_CTRL_TDES; 275 276 mask |= DES_REG_CTRL_CBC | DES_REG_CTRL_DIRECTION | DES_REG_CTRL_TDES; 277 278 omap_des_write_mask(dd, DES_REG_CTRL(dd), val, mask); 279 280 return 0; 281 } 282 283 static void omap_des_dma_trigger_omap4(struct omap_des_dev *dd, int length) 284 { 285 u32 mask, val; 286 287 omap_des_write(dd, DES_REG_LENGTH_N(0), length); 288 289 val = dd->pdata->dma_start; 290 291 if (dd->dma_lch_out != NULL) 292 val |= dd->pdata->dma_enable_out; 293 if (dd->dma_lch_in != NULL) 294 val |= dd->pdata->dma_enable_in; 295 296 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | 297 dd->pdata->dma_start; 298 299 omap_des_write_mask(dd, DES_REG_MASK(dd), val, mask); 300 } 301 302 static void omap_des_dma_stop(struct omap_des_dev *dd) 303 { 304 u32 mask; 305 306 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | 307 dd->pdata->dma_start; 308 309 omap_des_write_mask(dd, DES_REG_MASK(dd), 0, mask); 310 } 311 312 static struct omap_des_dev *omap_des_find_dev(struct omap_des_ctx *ctx) 313 { 314 struct omap_des_dev *dd = NULL, *tmp; 315 316 spin_lock_bh(&list_lock); 317 if (!ctx->dd) { 318 list_for_each_entry(tmp, &dev_list, list) { 319 /* FIXME: take fist available des core */ 320 dd = tmp; 321 break; 322 } 323 ctx->dd = dd; 324 } else { 325 /* already found before */ 326 dd = ctx->dd; 327 } 328 spin_unlock_bh(&list_lock); 329 330 return dd; 331 } 332 333 static void omap_des_dma_out_callback(void *data) 334 { 335 struct omap_des_dev *dd = data; 336 337 /* dma_lch_out - completed */ 338 tasklet_schedule(&dd->done_task); 339 } 340 341 static int omap_des_dma_init(struct omap_des_dev *dd) 342 { 343 int err = -ENOMEM; 344 dma_cap_mask_t mask; 345 346 dd->dma_lch_out = NULL; 347 dd->dma_lch_in = NULL; 348 349 dma_cap_zero(mask); 350 dma_cap_set(DMA_SLAVE, mask); 351 352 dd->dma_lch_in = dma_request_slave_channel_compat(mask, 353 omap_dma_filter_fn, 354 &dd->dma_in, 355 dd->dev, "rx"); 356 if (!dd->dma_lch_in) { 357 dev_err(dd->dev, "Unable to request in DMA channel\n"); 358 goto err_dma_in; 359 } 360 361 dd->dma_lch_out = dma_request_slave_channel_compat(mask, 362 omap_dma_filter_fn, 363 &dd->dma_out, 364 dd->dev, "tx"); 365 if (!dd->dma_lch_out) { 366 dev_err(dd->dev, "Unable to request out DMA channel\n"); 367 goto err_dma_out; 368 } 369 370 return 0; 371 372 err_dma_out: 373 dma_release_channel(dd->dma_lch_in); 374 err_dma_in: 375 if (err) 376 pr_err("error: %d\n", err); 377 return err; 378 } 379 380 static void omap_des_dma_cleanup(struct omap_des_dev *dd) 381 { 382 dma_release_channel(dd->dma_lch_out); 383 dma_release_channel(dd->dma_lch_in); 384 } 385 386 static void sg_copy_buf(void *buf, struct scatterlist *sg, 387 unsigned int start, unsigned int nbytes, int out) 388 { 389 struct scatter_walk walk; 390 391 if (!nbytes) 392 return; 393 394 scatterwalk_start(&walk, sg); 395 scatterwalk_advance(&walk, start); 396 scatterwalk_copychunks(buf, &walk, nbytes, out); 397 scatterwalk_done(&walk, out, 0); 398 } 399 400 static int omap_des_crypt_dma(struct crypto_tfm *tfm, 401 struct scatterlist *in_sg, struct scatterlist *out_sg, 402 int in_sg_len, int out_sg_len) 403 { 404 struct omap_des_ctx *ctx = crypto_tfm_ctx(tfm); 405 struct omap_des_dev *dd = ctx->dd; 406 struct dma_async_tx_descriptor *tx_in, *tx_out; 407 struct dma_slave_config cfg; 408 int ret; 409 410 if (dd->pio_only) { 411 scatterwalk_start(&dd->in_walk, dd->in_sg); 412 scatterwalk_start(&dd->out_walk, dd->out_sg); 413 414 /* Enable DATAIN interrupt and let it take 415 care of the rest */ 416 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2); 417 return 0; 418 } 419 420 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE); 421 422 memset(&cfg, 0, sizeof(cfg)); 423 424 cfg.src_addr = dd->phys_base + DES_REG_DATA_N(dd, 0); 425 cfg.dst_addr = dd->phys_base + DES_REG_DATA_N(dd, 0); 426 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 427 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 428 cfg.src_maxburst = DST_MAXBURST; 429 cfg.dst_maxburst = DST_MAXBURST; 430 431 /* IN */ 432 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg); 433 if (ret) { 434 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n", 435 ret); 436 return ret; 437 } 438 439 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len, 440 DMA_MEM_TO_DEV, 441 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 442 if (!tx_in) { 443 dev_err(dd->dev, "IN prep_slave_sg() failed\n"); 444 return -EINVAL; 445 } 446 447 /* No callback necessary */ 448 tx_in->callback_param = dd; 449 450 /* OUT */ 451 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg); 452 if (ret) { 453 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n", 454 ret); 455 return ret; 456 } 457 458 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len, 459 DMA_DEV_TO_MEM, 460 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 461 if (!tx_out) { 462 dev_err(dd->dev, "OUT prep_slave_sg() failed\n"); 463 return -EINVAL; 464 } 465 466 tx_out->callback = omap_des_dma_out_callback; 467 tx_out->callback_param = dd; 468 469 dmaengine_submit(tx_in); 470 dmaengine_submit(tx_out); 471 472 dma_async_issue_pending(dd->dma_lch_in); 473 dma_async_issue_pending(dd->dma_lch_out); 474 475 /* start DMA */ 476 dd->pdata->trigger(dd, dd->total); 477 478 return 0; 479 } 480 481 static int omap_des_crypt_dma_start(struct omap_des_dev *dd) 482 { 483 struct crypto_tfm *tfm = crypto_ablkcipher_tfm( 484 crypto_ablkcipher_reqtfm(dd->req)); 485 int err; 486 487 pr_debug("total: %d\n", dd->total); 488 489 if (!dd->pio_only) { 490 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len, 491 DMA_TO_DEVICE); 492 if (!err) { 493 dev_err(dd->dev, "dma_map_sg() error\n"); 494 return -EINVAL; 495 } 496 497 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len, 498 DMA_FROM_DEVICE); 499 if (!err) { 500 dev_err(dd->dev, "dma_map_sg() error\n"); 501 return -EINVAL; 502 } 503 } 504 505 err = omap_des_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len, 506 dd->out_sg_len); 507 if (err && !dd->pio_only) { 508 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 509 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, 510 DMA_FROM_DEVICE); 511 } 512 513 return err; 514 } 515 516 static void omap_des_finish_req(struct omap_des_dev *dd, int err) 517 { 518 struct ablkcipher_request *req = dd->req; 519 520 pr_debug("err: %d\n", err); 521 522 pm_runtime_put(dd->dev); 523 dd->flags &= ~FLAGS_BUSY; 524 525 req->base.complete(&req->base, err); 526 } 527 528 static int omap_des_crypt_dma_stop(struct omap_des_dev *dd) 529 { 530 int err = 0; 531 532 pr_debug("total: %d\n", dd->total); 533 534 omap_des_dma_stop(dd); 535 536 dmaengine_terminate_all(dd->dma_lch_in); 537 dmaengine_terminate_all(dd->dma_lch_out); 538 539 return err; 540 } 541 542 static int omap_des_copy_needed(struct scatterlist *sg) 543 { 544 while (sg) { 545 if (!IS_ALIGNED(sg->offset, 4)) 546 return -1; 547 if (!IS_ALIGNED(sg->length, DES_BLOCK_SIZE)) 548 return -1; 549 sg = sg_next(sg); 550 } 551 return 0; 552 } 553 554 static int omap_des_copy_sgs(struct omap_des_dev *dd) 555 { 556 void *buf_in, *buf_out; 557 int pages; 558 559 pages = dd->total >> PAGE_SHIFT; 560 561 if (dd->total & (PAGE_SIZE-1)) 562 pages++; 563 564 BUG_ON(!pages); 565 566 buf_in = (void *)__get_free_pages(GFP_ATOMIC, pages); 567 buf_out = (void *)__get_free_pages(GFP_ATOMIC, pages); 568 569 if (!buf_in || !buf_out) { 570 pr_err("Couldn't allocated pages for unaligned cases.\n"); 571 return -1; 572 } 573 574 dd->orig_out = dd->out_sg; 575 576 sg_copy_buf(buf_in, dd->in_sg, 0, dd->total, 0); 577 578 sg_init_table(&dd->in_sgl, 1); 579 sg_set_buf(&dd->in_sgl, buf_in, dd->total); 580 dd->in_sg = &dd->in_sgl; 581 582 sg_init_table(&dd->out_sgl, 1); 583 sg_set_buf(&dd->out_sgl, buf_out, dd->total); 584 dd->out_sg = &dd->out_sgl; 585 586 return 0; 587 } 588 589 static int omap_des_handle_queue(struct omap_des_dev *dd, 590 struct ablkcipher_request *req) 591 { 592 struct crypto_async_request *async_req, *backlog; 593 struct omap_des_ctx *ctx; 594 struct omap_des_reqctx *rctx; 595 unsigned long flags; 596 int err, ret = 0; 597 598 spin_lock_irqsave(&dd->lock, flags); 599 if (req) 600 ret = ablkcipher_enqueue_request(&dd->queue, req); 601 if (dd->flags & FLAGS_BUSY) { 602 spin_unlock_irqrestore(&dd->lock, flags); 603 return ret; 604 } 605 backlog = crypto_get_backlog(&dd->queue); 606 async_req = crypto_dequeue_request(&dd->queue); 607 if (async_req) 608 dd->flags |= FLAGS_BUSY; 609 spin_unlock_irqrestore(&dd->lock, flags); 610 611 if (!async_req) 612 return ret; 613 614 if (backlog) 615 backlog->complete(backlog, -EINPROGRESS); 616 617 req = ablkcipher_request_cast(async_req); 618 619 /* assign new request to device */ 620 dd->req = req; 621 dd->total = req->nbytes; 622 dd->total_save = req->nbytes; 623 dd->in_sg = req->src; 624 dd->out_sg = req->dst; 625 626 if (omap_des_copy_needed(dd->in_sg) || 627 omap_des_copy_needed(dd->out_sg)) { 628 if (omap_des_copy_sgs(dd)) 629 pr_err("Failed to copy SGs for unaligned cases\n"); 630 dd->sgs_copied = 1; 631 } else { 632 dd->sgs_copied = 0; 633 } 634 635 dd->in_sg_len = scatterwalk_bytes_sglen(dd->in_sg, dd->total); 636 dd->out_sg_len = scatterwalk_bytes_sglen(dd->out_sg, dd->total); 637 BUG_ON(dd->in_sg_len < 0 || dd->out_sg_len < 0); 638 639 rctx = ablkcipher_request_ctx(req); 640 ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req)); 641 rctx->mode &= FLAGS_MODE_MASK; 642 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode; 643 644 dd->ctx = ctx; 645 ctx->dd = dd; 646 647 err = omap_des_write_ctrl(dd); 648 if (!err) 649 err = omap_des_crypt_dma_start(dd); 650 if (err) { 651 /* des_task will not finish it, so do it here */ 652 omap_des_finish_req(dd, err); 653 tasklet_schedule(&dd->queue_task); 654 } 655 656 return ret; /* return ret, which is enqueue return value */ 657 } 658 659 static void omap_des_done_task(unsigned long data) 660 { 661 struct omap_des_dev *dd = (struct omap_des_dev *)data; 662 void *buf_in, *buf_out; 663 int pages; 664 665 pr_debug("enter done_task\n"); 666 667 if (!dd->pio_only) { 668 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len, 669 DMA_FROM_DEVICE); 670 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 671 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, 672 DMA_FROM_DEVICE); 673 omap_des_crypt_dma_stop(dd); 674 } 675 676 if (dd->sgs_copied) { 677 buf_in = sg_virt(&dd->in_sgl); 678 buf_out = sg_virt(&dd->out_sgl); 679 680 sg_copy_buf(buf_out, dd->orig_out, 0, dd->total_save, 1); 681 682 pages = get_order(dd->total_save); 683 free_pages((unsigned long)buf_in, pages); 684 free_pages((unsigned long)buf_out, pages); 685 } 686 687 omap_des_finish_req(dd, 0); 688 omap_des_handle_queue(dd, NULL); 689 690 pr_debug("exit\n"); 691 } 692 693 static void omap_des_queue_task(unsigned long data) 694 { 695 struct omap_des_dev *dd = (struct omap_des_dev *)data; 696 697 omap_des_handle_queue(dd, NULL); 698 } 699 700 static int omap_des_crypt(struct ablkcipher_request *req, unsigned long mode) 701 { 702 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx( 703 crypto_ablkcipher_reqtfm(req)); 704 struct omap_des_reqctx *rctx = ablkcipher_request_ctx(req); 705 struct omap_des_dev *dd; 706 707 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes, 708 !!(mode & FLAGS_ENCRYPT), 709 !!(mode & FLAGS_CBC)); 710 711 if (!IS_ALIGNED(req->nbytes, DES_BLOCK_SIZE)) { 712 pr_err("request size is not exact amount of DES blocks\n"); 713 return -EINVAL; 714 } 715 716 dd = omap_des_find_dev(ctx); 717 if (!dd) 718 return -ENODEV; 719 720 rctx->mode = mode; 721 722 return omap_des_handle_queue(dd, req); 723 } 724 725 /* ********************** ALG API ************************************ */ 726 727 static int omap_des_setkey(struct crypto_ablkcipher *tfm, const u8 *key, 728 unsigned int keylen) 729 { 730 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(tfm); 731 732 if (keylen != DES_KEY_SIZE && keylen != (3*DES_KEY_SIZE)) 733 return -EINVAL; 734 735 pr_debug("enter, keylen: %d\n", keylen); 736 737 memcpy(ctx->key, key, keylen); 738 ctx->keylen = keylen; 739 740 return 0; 741 } 742 743 static int omap_des_ecb_encrypt(struct ablkcipher_request *req) 744 { 745 return omap_des_crypt(req, FLAGS_ENCRYPT); 746 } 747 748 static int omap_des_ecb_decrypt(struct ablkcipher_request *req) 749 { 750 return omap_des_crypt(req, 0); 751 } 752 753 static int omap_des_cbc_encrypt(struct ablkcipher_request *req) 754 { 755 return omap_des_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC); 756 } 757 758 static int omap_des_cbc_decrypt(struct ablkcipher_request *req) 759 { 760 return omap_des_crypt(req, FLAGS_CBC); 761 } 762 763 static int omap_des_cra_init(struct crypto_tfm *tfm) 764 { 765 pr_debug("enter\n"); 766 767 tfm->crt_ablkcipher.reqsize = sizeof(struct omap_des_reqctx); 768 769 return 0; 770 } 771 772 static void omap_des_cra_exit(struct crypto_tfm *tfm) 773 { 774 pr_debug("enter\n"); 775 } 776 777 /* ********************** ALGS ************************************ */ 778 779 static struct crypto_alg algs_ecb_cbc[] = { 780 { 781 .cra_name = "ecb(des)", 782 .cra_driver_name = "ecb-des-omap", 783 .cra_priority = 100, 784 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 785 CRYPTO_ALG_KERN_DRIVER_ONLY | 786 CRYPTO_ALG_ASYNC, 787 .cra_blocksize = DES_BLOCK_SIZE, 788 .cra_ctxsize = sizeof(struct omap_des_ctx), 789 .cra_alignmask = 0, 790 .cra_type = &crypto_ablkcipher_type, 791 .cra_module = THIS_MODULE, 792 .cra_init = omap_des_cra_init, 793 .cra_exit = omap_des_cra_exit, 794 .cra_u.ablkcipher = { 795 .min_keysize = DES_KEY_SIZE, 796 .max_keysize = DES_KEY_SIZE, 797 .setkey = omap_des_setkey, 798 .encrypt = omap_des_ecb_encrypt, 799 .decrypt = omap_des_ecb_decrypt, 800 } 801 }, 802 { 803 .cra_name = "cbc(des)", 804 .cra_driver_name = "cbc-des-omap", 805 .cra_priority = 100, 806 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 807 CRYPTO_ALG_KERN_DRIVER_ONLY | 808 CRYPTO_ALG_ASYNC, 809 .cra_blocksize = DES_BLOCK_SIZE, 810 .cra_ctxsize = sizeof(struct omap_des_ctx), 811 .cra_alignmask = 0, 812 .cra_type = &crypto_ablkcipher_type, 813 .cra_module = THIS_MODULE, 814 .cra_init = omap_des_cra_init, 815 .cra_exit = omap_des_cra_exit, 816 .cra_u.ablkcipher = { 817 .min_keysize = DES_KEY_SIZE, 818 .max_keysize = DES_KEY_SIZE, 819 .ivsize = DES_BLOCK_SIZE, 820 .setkey = omap_des_setkey, 821 .encrypt = omap_des_cbc_encrypt, 822 .decrypt = omap_des_cbc_decrypt, 823 } 824 }, 825 { 826 .cra_name = "ecb(des3_ede)", 827 .cra_driver_name = "ecb-des3-omap", 828 .cra_priority = 100, 829 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 830 CRYPTO_ALG_KERN_DRIVER_ONLY | 831 CRYPTO_ALG_ASYNC, 832 .cra_blocksize = DES_BLOCK_SIZE, 833 .cra_ctxsize = sizeof(struct omap_des_ctx), 834 .cra_alignmask = 0, 835 .cra_type = &crypto_ablkcipher_type, 836 .cra_module = THIS_MODULE, 837 .cra_init = omap_des_cra_init, 838 .cra_exit = omap_des_cra_exit, 839 .cra_u.ablkcipher = { 840 .min_keysize = 3*DES_KEY_SIZE, 841 .max_keysize = 3*DES_KEY_SIZE, 842 .setkey = omap_des_setkey, 843 .encrypt = omap_des_ecb_encrypt, 844 .decrypt = omap_des_ecb_decrypt, 845 } 846 }, 847 { 848 .cra_name = "cbc(des3_ede)", 849 .cra_driver_name = "cbc-des3-omap", 850 .cra_priority = 100, 851 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 852 CRYPTO_ALG_KERN_DRIVER_ONLY | 853 CRYPTO_ALG_ASYNC, 854 .cra_blocksize = DES_BLOCK_SIZE, 855 .cra_ctxsize = sizeof(struct omap_des_ctx), 856 .cra_alignmask = 0, 857 .cra_type = &crypto_ablkcipher_type, 858 .cra_module = THIS_MODULE, 859 .cra_init = omap_des_cra_init, 860 .cra_exit = omap_des_cra_exit, 861 .cra_u.ablkcipher = { 862 .min_keysize = 3*DES_KEY_SIZE, 863 .max_keysize = 3*DES_KEY_SIZE, 864 .ivsize = DES_BLOCK_SIZE, 865 .setkey = omap_des_setkey, 866 .encrypt = omap_des_cbc_encrypt, 867 .decrypt = omap_des_cbc_decrypt, 868 } 869 } 870 }; 871 872 static struct omap_des_algs_info omap_des_algs_info_ecb_cbc[] = { 873 { 874 .algs_list = algs_ecb_cbc, 875 .size = ARRAY_SIZE(algs_ecb_cbc), 876 }, 877 }; 878 879 #ifdef CONFIG_OF 880 static const struct omap_des_pdata omap_des_pdata_omap4 = { 881 .algs_info = omap_des_algs_info_ecb_cbc, 882 .algs_info_size = ARRAY_SIZE(omap_des_algs_info_ecb_cbc), 883 .trigger = omap_des_dma_trigger_omap4, 884 .key_ofs = 0x14, 885 .iv_ofs = 0x18, 886 .ctrl_ofs = 0x20, 887 .data_ofs = 0x28, 888 .rev_ofs = 0x30, 889 .mask_ofs = 0x34, 890 .irq_status_ofs = 0x3c, 891 .irq_enable_ofs = 0x40, 892 .dma_enable_in = BIT(5), 893 .dma_enable_out = BIT(6), 894 .major_mask = 0x0700, 895 .major_shift = 8, 896 .minor_mask = 0x003f, 897 .minor_shift = 0, 898 }; 899 900 static irqreturn_t omap_des_irq(int irq, void *dev_id) 901 { 902 struct omap_des_dev *dd = dev_id; 903 u32 status, i; 904 u32 *src, *dst; 905 906 status = omap_des_read(dd, DES_REG_IRQ_STATUS(dd)); 907 if (status & DES_REG_IRQ_DATA_IN) { 908 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0); 909 910 BUG_ON(!dd->in_sg); 911 912 BUG_ON(_calc_walked(in) > dd->in_sg->length); 913 914 src = sg_virt(dd->in_sg) + _calc_walked(in); 915 916 for (i = 0; i < DES_BLOCK_WORDS; i++) { 917 omap_des_write(dd, DES_REG_DATA_N(dd, i), *src); 918 919 scatterwalk_advance(&dd->in_walk, 4); 920 if (dd->in_sg->length == _calc_walked(in)) { 921 dd->in_sg = sg_next(dd->in_sg); 922 if (dd->in_sg) { 923 scatterwalk_start(&dd->in_walk, 924 dd->in_sg); 925 src = sg_virt(dd->in_sg) + 926 _calc_walked(in); 927 } 928 } else { 929 src++; 930 } 931 } 932 933 /* Clear IRQ status */ 934 status &= ~DES_REG_IRQ_DATA_IN; 935 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status); 936 937 /* Enable DATA_OUT interrupt */ 938 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x4); 939 940 } else if (status & DES_REG_IRQ_DATA_OUT) { 941 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0); 942 943 BUG_ON(!dd->out_sg); 944 945 BUG_ON(_calc_walked(out) > dd->out_sg->length); 946 947 dst = sg_virt(dd->out_sg) + _calc_walked(out); 948 949 for (i = 0; i < DES_BLOCK_WORDS; i++) { 950 *dst = omap_des_read(dd, DES_REG_DATA_N(dd, i)); 951 scatterwalk_advance(&dd->out_walk, 4); 952 if (dd->out_sg->length == _calc_walked(out)) { 953 dd->out_sg = sg_next(dd->out_sg); 954 if (dd->out_sg) { 955 scatterwalk_start(&dd->out_walk, 956 dd->out_sg); 957 dst = sg_virt(dd->out_sg) + 958 _calc_walked(out); 959 } 960 } else { 961 dst++; 962 } 963 } 964 965 BUG_ON(dd->total < DES_BLOCK_SIZE); 966 967 dd->total -= DES_BLOCK_SIZE; 968 969 /* Clear IRQ status */ 970 status &= ~DES_REG_IRQ_DATA_OUT; 971 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status); 972 973 if (!dd->total) 974 /* All bytes read! */ 975 tasklet_schedule(&dd->done_task); 976 else 977 /* Enable DATA_IN interrupt for next block */ 978 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2); 979 } 980 981 return IRQ_HANDLED; 982 } 983 984 static const struct of_device_id omap_des_of_match[] = { 985 { 986 .compatible = "ti,omap4-des", 987 .data = &omap_des_pdata_omap4, 988 }, 989 {}, 990 }; 991 MODULE_DEVICE_TABLE(of, omap_des_of_match); 992 993 static int omap_des_get_of(struct omap_des_dev *dd, 994 struct platform_device *pdev) 995 { 996 const struct of_device_id *match; 997 998 match = of_match_device(of_match_ptr(omap_des_of_match), &pdev->dev); 999 if (!match) { 1000 dev_err(&pdev->dev, "no compatible OF match\n"); 1001 return -EINVAL; 1002 } 1003 1004 dd->dma_out = -1; /* Dummy value that's unused */ 1005 dd->dma_in = -1; /* Dummy value that's unused */ 1006 dd->pdata = match->data; 1007 1008 return 0; 1009 } 1010 #else 1011 static int omap_des_get_of(struct omap_des_dev *dd, 1012 struct device *dev) 1013 { 1014 return -EINVAL; 1015 } 1016 #endif 1017 1018 static int omap_des_get_pdev(struct omap_des_dev *dd, 1019 struct platform_device *pdev) 1020 { 1021 struct device *dev = &pdev->dev; 1022 struct resource *r; 1023 int err = 0; 1024 1025 /* Get the DMA out channel */ 1026 r = platform_get_resource(pdev, IORESOURCE_DMA, 0); 1027 if (!r) { 1028 dev_err(dev, "no DMA out resource info\n"); 1029 err = -ENODEV; 1030 goto err; 1031 } 1032 dd->dma_out = r->start; 1033 1034 /* Get the DMA in channel */ 1035 r = platform_get_resource(pdev, IORESOURCE_DMA, 1); 1036 if (!r) { 1037 dev_err(dev, "no DMA in resource info\n"); 1038 err = -ENODEV; 1039 goto err; 1040 } 1041 dd->dma_in = r->start; 1042 1043 /* non-DT devices get pdata from pdev */ 1044 dd->pdata = pdev->dev.platform_data; 1045 1046 err: 1047 return err; 1048 } 1049 1050 static int omap_des_probe(struct platform_device *pdev) 1051 { 1052 struct device *dev = &pdev->dev; 1053 struct omap_des_dev *dd; 1054 struct crypto_alg *algp; 1055 struct resource *res; 1056 int err = -ENOMEM, i, j, irq = -1; 1057 u32 reg; 1058 1059 dd = devm_kzalloc(dev, sizeof(struct omap_des_dev), GFP_KERNEL); 1060 if (dd == NULL) { 1061 dev_err(dev, "unable to alloc data struct.\n"); 1062 goto err_data; 1063 } 1064 dd->dev = dev; 1065 platform_set_drvdata(pdev, dd); 1066 1067 spin_lock_init(&dd->lock); 1068 crypto_init_queue(&dd->queue, OMAP_DES_QUEUE_LENGTH); 1069 1070 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1071 if (!res) { 1072 dev_err(dev, "no MEM resource info\n"); 1073 goto err_res; 1074 } 1075 1076 err = (dev->of_node) ? omap_des_get_of(dd, pdev) : 1077 omap_des_get_pdev(dd, pdev); 1078 if (err) 1079 goto err_res; 1080 1081 dd->io_base = devm_ioremap_resource(dev, res); 1082 if (IS_ERR(dd->io_base)) { 1083 err = PTR_ERR(dd->io_base); 1084 goto err_res; 1085 } 1086 dd->phys_base = res->start; 1087 1088 pm_runtime_enable(dev); 1089 err = pm_runtime_get_sync(dev); 1090 if (err < 0) { 1091 pm_runtime_put_noidle(dev); 1092 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err); 1093 goto err_get; 1094 } 1095 1096 omap_des_dma_stop(dd); 1097 1098 reg = omap_des_read(dd, DES_REG_REV(dd)); 1099 1100 pm_runtime_put_sync(dev); 1101 1102 dev_info(dev, "OMAP DES hw accel rev: %u.%u\n", 1103 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift, 1104 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift); 1105 1106 tasklet_init(&dd->done_task, omap_des_done_task, (unsigned long)dd); 1107 tasklet_init(&dd->queue_task, omap_des_queue_task, (unsigned long)dd); 1108 1109 err = omap_des_dma_init(dd); 1110 if (err && DES_REG_IRQ_STATUS(dd) && DES_REG_IRQ_ENABLE(dd)) { 1111 dd->pio_only = 1; 1112 1113 irq = platform_get_irq(pdev, 0); 1114 if (irq < 0) { 1115 dev_err(dev, "can't get IRQ resource\n"); 1116 goto err_irq; 1117 } 1118 1119 err = devm_request_irq(dev, irq, omap_des_irq, 0, 1120 dev_name(dev), dd); 1121 if (err) { 1122 dev_err(dev, "Unable to grab omap-des IRQ\n"); 1123 goto err_irq; 1124 } 1125 } 1126 1127 1128 INIT_LIST_HEAD(&dd->list); 1129 spin_lock(&list_lock); 1130 list_add_tail(&dd->list, &dev_list); 1131 spin_unlock(&list_lock); 1132 1133 for (i = 0; i < dd->pdata->algs_info_size; i++) { 1134 for (j = 0; j < dd->pdata->algs_info[i].size; j++) { 1135 algp = &dd->pdata->algs_info[i].algs_list[j]; 1136 1137 pr_debug("reg alg: %s\n", algp->cra_name); 1138 INIT_LIST_HEAD(&algp->cra_list); 1139 1140 err = crypto_register_alg(algp); 1141 if (err) 1142 goto err_algs; 1143 1144 dd->pdata->algs_info[i].registered++; 1145 } 1146 } 1147 1148 return 0; 1149 err_algs: 1150 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1151 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1152 crypto_unregister_alg( 1153 &dd->pdata->algs_info[i].algs_list[j]); 1154 if (!dd->pio_only) 1155 omap_des_dma_cleanup(dd); 1156 err_irq: 1157 tasklet_kill(&dd->done_task); 1158 tasklet_kill(&dd->queue_task); 1159 err_get: 1160 pm_runtime_disable(dev); 1161 err_res: 1162 dd = NULL; 1163 err_data: 1164 dev_err(dev, "initialization failed.\n"); 1165 return err; 1166 } 1167 1168 static int omap_des_remove(struct platform_device *pdev) 1169 { 1170 struct omap_des_dev *dd = platform_get_drvdata(pdev); 1171 int i, j; 1172 1173 if (!dd) 1174 return -ENODEV; 1175 1176 spin_lock(&list_lock); 1177 list_del(&dd->list); 1178 spin_unlock(&list_lock); 1179 1180 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1181 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1182 crypto_unregister_alg( 1183 &dd->pdata->algs_info[i].algs_list[j]); 1184 1185 tasklet_kill(&dd->done_task); 1186 tasklet_kill(&dd->queue_task); 1187 omap_des_dma_cleanup(dd); 1188 pm_runtime_disable(dd->dev); 1189 dd = NULL; 1190 1191 return 0; 1192 } 1193 1194 #ifdef CONFIG_PM_SLEEP 1195 static int omap_des_suspend(struct device *dev) 1196 { 1197 pm_runtime_put_sync(dev); 1198 return 0; 1199 } 1200 1201 static int omap_des_resume(struct device *dev) 1202 { 1203 int err; 1204 1205 err = pm_runtime_get_sync(dev); 1206 if (err < 0) { 1207 pm_runtime_put_noidle(dev); 1208 dev_err(dev, "%s: failed to get_sync(%d)\n", __func__, err); 1209 return err; 1210 } 1211 return 0; 1212 } 1213 #endif 1214 1215 static SIMPLE_DEV_PM_OPS(omap_des_pm_ops, omap_des_suspend, omap_des_resume); 1216 1217 static struct platform_driver omap_des_driver = { 1218 .probe = omap_des_probe, 1219 .remove = omap_des_remove, 1220 .driver = { 1221 .name = "omap-des", 1222 .pm = &omap_des_pm_ops, 1223 .of_match_table = of_match_ptr(omap_des_of_match), 1224 }, 1225 }; 1226 1227 module_platform_driver(omap_des_driver); 1228 1229 MODULE_DESCRIPTION("OMAP DES hw acceleration support."); 1230 MODULE_LICENSE("GPL v2"); 1231 MODULE_AUTHOR("Joel Fernandes <joelf@ti.com>"); 1232