1 /* 2 * Support for OMAP DES and Triple DES HW acceleration. 3 * 4 * Copyright (c) 2013 Texas Instruments Incorporated 5 * Author: Joel Fernandes <joelf@ti.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as published 9 * by the Free Software Foundation. 10 * 11 */ 12 13 #define pr_fmt(fmt) "%s: " fmt, __func__ 14 15 #ifdef DEBUG 16 #define prn(num) printk(#num "=%d\n", num) 17 #define prx(num) printk(#num "=%x\n", num) 18 #else 19 #define prn(num) do { } while (0) 20 #define prx(num) do { } while (0) 21 #endif 22 23 #include <linux/err.h> 24 #include <linux/module.h> 25 #include <linux/init.h> 26 #include <linux/errno.h> 27 #include <linux/kernel.h> 28 #include <linux/platform_device.h> 29 #include <linux/scatterlist.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/dmaengine.h> 32 #include <linux/omap-dma.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/of.h> 35 #include <linux/of_device.h> 36 #include <linux/of_address.h> 37 #include <linux/io.h> 38 #include <linux/crypto.h> 39 #include <linux/interrupt.h> 40 #include <crypto/scatterwalk.h> 41 #include <crypto/des.h> 42 43 #define DST_MAXBURST 2 44 45 #define DES_BLOCK_WORDS (DES_BLOCK_SIZE >> 2) 46 47 #define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset) 48 49 #define DES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \ 50 ((x ^ 0x01) * 0x04)) 51 52 #define DES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04)) 53 54 #define DES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs) 55 #define DES_REG_CTRL_CBC BIT(4) 56 #define DES_REG_CTRL_TDES BIT(3) 57 #define DES_REG_CTRL_DIRECTION BIT(2) 58 #define DES_REG_CTRL_INPUT_READY BIT(1) 59 #define DES_REG_CTRL_OUTPUT_READY BIT(0) 60 61 #define DES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04)) 62 63 #define DES_REG_REV(dd) ((dd)->pdata->rev_ofs) 64 65 #define DES_REG_MASK(dd) ((dd)->pdata->mask_ofs) 66 67 #define DES_REG_LENGTH_N(x) (0x24 + ((x) * 0x04)) 68 69 #define DES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs) 70 #define DES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs) 71 #define DES_REG_IRQ_DATA_IN BIT(1) 72 #define DES_REG_IRQ_DATA_OUT BIT(2) 73 74 #define FLAGS_MODE_MASK 0x000f 75 #define FLAGS_ENCRYPT BIT(0) 76 #define FLAGS_CBC BIT(1) 77 #define FLAGS_INIT BIT(4) 78 #define FLAGS_BUSY BIT(6) 79 80 struct omap_des_ctx { 81 struct omap_des_dev *dd; 82 83 int keylen; 84 u32 key[(3 * DES_KEY_SIZE) / sizeof(u32)]; 85 unsigned long flags; 86 }; 87 88 struct omap_des_reqctx { 89 unsigned long mode; 90 }; 91 92 #define OMAP_DES_QUEUE_LENGTH 1 93 #define OMAP_DES_CACHE_SIZE 0 94 95 struct omap_des_algs_info { 96 struct crypto_alg *algs_list; 97 unsigned int size; 98 unsigned int registered; 99 }; 100 101 struct omap_des_pdata { 102 struct omap_des_algs_info *algs_info; 103 unsigned int algs_info_size; 104 105 void (*trigger)(struct omap_des_dev *dd, int length); 106 107 u32 key_ofs; 108 u32 iv_ofs; 109 u32 ctrl_ofs; 110 u32 data_ofs; 111 u32 rev_ofs; 112 u32 mask_ofs; 113 u32 irq_enable_ofs; 114 u32 irq_status_ofs; 115 116 u32 dma_enable_in; 117 u32 dma_enable_out; 118 u32 dma_start; 119 120 u32 major_mask; 121 u32 major_shift; 122 u32 minor_mask; 123 u32 minor_shift; 124 }; 125 126 struct omap_des_dev { 127 struct list_head list; 128 unsigned long phys_base; 129 void __iomem *io_base; 130 struct omap_des_ctx *ctx; 131 struct device *dev; 132 unsigned long flags; 133 int err; 134 135 /* spinlock used for queues */ 136 spinlock_t lock; 137 struct crypto_queue queue; 138 139 struct tasklet_struct done_task; 140 struct tasklet_struct queue_task; 141 142 struct ablkcipher_request *req; 143 /* 144 * total is used by PIO mode for book keeping so introduce 145 * variable total_save as need it to calc page_order 146 */ 147 size_t total; 148 size_t total_save; 149 150 struct scatterlist *in_sg; 151 struct scatterlist *out_sg; 152 153 /* Buffers for copying for unaligned cases */ 154 struct scatterlist in_sgl; 155 struct scatterlist out_sgl; 156 struct scatterlist *orig_out; 157 int sgs_copied; 158 159 struct scatter_walk in_walk; 160 struct scatter_walk out_walk; 161 int dma_in; 162 struct dma_chan *dma_lch_in; 163 int dma_out; 164 struct dma_chan *dma_lch_out; 165 int in_sg_len; 166 int out_sg_len; 167 int pio_only; 168 const struct omap_des_pdata *pdata; 169 }; 170 171 /* keep registered devices data here */ 172 static LIST_HEAD(dev_list); 173 static DEFINE_SPINLOCK(list_lock); 174 175 #ifdef DEBUG 176 #define omap_des_read(dd, offset) \ 177 ({ \ 178 int _read_ret; \ 179 _read_ret = __raw_readl(dd->io_base + offset); \ 180 pr_err("omap_des_read(" #offset "=%#x)= %#x\n", \ 181 offset, _read_ret); \ 182 _read_ret; \ 183 }) 184 #else 185 static inline u32 omap_des_read(struct omap_des_dev *dd, u32 offset) 186 { 187 return __raw_readl(dd->io_base + offset); 188 } 189 #endif 190 191 #ifdef DEBUG 192 #define omap_des_write(dd, offset, value) \ 193 do { \ 194 pr_err("omap_des_write(" #offset "=%#x) value=%#x\n", \ 195 offset, value); \ 196 __raw_writel(value, dd->io_base + offset); \ 197 } while (0) 198 #else 199 static inline void omap_des_write(struct omap_des_dev *dd, u32 offset, 200 u32 value) 201 { 202 __raw_writel(value, dd->io_base + offset); 203 } 204 #endif 205 206 static inline void omap_des_write_mask(struct omap_des_dev *dd, u32 offset, 207 u32 value, u32 mask) 208 { 209 u32 val; 210 211 val = omap_des_read(dd, offset); 212 val &= ~mask; 213 val |= value; 214 omap_des_write(dd, offset, val); 215 } 216 217 static void omap_des_write_n(struct omap_des_dev *dd, u32 offset, 218 u32 *value, int count) 219 { 220 for (; count--; value++, offset += 4) 221 omap_des_write(dd, offset, *value); 222 } 223 224 static int omap_des_hw_init(struct omap_des_dev *dd) 225 { 226 int err; 227 228 /* 229 * clocks are enabled when request starts and disabled when finished. 230 * It may be long delays between requests. 231 * Device might go to off mode to save power. 232 */ 233 err = pm_runtime_get_sync(dd->dev); 234 if (err < 0) { 235 pm_runtime_put_noidle(dd->dev); 236 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err); 237 return err; 238 } 239 240 if (!(dd->flags & FLAGS_INIT)) { 241 dd->flags |= FLAGS_INIT; 242 dd->err = 0; 243 } 244 245 return 0; 246 } 247 248 static int omap_des_write_ctrl(struct omap_des_dev *dd) 249 { 250 unsigned int key32; 251 int i, err; 252 u32 val = 0, mask = 0; 253 254 err = omap_des_hw_init(dd); 255 if (err) 256 return err; 257 258 key32 = dd->ctx->keylen / sizeof(u32); 259 260 /* it seems a key should always be set even if it has not changed */ 261 for (i = 0; i < key32; i++) { 262 omap_des_write(dd, DES_REG_KEY(dd, i), 263 __le32_to_cpu(dd->ctx->key[i])); 264 } 265 266 if ((dd->flags & FLAGS_CBC) && dd->req->info) 267 omap_des_write_n(dd, DES_REG_IV(dd, 0), dd->req->info, 2); 268 269 if (dd->flags & FLAGS_CBC) 270 val |= DES_REG_CTRL_CBC; 271 if (dd->flags & FLAGS_ENCRYPT) 272 val |= DES_REG_CTRL_DIRECTION; 273 if (key32 == 6) 274 val |= DES_REG_CTRL_TDES; 275 276 mask |= DES_REG_CTRL_CBC | DES_REG_CTRL_DIRECTION | DES_REG_CTRL_TDES; 277 278 omap_des_write_mask(dd, DES_REG_CTRL(dd), val, mask); 279 280 return 0; 281 } 282 283 static void omap_des_dma_trigger_omap4(struct omap_des_dev *dd, int length) 284 { 285 u32 mask, val; 286 287 omap_des_write(dd, DES_REG_LENGTH_N(0), length); 288 289 val = dd->pdata->dma_start; 290 291 if (dd->dma_lch_out != NULL) 292 val |= dd->pdata->dma_enable_out; 293 if (dd->dma_lch_in != NULL) 294 val |= dd->pdata->dma_enable_in; 295 296 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | 297 dd->pdata->dma_start; 298 299 omap_des_write_mask(dd, DES_REG_MASK(dd), val, mask); 300 } 301 302 static void omap_des_dma_stop(struct omap_des_dev *dd) 303 { 304 u32 mask; 305 306 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | 307 dd->pdata->dma_start; 308 309 omap_des_write_mask(dd, DES_REG_MASK(dd), 0, mask); 310 } 311 312 static struct omap_des_dev *omap_des_find_dev(struct omap_des_ctx *ctx) 313 { 314 struct omap_des_dev *dd = NULL, *tmp; 315 316 spin_lock_bh(&list_lock); 317 if (!ctx->dd) { 318 list_for_each_entry(tmp, &dev_list, list) { 319 /* FIXME: take fist available des core */ 320 dd = tmp; 321 break; 322 } 323 ctx->dd = dd; 324 } else { 325 /* already found before */ 326 dd = ctx->dd; 327 } 328 spin_unlock_bh(&list_lock); 329 330 return dd; 331 } 332 333 static void omap_des_dma_out_callback(void *data) 334 { 335 struct omap_des_dev *dd = data; 336 337 /* dma_lch_out - completed */ 338 tasklet_schedule(&dd->done_task); 339 } 340 341 static int omap_des_dma_init(struct omap_des_dev *dd) 342 { 343 int err = -ENOMEM; 344 dma_cap_mask_t mask; 345 346 dd->dma_lch_out = NULL; 347 dd->dma_lch_in = NULL; 348 349 dma_cap_zero(mask); 350 dma_cap_set(DMA_SLAVE, mask); 351 352 dd->dma_lch_in = dma_request_slave_channel_compat(mask, 353 omap_dma_filter_fn, 354 &dd->dma_in, 355 dd->dev, "rx"); 356 if (!dd->dma_lch_in) { 357 dev_err(dd->dev, "Unable to request in DMA channel\n"); 358 goto err_dma_in; 359 } 360 361 dd->dma_lch_out = dma_request_slave_channel_compat(mask, 362 omap_dma_filter_fn, 363 &dd->dma_out, 364 dd->dev, "tx"); 365 if (!dd->dma_lch_out) { 366 dev_err(dd->dev, "Unable to request out DMA channel\n"); 367 goto err_dma_out; 368 } 369 370 return 0; 371 372 err_dma_out: 373 dma_release_channel(dd->dma_lch_in); 374 err_dma_in: 375 if (err) 376 pr_err("error: %d\n", err); 377 return err; 378 } 379 380 static void omap_des_dma_cleanup(struct omap_des_dev *dd) 381 { 382 dma_release_channel(dd->dma_lch_out); 383 dma_release_channel(dd->dma_lch_in); 384 } 385 386 static void sg_copy_buf(void *buf, struct scatterlist *sg, 387 unsigned int start, unsigned int nbytes, int out) 388 { 389 struct scatter_walk walk; 390 391 if (!nbytes) 392 return; 393 394 scatterwalk_start(&walk, sg); 395 scatterwalk_advance(&walk, start); 396 scatterwalk_copychunks(buf, &walk, nbytes, out); 397 scatterwalk_done(&walk, out, 0); 398 } 399 400 static int omap_des_crypt_dma(struct crypto_tfm *tfm, 401 struct scatterlist *in_sg, struct scatterlist *out_sg, 402 int in_sg_len, int out_sg_len) 403 { 404 struct omap_des_ctx *ctx = crypto_tfm_ctx(tfm); 405 struct omap_des_dev *dd = ctx->dd; 406 struct dma_async_tx_descriptor *tx_in, *tx_out; 407 struct dma_slave_config cfg; 408 int ret; 409 410 if (dd->pio_only) { 411 scatterwalk_start(&dd->in_walk, dd->in_sg); 412 scatterwalk_start(&dd->out_walk, dd->out_sg); 413 414 /* Enable DATAIN interrupt and let it take 415 care of the rest */ 416 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2); 417 return 0; 418 } 419 420 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE); 421 422 memset(&cfg, 0, sizeof(cfg)); 423 424 cfg.src_addr = dd->phys_base + DES_REG_DATA_N(dd, 0); 425 cfg.dst_addr = dd->phys_base + DES_REG_DATA_N(dd, 0); 426 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 427 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 428 cfg.src_maxburst = DST_MAXBURST; 429 cfg.dst_maxburst = DST_MAXBURST; 430 431 /* IN */ 432 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg); 433 if (ret) { 434 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n", 435 ret); 436 return ret; 437 } 438 439 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len, 440 DMA_MEM_TO_DEV, 441 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 442 if (!tx_in) { 443 dev_err(dd->dev, "IN prep_slave_sg() failed\n"); 444 return -EINVAL; 445 } 446 447 /* No callback necessary */ 448 tx_in->callback_param = dd; 449 450 /* OUT */ 451 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg); 452 if (ret) { 453 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n", 454 ret); 455 return ret; 456 } 457 458 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len, 459 DMA_DEV_TO_MEM, 460 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 461 if (!tx_out) { 462 dev_err(dd->dev, "OUT prep_slave_sg() failed\n"); 463 return -EINVAL; 464 } 465 466 tx_out->callback = omap_des_dma_out_callback; 467 tx_out->callback_param = dd; 468 469 dmaengine_submit(tx_in); 470 dmaengine_submit(tx_out); 471 472 dma_async_issue_pending(dd->dma_lch_in); 473 dma_async_issue_pending(dd->dma_lch_out); 474 475 /* start DMA */ 476 dd->pdata->trigger(dd, dd->total); 477 478 return 0; 479 } 480 481 static int omap_des_crypt_dma_start(struct omap_des_dev *dd) 482 { 483 struct crypto_tfm *tfm = crypto_ablkcipher_tfm( 484 crypto_ablkcipher_reqtfm(dd->req)); 485 int err; 486 487 pr_debug("total: %d\n", dd->total); 488 489 if (!dd->pio_only) { 490 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len, 491 DMA_TO_DEVICE); 492 if (!err) { 493 dev_err(dd->dev, "dma_map_sg() error\n"); 494 return -EINVAL; 495 } 496 497 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len, 498 DMA_FROM_DEVICE); 499 if (!err) { 500 dev_err(dd->dev, "dma_map_sg() error\n"); 501 return -EINVAL; 502 } 503 } 504 505 err = omap_des_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len, 506 dd->out_sg_len); 507 if (err && !dd->pio_only) { 508 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 509 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, 510 DMA_FROM_DEVICE); 511 } 512 513 return err; 514 } 515 516 static void omap_des_finish_req(struct omap_des_dev *dd, int err) 517 { 518 struct ablkcipher_request *req = dd->req; 519 520 pr_debug("err: %d\n", err); 521 522 pm_runtime_put(dd->dev); 523 dd->flags &= ~FLAGS_BUSY; 524 525 req->base.complete(&req->base, err); 526 } 527 528 static int omap_des_crypt_dma_stop(struct omap_des_dev *dd) 529 { 530 int err = 0; 531 532 pr_debug("total: %d\n", dd->total); 533 534 omap_des_dma_stop(dd); 535 536 dmaengine_terminate_all(dd->dma_lch_in); 537 dmaengine_terminate_all(dd->dma_lch_out); 538 539 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 540 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, DMA_FROM_DEVICE); 541 542 return err; 543 } 544 545 static int omap_des_copy_needed(struct scatterlist *sg) 546 { 547 while (sg) { 548 if (!IS_ALIGNED(sg->offset, 4)) 549 return -1; 550 if (!IS_ALIGNED(sg->length, DES_BLOCK_SIZE)) 551 return -1; 552 sg = sg_next(sg); 553 } 554 return 0; 555 } 556 557 static int omap_des_copy_sgs(struct omap_des_dev *dd) 558 { 559 void *buf_in, *buf_out; 560 int pages; 561 562 pages = dd->total >> PAGE_SHIFT; 563 564 if (dd->total & (PAGE_SIZE-1)) 565 pages++; 566 567 BUG_ON(!pages); 568 569 buf_in = (void *)__get_free_pages(GFP_ATOMIC, pages); 570 buf_out = (void *)__get_free_pages(GFP_ATOMIC, pages); 571 572 if (!buf_in || !buf_out) { 573 pr_err("Couldn't allocated pages for unaligned cases.\n"); 574 return -1; 575 } 576 577 dd->orig_out = dd->out_sg; 578 579 sg_copy_buf(buf_in, dd->in_sg, 0, dd->total, 0); 580 581 sg_init_table(&dd->in_sgl, 1); 582 sg_set_buf(&dd->in_sgl, buf_in, dd->total); 583 dd->in_sg = &dd->in_sgl; 584 585 sg_init_table(&dd->out_sgl, 1); 586 sg_set_buf(&dd->out_sgl, buf_out, dd->total); 587 dd->out_sg = &dd->out_sgl; 588 589 return 0; 590 } 591 592 static int omap_des_handle_queue(struct omap_des_dev *dd, 593 struct ablkcipher_request *req) 594 { 595 struct crypto_async_request *async_req, *backlog; 596 struct omap_des_ctx *ctx; 597 struct omap_des_reqctx *rctx; 598 unsigned long flags; 599 int err, ret = 0; 600 601 spin_lock_irqsave(&dd->lock, flags); 602 if (req) 603 ret = ablkcipher_enqueue_request(&dd->queue, req); 604 if (dd->flags & FLAGS_BUSY) { 605 spin_unlock_irqrestore(&dd->lock, flags); 606 return ret; 607 } 608 backlog = crypto_get_backlog(&dd->queue); 609 async_req = crypto_dequeue_request(&dd->queue); 610 if (async_req) 611 dd->flags |= FLAGS_BUSY; 612 spin_unlock_irqrestore(&dd->lock, flags); 613 614 if (!async_req) 615 return ret; 616 617 if (backlog) 618 backlog->complete(backlog, -EINPROGRESS); 619 620 req = ablkcipher_request_cast(async_req); 621 622 /* assign new request to device */ 623 dd->req = req; 624 dd->total = req->nbytes; 625 dd->total_save = req->nbytes; 626 dd->in_sg = req->src; 627 dd->out_sg = req->dst; 628 629 if (omap_des_copy_needed(dd->in_sg) || 630 omap_des_copy_needed(dd->out_sg)) { 631 if (omap_des_copy_sgs(dd)) 632 pr_err("Failed to copy SGs for unaligned cases\n"); 633 dd->sgs_copied = 1; 634 } else { 635 dd->sgs_copied = 0; 636 } 637 638 dd->in_sg_len = scatterwalk_bytes_sglen(dd->in_sg, dd->total); 639 dd->out_sg_len = scatterwalk_bytes_sglen(dd->out_sg, dd->total); 640 BUG_ON(dd->in_sg_len < 0 || dd->out_sg_len < 0); 641 642 rctx = ablkcipher_request_ctx(req); 643 ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req)); 644 rctx->mode &= FLAGS_MODE_MASK; 645 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode; 646 647 dd->ctx = ctx; 648 ctx->dd = dd; 649 650 err = omap_des_write_ctrl(dd); 651 if (!err) 652 err = omap_des_crypt_dma_start(dd); 653 if (err) { 654 /* des_task will not finish it, so do it here */ 655 omap_des_finish_req(dd, err); 656 tasklet_schedule(&dd->queue_task); 657 } 658 659 return ret; /* return ret, which is enqueue return value */ 660 } 661 662 static void omap_des_done_task(unsigned long data) 663 { 664 struct omap_des_dev *dd = (struct omap_des_dev *)data; 665 void *buf_in, *buf_out; 666 int pages; 667 668 pr_debug("enter done_task\n"); 669 670 if (!dd->pio_only) { 671 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len, 672 DMA_FROM_DEVICE); 673 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 674 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, 675 DMA_FROM_DEVICE); 676 omap_des_crypt_dma_stop(dd); 677 } 678 679 if (dd->sgs_copied) { 680 buf_in = sg_virt(&dd->in_sgl); 681 buf_out = sg_virt(&dd->out_sgl); 682 683 sg_copy_buf(buf_out, dd->orig_out, 0, dd->total_save, 1); 684 685 pages = get_order(dd->total_save); 686 free_pages((unsigned long)buf_in, pages); 687 free_pages((unsigned long)buf_out, pages); 688 } 689 690 omap_des_finish_req(dd, 0); 691 omap_des_handle_queue(dd, NULL); 692 693 pr_debug("exit\n"); 694 } 695 696 static void omap_des_queue_task(unsigned long data) 697 { 698 struct omap_des_dev *dd = (struct omap_des_dev *)data; 699 700 omap_des_handle_queue(dd, NULL); 701 } 702 703 static int omap_des_crypt(struct ablkcipher_request *req, unsigned long mode) 704 { 705 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx( 706 crypto_ablkcipher_reqtfm(req)); 707 struct omap_des_reqctx *rctx = ablkcipher_request_ctx(req); 708 struct omap_des_dev *dd; 709 710 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes, 711 !!(mode & FLAGS_ENCRYPT), 712 !!(mode & FLAGS_CBC)); 713 714 if (!IS_ALIGNED(req->nbytes, DES_BLOCK_SIZE)) { 715 pr_err("request size is not exact amount of DES blocks\n"); 716 return -EINVAL; 717 } 718 719 dd = omap_des_find_dev(ctx); 720 if (!dd) 721 return -ENODEV; 722 723 rctx->mode = mode; 724 725 return omap_des_handle_queue(dd, req); 726 } 727 728 /* ********************** ALG API ************************************ */ 729 730 static int omap_des_setkey(struct crypto_ablkcipher *tfm, const u8 *key, 731 unsigned int keylen) 732 { 733 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(tfm); 734 735 if (keylen != DES_KEY_SIZE && keylen != (3*DES_KEY_SIZE)) 736 return -EINVAL; 737 738 pr_debug("enter, keylen: %d\n", keylen); 739 740 memcpy(ctx->key, key, keylen); 741 ctx->keylen = keylen; 742 743 return 0; 744 } 745 746 static int omap_des_ecb_encrypt(struct ablkcipher_request *req) 747 { 748 return omap_des_crypt(req, FLAGS_ENCRYPT); 749 } 750 751 static int omap_des_ecb_decrypt(struct ablkcipher_request *req) 752 { 753 return omap_des_crypt(req, 0); 754 } 755 756 static int omap_des_cbc_encrypt(struct ablkcipher_request *req) 757 { 758 return omap_des_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC); 759 } 760 761 static int omap_des_cbc_decrypt(struct ablkcipher_request *req) 762 { 763 return omap_des_crypt(req, FLAGS_CBC); 764 } 765 766 static int omap_des_cra_init(struct crypto_tfm *tfm) 767 { 768 pr_debug("enter\n"); 769 770 tfm->crt_ablkcipher.reqsize = sizeof(struct omap_des_reqctx); 771 772 return 0; 773 } 774 775 static void omap_des_cra_exit(struct crypto_tfm *tfm) 776 { 777 pr_debug("enter\n"); 778 } 779 780 /* ********************** ALGS ************************************ */ 781 782 static struct crypto_alg algs_ecb_cbc[] = { 783 { 784 .cra_name = "ecb(des)", 785 .cra_driver_name = "ecb-des-omap", 786 .cra_priority = 100, 787 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 788 CRYPTO_ALG_KERN_DRIVER_ONLY | 789 CRYPTO_ALG_ASYNC, 790 .cra_blocksize = DES_BLOCK_SIZE, 791 .cra_ctxsize = sizeof(struct omap_des_ctx), 792 .cra_alignmask = 0, 793 .cra_type = &crypto_ablkcipher_type, 794 .cra_module = THIS_MODULE, 795 .cra_init = omap_des_cra_init, 796 .cra_exit = omap_des_cra_exit, 797 .cra_u.ablkcipher = { 798 .min_keysize = DES_KEY_SIZE, 799 .max_keysize = DES_KEY_SIZE, 800 .setkey = omap_des_setkey, 801 .encrypt = omap_des_ecb_encrypt, 802 .decrypt = omap_des_ecb_decrypt, 803 } 804 }, 805 { 806 .cra_name = "cbc(des)", 807 .cra_driver_name = "cbc-des-omap", 808 .cra_priority = 100, 809 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 810 CRYPTO_ALG_KERN_DRIVER_ONLY | 811 CRYPTO_ALG_ASYNC, 812 .cra_blocksize = DES_BLOCK_SIZE, 813 .cra_ctxsize = sizeof(struct omap_des_ctx), 814 .cra_alignmask = 0, 815 .cra_type = &crypto_ablkcipher_type, 816 .cra_module = THIS_MODULE, 817 .cra_init = omap_des_cra_init, 818 .cra_exit = omap_des_cra_exit, 819 .cra_u.ablkcipher = { 820 .min_keysize = DES_KEY_SIZE, 821 .max_keysize = DES_KEY_SIZE, 822 .ivsize = DES_BLOCK_SIZE, 823 .setkey = omap_des_setkey, 824 .encrypt = omap_des_cbc_encrypt, 825 .decrypt = omap_des_cbc_decrypt, 826 } 827 }, 828 { 829 .cra_name = "ecb(des3_ede)", 830 .cra_driver_name = "ecb-des3-omap", 831 .cra_priority = 100, 832 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 833 CRYPTO_ALG_KERN_DRIVER_ONLY | 834 CRYPTO_ALG_ASYNC, 835 .cra_blocksize = DES_BLOCK_SIZE, 836 .cra_ctxsize = sizeof(struct omap_des_ctx), 837 .cra_alignmask = 0, 838 .cra_type = &crypto_ablkcipher_type, 839 .cra_module = THIS_MODULE, 840 .cra_init = omap_des_cra_init, 841 .cra_exit = omap_des_cra_exit, 842 .cra_u.ablkcipher = { 843 .min_keysize = 3*DES_KEY_SIZE, 844 .max_keysize = 3*DES_KEY_SIZE, 845 .setkey = omap_des_setkey, 846 .encrypt = omap_des_ecb_encrypt, 847 .decrypt = omap_des_ecb_decrypt, 848 } 849 }, 850 { 851 .cra_name = "cbc(des3_ede)", 852 .cra_driver_name = "cbc-des3-omap", 853 .cra_priority = 100, 854 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 855 CRYPTO_ALG_KERN_DRIVER_ONLY | 856 CRYPTO_ALG_ASYNC, 857 .cra_blocksize = DES_BLOCK_SIZE, 858 .cra_ctxsize = sizeof(struct omap_des_ctx), 859 .cra_alignmask = 0, 860 .cra_type = &crypto_ablkcipher_type, 861 .cra_module = THIS_MODULE, 862 .cra_init = omap_des_cra_init, 863 .cra_exit = omap_des_cra_exit, 864 .cra_u.ablkcipher = { 865 .min_keysize = 3*DES_KEY_SIZE, 866 .max_keysize = 3*DES_KEY_SIZE, 867 .ivsize = DES_BLOCK_SIZE, 868 .setkey = omap_des_setkey, 869 .encrypt = omap_des_cbc_encrypt, 870 .decrypt = omap_des_cbc_decrypt, 871 } 872 } 873 }; 874 875 static struct omap_des_algs_info omap_des_algs_info_ecb_cbc[] = { 876 { 877 .algs_list = algs_ecb_cbc, 878 .size = ARRAY_SIZE(algs_ecb_cbc), 879 }, 880 }; 881 882 #ifdef CONFIG_OF 883 static const struct omap_des_pdata omap_des_pdata_omap4 = { 884 .algs_info = omap_des_algs_info_ecb_cbc, 885 .algs_info_size = ARRAY_SIZE(omap_des_algs_info_ecb_cbc), 886 .trigger = omap_des_dma_trigger_omap4, 887 .key_ofs = 0x14, 888 .iv_ofs = 0x18, 889 .ctrl_ofs = 0x20, 890 .data_ofs = 0x28, 891 .rev_ofs = 0x30, 892 .mask_ofs = 0x34, 893 .irq_status_ofs = 0x3c, 894 .irq_enable_ofs = 0x40, 895 .dma_enable_in = BIT(5), 896 .dma_enable_out = BIT(6), 897 .major_mask = 0x0700, 898 .major_shift = 8, 899 .minor_mask = 0x003f, 900 .minor_shift = 0, 901 }; 902 903 static irqreturn_t omap_des_irq(int irq, void *dev_id) 904 { 905 struct omap_des_dev *dd = dev_id; 906 u32 status, i; 907 u32 *src, *dst; 908 909 status = omap_des_read(dd, DES_REG_IRQ_STATUS(dd)); 910 if (status & DES_REG_IRQ_DATA_IN) { 911 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0); 912 913 BUG_ON(!dd->in_sg); 914 915 BUG_ON(_calc_walked(in) > dd->in_sg->length); 916 917 src = sg_virt(dd->in_sg) + _calc_walked(in); 918 919 for (i = 0; i < DES_BLOCK_WORDS; i++) { 920 omap_des_write(dd, DES_REG_DATA_N(dd, i), *src); 921 922 scatterwalk_advance(&dd->in_walk, 4); 923 if (dd->in_sg->length == _calc_walked(in)) { 924 dd->in_sg = sg_next(dd->in_sg); 925 if (dd->in_sg) { 926 scatterwalk_start(&dd->in_walk, 927 dd->in_sg); 928 src = sg_virt(dd->in_sg) + 929 _calc_walked(in); 930 } 931 } else { 932 src++; 933 } 934 } 935 936 /* Clear IRQ status */ 937 status &= ~DES_REG_IRQ_DATA_IN; 938 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status); 939 940 /* Enable DATA_OUT interrupt */ 941 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x4); 942 943 } else if (status & DES_REG_IRQ_DATA_OUT) { 944 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0); 945 946 BUG_ON(!dd->out_sg); 947 948 BUG_ON(_calc_walked(out) > dd->out_sg->length); 949 950 dst = sg_virt(dd->out_sg) + _calc_walked(out); 951 952 for (i = 0; i < DES_BLOCK_WORDS; i++) { 953 *dst = omap_des_read(dd, DES_REG_DATA_N(dd, i)); 954 scatterwalk_advance(&dd->out_walk, 4); 955 if (dd->out_sg->length == _calc_walked(out)) { 956 dd->out_sg = sg_next(dd->out_sg); 957 if (dd->out_sg) { 958 scatterwalk_start(&dd->out_walk, 959 dd->out_sg); 960 dst = sg_virt(dd->out_sg) + 961 _calc_walked(out); 962 } 963 } else { 964 dst++; 965 } 966 } 967 968 BUG_ON(dd->total < DES_BLOCK_SIZE); 969 970 dd->total -= DES_BLOCK_SIZE; 971 972 /* Clear IRQ status */ 973 status &= ~DES_REG_IRQ_DATA_OUT; 974 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status); 975 976 if (!dd->total) 977 /* All bytes read! */ 978 tasklet_schedule(&dd->done_task); 979 else 980 /* Enable DATA_IN interrupt for next block */ 981 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2); 982 } 983 984 return IRQ_HANDLED; 985 } 986 987 static const struct of_device_id omap_des_of_match[] = { 988 { 989 .compatible = "ti,omap4-des", 990 .data = &omap_des_pdata_omap4, 991 }, 992 {}, 993 }; 994 MODULE_DEVICE_TABLE(of, omap_des_of_match); 995 996 static int omap_des_get_of(struct omap_des_dev *dd, 997 struct platform_device *pdev) 998 { 999 const struct of_device_id *match; 1000 1001 match = of_match_device(of_match_ptr(omap_des_of_match), &pdev->dev); 1002 if (!match) { 1003 dev_err(&pdev->dev, "no compatible OF match\n"); 1004 return -EINVAL; 1005 } 1006 1007 dd->dma_out = -1; /* Dummy value that's unused */ 1008 dd->dma_in = -1; /* Dummy value that's unused */ 1009 dd->pdata = match->data; 1010 1011 return 0; 1012 } 1013 #else 1014 static int omap_des_get_of(struct omap_des_dev *dd, 1015 struct device *dev) 1016 { 1017 return -EINVAL; 1018 } 1019 #endif 1020 1021 static int omap_des_get_pdev(struct omap_des_dev *dd, 1022 struct platform_device *pdev) 1023 { 1024 struct device *dev = &pdev->dev; 1025 struct resource *r; 1026 int err = 0; 1027 1028 /* Get the DMA out channel */ 1029 r = platform_get_resource(pdev, IORESOURCE_DMA, 0); 1030 if (!r) { 1031 dev_err(dev, "no DMA out resource info\n"); 1032 err = -ENODEV; 1033 goto err; 1034 } 1035 dd->dma_out = r->start; 1036 1037 /* Get the DMA in channel */ 1038 r = platform_get_resource(pdev, IORESOURCE_DMA, 1); 1039 if (!r) { 1040 dev_err(dev, "no DMA in resource info\n"); 1041 err = -ENODEV; 1042 goto err; 1043 } 1044 dd->dma_in = r->start; 1045 1046 /* non-DT devices get pdata from pdev */ 1047 dd->pdata = pdev->dev.platform_data; 1048 1049 err: 1050 return err; 1051 } 1052 1053 static int omap_des_probe(struct platform_device *pdev) 1054 { 1055 struct device *dev = &pdev->dev; 1056 struct omap_des_dev *dd; 1057 struct crypto_alg *algp; 1058 struct resource *res; 1059 int err = -ENOMEM, i, j, irq = -1; 1060 u32 reg; 1061 1062 dd = devm_kzalloc(dev, sizeof(struct omap_des_dev), GFP_KERNEL); 1063 if (dd == NULL) { 1064 dev_err(dev, "unable to alloc data struct.\n"); 1065 goto err_data; 1066 } 1067 dd->dev = dev; 1068 platform_set_drvdata(pdev, dd); 1069 1070 spin_lock_init(&dd->lock); 1071 crypto_init_queue(&dd->queue, OMAP_DES_QUEUE_LENGTH); 1072 1073 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1074 if (!res) { 1075 dev_err(dev, "no MEM resource info\n"); 1076 goto err_res; 1077 } 1078 1079 err = (dev->of_node) ? omap_des_get_of(dd, pdev) : 1080 omap_des_get_pdev(dd, pdev); 1081 if (err) 1082 goto err_res; 1083 1084 dd->io_base = devm_ioremap_resource(dev, res); 1085 if (IS_ERR(dd->io_base)) { 1086 err = PTR_ERR(dd->io_base); 1087 goto err_res; 1088 } 1089 dd->phys_base = res->start; 1090 1091 pm_runtime_enable(dev); 1092 err = pm_runtime_get_sync(dev); 1093 if (err < 0) { 1094 pm_runtime_put_noidle(dev); 1095 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err); 1096 goto err_get; 1097 } 1098 1099 omap_des_dma_stop(dd); 1100 1101 reg = omap_des_read(dd, DES_REG_REV(dd)); 1102 1103 pm_runtime_put_sync(dev); 1104 1105 dev_info(dev, "OMAP DES hw accel rev: %u.%u\n", 1106 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift, 1107 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift); 1108 1109 tasklet_init(&dd->done_task, omap_des_done_task, (unsigned long)dd); 1110 tasklet_init(&dd->queue_task, omap_des_queue_task, (unsigned long)dd); 1111 1112 err = omap_des_dma_init(dd); 1113 if (err && DES_REG_IRQ_STATUS(dd) && DES_REG_IRQ_ENABLE(dd)) { 1114 dd->pio_only = 1; 1115 1116 irq = platform_get_irq(pdev, 0); 1117 if (irq < 0) { 1118 dev_err(dev, "can't get IRQ resource\n"); 1119 goto err_irq; 1120 } 1121 1122 err = devm_request_irq(dev, irq, omap_des_irq, 0, 1123 dev_name(dev), dd); 1124 if (err) { 1125 dev_err(dev, "Unable to grab omap-des IRQ\n"); 1126 goto err_irq; 1127 } 1128 } 1129 1130 1131 INIT_LIST_HEAD(&dd->list); 1132 spin_lock(&list_lock); 1133 list_add_tail(&dd->list, &dev_list); 1134 spin_unlock(&list_lock); 1135 1136 for (i = 0; i < dd->pdata->algs_info_size; i++) { 1137 for (j = 0; j < dd->pdata->algs_info[i].size; j++) { 1138 algp = &dd->pdata->algs_info[i].algs_list[j]; 1139 1140 pr_debug("reg alg: %s\n", algp->cra_name); 1141 INIT_LIST_HEAD(&algp->cra_list); 1142 1143 err = crypto_register_alg(algp); 1144 if (err) 1145 goto err_algs; 1146 1147 dd->pdata->algs_info[i].registered++; 1148 } 1149 } 1150 1151 return 0; 1152 err_algs: 1153 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1154 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1155 crypto_unregister_alg( 1156 &dd->pdata->algs_info[i].algs_list[j]); 1157 if (!dd->pio_only) 1158 omap_des_dma_cleanup(dd); 1159 err_irq: 1160 tasklet_kill(&dd->done_task); 1161 tasklet_kill(&dd->queue_task); 1162 err_get: 1163 pm_runtime_disable(dev); 1164 err_res: 1165 dd = NULL; 1166 err_data: 1167 dev_err(dev, "initialization failed.\n"); 1168 return err; 1169 } 1170 1171 static int omap_des_remove(struct platform_device *pdev) 1172 { 1173 struct omap_des_dev *dd = platform_get_drvdata(pdev); 1174 int i, j; 1175 1176 if (!dd) 1177 return -ENODEV; 1178 1179 spin_lock(&list_lock); 1180 list_del(&dd->list); 1181 spin_unlock(&list_lock); 1182 1183 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1184 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1185 crypto_unregister_alg( 1186 &dd->pdata->algs_info[i].algs_list[j]); 1187 1188 tasklet_kill(&dd->done_task); 1189 tasklet_kill(&dd->queue_task); 1190 omap_des_dma_cleanup(dd); 1191 pm_runtime_disable(dd->dev); 1192 dd = NULL; 1193 1194 return 0; 1195 } 1196 1197 #ifdef CONFIG_PM_SLEEP 1198 static int omap_des_suspend(struct device *dev) 1199 { 1200 pm_runtime_put_sync(dev); 1201 return 0; 1202 } 1203 1204 static int omap_des_resume(struct device *dev) 1205 { 1206 int err; 1207 1208 err = pm_runtime_get_sync(dev); 1209 if (err < 0) { 1210 pm_runtime_put_noidle(dev); 1211 dev_err(dev, "%s: failed to get_sync(%d)\n", __func__, err); 1212 return err; 1213 } 1214 return 0; 1215 } 1216 #endif 1217 1218 static SIMPLE_DEV_PM_OPS(omap_des_pm_ops, omap_des_suspend, omap_des_resume); 1219 1220 static struct platform_driver omap_des_driver = { 1221 .probe = omap_des_probe, 1222 .remove = omap_des_remove, 1223 .driver = { 1224 .name = "omap-des", 1225 .pm = &omap_des_pm_ops, 1226 .of_match_table = of_match_ptr(omap_des_of_match), 1227 }, 1228 }; 1229 1230 module_platform_driver(omap_des_driver); 1231 1232 MODULE_DESCRIPTION("OMAP DES hw acceleration support."); 1233 MODULE_LICENSE("GPL v2"); 1234 MODULE_AUTHOR("Joel Fernandes <joelf@ti.com>"); 1235