1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Support for OMAP DES and Triple DES HW acceleration. 4 * 5 * Copyright (c) 2013 Texas Instruments Incorporated 6 * Author: Joel Fernandes <joelf@ti.com> 7 */ 8 9 #define pr_fmt(fmt) "%s: " fmt, __func__ 10 11 #ifdef DEBUG 12 #define prn(num) printk(#num "=%d\n", num) 13 #define prx(num) printk(#num "=%x\n", num) 14 #else 15 #define prn(num) do { } while (0) 16 #define prx(num) do { } while (0) 17 #endif 18 19 #include <linux/err.h> 20 #include <linux/module.h> 21 #include <linux/init.h> 22 #include <linux/errno.h> 23 #include <linux/kernel.h> 24 #include <linux/platform_device.h> 25 #include <linux/scatterlist.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/dmaengine.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/of.h> 30 #include <linux/of_device.h> 31 #include <linux/of_address.h> 32 #include <linux/io.h> 33 #include <linux/crypto.h> 34 #include <linux/interrupt.h> 35 #include <crypto/scatterwalk.h> 36 #include <crypto/internal/des.h> 37 #include <crypto/internal/skcipher.h> 38 #include <crypto/algapi.h> 39 #include <crypto/engine.h> 40 41 #include "omap-crypto.h" 42 43 #define DST_MAXBURST 2 44 45 #define DES_BLOCK_WORDS (DES_BLOCK_SIZE >> 2) 46 47 #define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset) 48 49 #define DES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \ 50 ((x ^ 0x01) * 0x04)) 51 52 #define DES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04)) 53 54 #define DES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs) 55 #define DES_REG_CTRL_CBC BIT(4) 56 #define DES_REG_CTRL_TDES BIT(3) 57 #define DES_REG_CTRL_DIRECTION BIT(2) 58 #define DES_REG_CTRL_INPUT_READY BIT(1) 59 #define DES_REG_CTRL_OUTPUT_READY BIT(0) 60 61 #define DES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04)) 62 63 #define DES_REG_REV(dd) ((dd)->pdata->rev_ofs) 64 65 #define DES_REG_MASK(dd) ((dd)->pdata->mask_ofs) 66 67 #define DES_REG_LENGTH_N(x) (0x24 + ((x) * 0x04)) 68 69 #define DES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs) 70 #define DES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs) 71 #define DES_REG_IRQ_DATA_IN BIT(1) 72 #define DES_REG_IRQ_DATA_OUT BIT(2) 73 74 #define FLAGS_MODE_MASK 0x000f 75 #define FLAGS_ENCRYPT BIT(0) 76 #define FLAGS_CBC BIT(1) 77 #define FLAGS_INIT BIT(4) 78 #define FLAGS_BUSY BIT(6) 79 80 #define DEFAULT_AUTOSUSPEND_DELAY 1000 81 82 #define FLAGS_IN_DATA_ST_SHIFT 8 83 #define FLAGS_OUT_DATA_ST_SHIFT 10 84 85 struct omap_des_ctx { 86 struct crypto_engine_ctx enginectx; 87 struct omap_des_dev *dd; 88 89 int keylen; 90 __le32 key[(3 * DES_KEY_SIZE) / sizeof(u32)]; 91 unsigned long flags; 92 }; 93 94 struct omap_des_reqctx { 95 unsigned long mode; 96 }; 97 98 #define OMAP_DES_QUEUE_LENGTH 1 99 #define OMAP_DES_CACHE_SIZE 0 100 101 struct omap_des_algs_info { 102 struct skcipher_alg *algs_list; 103 unsigned int size; 104 unsigned int registered; 105 }; 106 107 struct omap_des_pdata { 108 struct omap_des_algs_info *algs_info; 109 unsigned int algs_info_size; 110 111 void (*trigger)(struct omap_des_dev *dd, int length); 112 113 u32 key_ofs; 114 u32 iv_ofs; 115 u32 ctrl_ofs; 116 u32 data_ofs; 117 u32 rev_ofs; 118 u32 mask_ofs; 119 u32 irq_enable_ofs; 120 u32 irq_status_ofs; 121 122 u32 dma_enable_in; 123 u32 dma_enable_out; 124 u32 dma_start; 125 126 u32 major_mask; 127 u32 major_shift; 128 u32 minor_mask; 129 u32 minor_shift; 130 }; 131 132 struct omap_des_dev { 133 struct list_head list; 134 unsigned long phys_base; 135 void __iomem *io_base; 136 struct omap_des_ctx *ctx; 137 struct device *dev; 138 unsigned long flags; 139 int err; 140 141 struct tasklet_struct done_task; 142 143 struct skcipher_request *req; 144 struct crypto_engine *engine; 145 /* 146 * total is used by PIO mode for book keeping so introduce 147 * variable total_save as need it to calc page_order 148 */ 149 size_t total; 150 size_t total_save; 151 152 struct scatterlist *in_sg; 153 struct scatterlist *out_sg; 154 155 /* Buffers for copying for unaligned cases */ 156 struct scatterlist in_sgl; 157 struct scatterlist out_sgl; 158 struct scatterlist *orig_out; 159 160 struct scatter_walk in_walk; 161 struct scatter_walk out_walk; 162 struct dma_chan *dma_lch_in; 163 struct dma_chan *dma_lch_out; 164 int in_sg_len; 165 int out_sg_len; 166 int pio_only; 167 const struct omap_des_pdata *pdata; 168 }; 169 170 /* keep registered devices data here */ 171 static LIST_HEAD(dev_list); 172 static DEFINE_SPINLOCK(list_lock); 173 174 #ifdef DEBUG 175 #define omap_des_read(dd, offset) \ 176 ({ \ 177 int _read_ret; \ 178 _read_ret = __raw_readl(dd->io_base + offset); \ 179 pr_err("omap_des_read(" #offset "=%#x)= %#x\n", \ 180 offset, _read_ret); \ 181 _read_ret; \ 182 }) 183 #else 184 static inline u32 omap_des_read(struct omap_des_dev *dd, u32 offset) 185 { 186 return __raw_readl(dd->io_base + offset); 187 } 188 #endif 189 190 #ifdef DEBUG 191 #define omap_des_write(dd, offset, value) \ 192 do { \ 193 pr_err("omap_des_write(" #offset "=%#x) value=%#x\n", \ 194 offset, value); \ 195 __raw_writel(value, dd->io_base + offset); \ 196 } while (0) 197 #else 198 static inline void omap_des_write(struct omap_des_dev *dd, u32 offset, 199 u32 value) 200 { 201 __raw_writel(value, dd->io_base + offset); 202 } 203 #endif 204 205 static inline void omap_des_write_mask(struct omap_des_dev *dd, u32 offset, 206 u32 value, u32 mask) 207 { 208 u32 val; 209 210 val = omap_des_read(dd, offset); 211 val &= ~mask; 212 val |= value; 213 omap_des_write(dd, offset, val); 214 } 215 216 static void omap_des_write_n(struct omap_des_dev *dd, u32 offset, 217 u32 *value, int count) 218 { 219 for (; count--; value++, offset += 4) 220 omap_des_write(dd, offset, *value); 221 } 222 223 static int omap_des_hw_init(struct omap_des_dev *dd) 224 { 225 int err; 226 227 /* 228 * clocks are enabled when request starts and disabled when finished. 229 * It may be long delays between requests. 230 * Device might go to off mode to save power. 231 */ 232 err = pm_runtime_resume_and_get(dd->dev); 233 if (err < 0) { 234 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err); 235 return err; 236 } 237 238 if (!(dd->flags & FLAGS_INIT)) { 239 dd->flags |= FLAGS_INIT; 240 dd->err = 0; 241 } 242 243 return 0; 244 } 245 246 static int omap_des_write_ctrl(struct omap_des_dev *dd) 247 { 248 unsigned int key32; 249 int i, err; 250 u32 val = 0, mask = 0; 251 252 err = omap_des_hw_init(dd); 253 if (err) 254 return err; 255 256 key32 = dd->ctx->keylen / sizeof(u32); 257 258 /* it seems a key should always be set even if it has not changed */ 259 for (i = 0; i < key32; i++) { 260 omap_des_write(dd, DES_REG_KEY(dd, i), 261 __le32_to_cpu(dd->ctx->key[i])); 262 } 263 264 if ((dd->flags & FLAGS_CBC) && dd->req->iv) 265 omap_des_write_n(dd, DES_REG_IV(dd, 0), (void *)dd->req->iv, 2); 266 267 if (dd->flags & FLAGS_CBC) 268 val |= DES_REG_CTRL_CBC; 269 if (dd->flags & FLAGS_ENCRYPT) 270 val |= DES_REG_CTRL_DIRECTION; 271 if (key32 == 6) 272 val |= DES_REG_CTRL_TDES; 273 274 mask |= DES_REG_CTRL_CBC | DES_REG_CTRL_DIRECTION | DES_REG_CTRL_TDES; 275 276 omap_des_write_mask(dd, DES_REG_CTRL(dd), val, mask); 277 278 return 0; 279 } 280 281 static void omap_des_dma_trigger_omap4(struct omap_des_dev *dd, int length) 282 { 283 u32 mask, val; 284 285 omap_des_write(dd, DES_REG_LENGTH_N(0), length); 286 287 val = dd->pdata->dma_start; 288 289 if (dd->dma_lch_out != NULL) 290 val |= dd->pdata->dma_enable_out; 291 if (dd->dma_lch_in != NULL) 292 val |= dd->pdata->dma_enable_in; 293 294 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | 295 dd->pdata->dma_start; 296 297 omap_des_write_mask(dd, DES_REG_MASK(dd), val, mask); 298 } 299 300 static void omap_des_dma_stop(struct omap_des_dev *dd) 301 { 302 u32 mask; 303 304 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | 305 dd->pdata->dma_start; 306 307 omap_des_write_mask(dd, DES_REG_MASK(dd), 0, mask); 308 } 309 310 static struct omap_des_dev *omap_des_find_dev(struct omap_des_ctx *ctx) 311 { 312 struct omap_des_dev *dd = NULL, *tmp; 313 314 spin_lock_bh(&list_lock); 315 if (!ctx->dd) { 316 list_for_each_entry(tmp, &dev_list, list) { 317 /* FIXME: take fist available des core */ 318 dd = tmp; 319 break; 320 } 321 ctx->dd = dd; 322 } else { 323 /* already found before */ 324 dd = ctx->dd; 325 } 326 spin_unlock_bh(&list_lock); 327 328 return dd; 329 } 330 331 static void omap_des_dma_out_callback(void *data) 332 { 333 struct omap_des_dev *dd = data; 334 335 /* dma_lch_out - completed */ 336 tasklet_schedule(&dd->done_task); 337 } 338 339 static int omap_des_dma_init(struct omap_des_dev *dd) 340 { 341 int err; 342 343 dd->dma_lch_out = NULL; 344 dd->dma_lch_in = NULL; 345 346 dd->dma_lch_in = dma_request_chan(dd->dev, "rx"); 347 if (IS_ERR(dd->dma_lch_in)) { 348 dev_err(dd->dev, "Unable to request in DMA channel\n"); 349 return PTR_ERR(dd->dma_lch_in); 350 } 351 352 dd->dma_lch_out = dma_request_chan(dd->dev, "tx"); 353 if (IS_ERR(dd->dma_lch_out)) { 354 dev_err(dd->dev, "Unable to request out DMA channel\n"); 355 err = PTR_ERR(dd->dma_lch_out); 356 goto err_dma_out; 357 } 358 359 return 0; 360 361 err_dma_out: 362 dma_release_channel(dd->dma_lch_in); 363 364 return err; 365 } 366 367 static void omap_des_dma_cleanup(struct omap_des_dev *dd) 368 { 369 if (dd->pio_only) 370 return; 371 372 dma_release_channel(dd->dma_lch_out); 373 dma_release_channel(dd->dma_lch_in); 374 } 375 376 static int omap_des_crypt_dma(struct crypto_tfm *tfm, 377 struct scatterlist *in_sg, struct scatterlist *out_sg, 378 int in_sg_len, int out_sg_len) 379 { 380 struct omap_des_ctx *ctx = crypto_tfm_ctx(tfm); 381 struct omap_des_dev *dd = ctx->dd; 382 struct dma_async_tx_descriptor *tx_in, *tx_out; 383 struct dma_slave_config cfg; 384 int ret; 385 386 if (dd->pio_only) { 387 scatterwalk_start(&dd->in_walk, dd->in_sg); 388 scatterwalk_start(&dd->out_walk, dd->out_sg); 389 390 /* Enable DATAIN interrupt and let it take 391 care of the rest */ 392 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2); 393 return 0; 394 } 395 396 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE); 397 398 memset(&cfg, 0, sizeof(cfg)); 399 400 cfg.src_addr = dd->phys_base + DES_REG_DATA_N(dd, 0); 401 cfg.dst_addr = dd->phys_base + DES_REG_DATA_N(dd, 0); 402 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 403 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 404 cfg.src_maxburst = DST_MAXBURST; 405 cfg.dst_maxburst = DST_MAXBURST; 406 407 /* IN */ 408 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg); 409 if (ret) { 410 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n", 411 ret); 412 return ret; 413 } 414 415 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len, 416 DMA_MEM_TO_DEV, 417 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 418 if (!tx_in) { 419 dev_err(dd->dev, "IN prep_slave_sg() failed\n"); 420 return -EINVAL; 421 } 422 423 /* No callback necessary */ 424 tx_in->callback_param = dd; 425 426 /* OUT */ 427 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg); 428 if (ret) { 429 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n", 430 ret); 431 return ret; 432 } 433 434 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len, 435 DMA_DEV_TO_MEM, 436 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 437 if (!tx_out) { 438 dev_err(dd->dev, "OUT prep_slave_sg() failed\n"); 439 return -EINVAL; 440 } 441 442 tx_out->callback = omap_des_dma_out_callback; 443 tx_out->callback_param = dd; 444 445 dmaengine_submit(tx_in); 446 dmaengine_submit(tx_out); 447 448 dma_async_issue_pending(dd->dma_lch_in); 449 dma_async_issue_pending(dd->dma_lch_out); 450 451 /* start DMA */ 452 dd->pdata->trigger(dd, dd->total); 453 454 return 0; 455 } 456 457 static int omap_des_crypt_dma_start(struct omap_des_dev *dd) 458 { 459 struct crypto_tfm *tfm = crypto_skcipher_tfm( 460 crypto_skcipher_reqtfm(dd->req)); 461 int err; 462 463 pr_debug("total: %zd\n", dd->total); 464 465 if (!dd->pio_only) { 466 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len, 467 DMA_TO_DEVICE); 468 if (!err) { 469 dev_err(dd->dev, "dma_map_sg() error\n"); 470 return -EINVAL; 471 } 472 473 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len, 474 DMA_FROM_DEVICE); 475 if (!err) { 476 dev_err(dd->dev, "dma_map_sg() error\n"); 477 return -EINVAL; 478 } 479 } 480 481 err = omap_des_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len, 482 dd->out_sg_len); 483 if (err && !dd->pio_only) { 484 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 485 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, 486 DMA_FROM_DEVICE); 487 } 488 489 return err; 490 } 491 492 static void omap_des_finish_req(struct omap_des_dev *dd, int err) 493 { 494 struct skcipher_request *req = dd->req; 495 496 pr_debug("err: %d\n", err); 497 498 crypto_finalize_skcipher_request(dd->engine, req, err); 499 500 pm_runtime_mark_last_busy(dd->dev); 501 pm_runtime_put_autosuspend(dd->dev); 502 } 503 504 static int omap_des_crypt_dma_stop(struct omap_des_dev *dd) 505 { 506 pr_debug("total: %zd\n", dd->total); 507 508 omap_des_dma_stop(dd); 509 510 dmaengine_terminate_all(dd->dma_lch_in); 511 dmaengine_terminate_all(dd->dma_lch_out); 512 513 return 0; 514 } 515 516 static int omap_des_handle_queue(struct omap_des_dev *dd, 517 struct skcipher_request *req) 518 { 519 if (req) 520 return crypto_transfer_skcipher_request_to_engine(dd->engine, req); 521 522 return 0; 523 } 524 525 static int omap_des_prepare_req(struct skcipher_request *req, 526 struct omap_des_dev *dd) 527 { 528 struct omap_des_ctx *ctx = crypto_skcipher_ctx( 529 crypto_skcipher_reqtfm(req)); 530 struct omap_des_reqctx *rctx; 531 int ret; 532 u16 flags; 533 534 /* assign new request to device */ 535 dd->req = req; 536 dd->total = req->cryptlen; 537 dd->total_save = req->cryptlen; 538 dd->in_sg = req->src; 539 dd->out_sg = req->dst; 540 dd->orig_out = req->dst; 541 542 flags = OMAP_CRYPTO_COPY_DATA; 543 if (req->src == req->dst) 544 flags |= OMAP_CRYPTO_FORCE_COPY; 545 546 ret = omap_crypto_align_sg(&dd->in_sg, dd->total, DES_BLOCK_SIZE, 547 &dd->in_sgl, flags, 548 FLAGS_IN_DATA_ST_SHIFT, &dd->flags); 549 if (ret) 550 return ret; 551 552 ret = omap_crypto_align_sg(&dd->out_sg, dd->total, DES_BLOCK_SIZE, 553 &dd->out_sgl, 0, 554 FLAGS_OUT_DATA_ST_SHIFT, &dd->flags); 555 if (ret) 556 return ret; 557 558 dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total); 559 if (dd->in_sg_len < 0) 560 return dd->in_sg_len; 561 562 dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total); 563 if (dd->out_sg_len < 0) 564 return dd->out_sg_len; 565 566 rctx = skcipher_request_ctx(req); 567 ctx = crypto_skcipher_ctx(crypto_skcipher_reqtfm(req)); 568 rctx->mode &= FLAGS_MODE_MASK; 569 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode; 570 571 dd->ctx = ctx; 572 ctx->dd = dd; 573 574 return omap_des_write_ctrl(dd); 575 } 576 577 static int omap_des_crypt_req(struct crypto_engine *engine, 578 void *areq) 579 { 580 struct skcipher_request *req = container_of(areq, struct skcipher_request, base); 581 struct omap_des_ctx *ctx = crypto_skcipher_ctx( 582 crypto_skcipher_reqtfm(req)); 583 struct omap_des_dev *dd = omap_des_find_dev(ctx); 584 585 if (!dd) 586 return -ENODEV; 587 588 return omap_des_prepare_req(req, dd) ?: 589 omap_des_crypt_dma_start(dd); 590 } 591 592 static void omap_des_done_task(unsigned long data) 593 { 594 struct omap_des_dev *dd = (struct omap_des_dev *)data; 595 int i; 596 597 pr_debug("enter done_task\n"); 598 599 if (!dd->pio_only) { 600 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len, 601 DMA_FROM_DEVICE); 602 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 603 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, 604 DMA_FROM_DEVICE); 605 omap_des_crypt_dma_stop(dd); 606 } 607 608 omap_crypto_cleanup(&dd->in_sgl, NULL, 0, dd->total_save, 609 FLAGS_IN_DATA_ST_SHIFT, dd->flags); 610 611 omap_crypto_cleanup(&dd->out_sgl, dd->orig_out, 0, dd->total_save, 612 FLAGS_OUT_DATA_ST_SHIFT, dd->flags); 613 614 if ((dd->flags & FLAGS_CBC) && dd->req->iv) 615 for (i = 0; i < 2; i++) 616 ((u32 *)dd->req->iv)[i] = 617 omap_des_read(dd, DES_REG_IV(dd, i)); 618 619 omap_des_finish_req(dd, 0); 620 621 pr_debug("exit\n"); 622 } 623 624 static int omap_des_crypt(struct skcipher_request *req, unsigned long mode) 625 { 626 struct omap_des_ctx *ctx = crypto_skcipher_ctx( 627 crypto_skcipher_reqtfm(req)); 628 struct omap_des_reqctx *rctx = skcipher_request_ctx(req); 629 struct omap_des_dev *dd; 630 631 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->cryptlen, 632 !!(mode & FLAGS_ENCRYPT), 633 !!(mode & FLAGS_CBC)); 634 635 if (!req->cryptlen) 636 return 0; 637 638 if (!IS_ALIGNED(req->cryptlen, DES_BLOCK_SIZE)) 639 return -EINVAL; 640 641 dd = omap_des_find_dev(ctx); 642 if (!dd) 643 return -ENODEV; 644 645 rctx->mode = mode; 646 647 return omap_des_handle_queue(dd, req); 648 } 649 650 /* ********************** ALG API ************************************ */ 651 652 static int omap_des_setkey(struct crypto_skcipher *cipher, const u8 *key, 653 unsigned int keylen) 654 { 655 struct omap_des_ctx *ctx = crypto_skcipher_ctx(cipher); 656 int err; 657 658 pr_debug("enter, keylen: %d\n", keylen); 659 660 err = verify_skcipher_des_key(cipher, key); 661 if (err) 662 return err; 663 664 memcpy(ctx->key, key, keylen); 665 ctx->keylen = keylen; 666 667 return 0; 668 } 669 670 static int omap_des3_setkey(struct crypto_skcipher *cipher, const u8 *key, 671 unsigned int keylen) 672 { 673 struct omap_des_ctx *ctx = crypto_skcipher_ctx(cipher); 674 int err; 675 676 pr_debug("enter, keylen: %d\n", keylen); 677 678 err = verify_skcipher_des3_key(cipher, key); 679 if (err) 680 return err; 681 682 memcpy(ctx->key, key, keylen); 683 ctx->keylen = keylen; 684 685 return 0; 686 } 687 688 static int omap_des_ecb_encrypt(struct skcipher_request *req) 689 { 690 return omap_des_crypt(req, FLAGS_ENCRYPT); 691 } 692 693 static int omap_des_ecb_decrypt(struct skcipher_request *req) 694 { 695 return omap_des_crypt(req, 0); 696 } 697 698 static int omap_des_cbc_encrypt(struct skcipher_request *req) 699 { 700 return omap_des_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC); 701 } 702 703 static int omap_des_cbc_decrypt(struct skcipher_request *req) 704 { 705 return omap_des_crypt(req, FLAGS_CBC); 706 } 707 708 static int omap_des_init_tfm(struct crypto_skcipher *tfm) 709 { 710 struct omap_des_ctx *ctx = crypto_skcipher_ctx(tfm); 711 712 pr_debug("enter\n"); 713 714 crypto_skcipher_set_reqsize(tfm, sizeof(struct omap_des_reqctx)); 715 716 ctx->enginectx.op.do_one_request = omap_des_crypt_req; 717 718 return 0; 719 } 720 721 /* ********************** ALGS ************************************ */ 722 723 static struct skcipher_alg algs_ecb_cbc[] = { 724 { 725 .base.cra_name = "ecb(des)", 726 .base.cra_driver_name = "ecb-des-omap", 727 .base.cra_priority = 300, 728 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 729 CRYPTO_ALG_ASYNC, 730 .base.cra_blocksize = DES_BLOCK_SIZE, 731 .base.cra_ctxsize = sizeof(struct omap_des_ctx), 732 .base.cra_module = THIS_MODULE, 733 734 .min_keysize = DES_KEY_SIZE, 735 .max_keysize = DES_KEY_SIZE, 736 .setkey = omap_des_setkey, 737 .encrypt = omap_des_ecb_encrypt, 738 .decrypt = omap_des_ecb_decrypt, 739 .init = omap_des_init_tfm, 740 }, 741 { 742 .base.cra_name = "cbc(des)", 743 .base.cra_driver_name = "cbc-des-omap", 744 .base.cra_priority = 300, 745 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 746 CRYPTO_ALG_ASYNC, 747 .base.cra_blocksize = DES_BLOCK_SIZE, 748 .base.cra_ctxsize = sizeof(struct omap_des_ctx), 749 .base.cra_module = THIS_MODULE, 750 751 .min_keysize = DES_KEY_SIZE, 752 .max_keysize = DES_KEY_SIZE, 753 .ivsize = DES_BLOCK_SIZE, 754 .setkey = omap_des_setkey, 755 .encrypt = omap_des_cbc_encrypt, 756 .decrypt = omap_des_cbc_decrypt, 757 .init = omap_des_init_tfm, 758 }, 759 { 760 .base.cra_name = "ecb(des3_ede)", 761 .base.cra_driver_name = "ecb-des3-omap", 762 .base.cra_priority = 300, 763 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 764 CRYPTO_ALG_ASYNC, 765 .base.cra_blocksize = DES3_EDE_BLOCK_SIZE, 766 .base.cra_ctxsize = sizeof(struct omap_des_ctx), 767 .base.cra_module = THIS_MODULE, 768 769 .min_keysize = DES3_EDE_KEY_SIZE, 770 .max_keysize = DES3_EDE_KEY_SIZE, 771 .setkey = omap_des3_setkey, 772 .encrypt = omap_des_ecb_encrypt, 773 .decrypt = omap_des_ecb_decrypt, 774 .init = omap_des_init_tfm, 775 }, 776 { 777 .base.cra_name = "cbc(des3_ede)", 778 .base.cra_driver_name = "cbc-des3-omap", 779 .base.cra_priority = 300, 780 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 781 CRYPTO_ALG_ASYNC, 782 .base.cra_blocksize = DES3_EDE_BLOCK_SIZE, 783 .base.cra_ctxsize = sizeof(struct omap_des_ctx), 784 .base.cra_module = THIS_MODULE, 785 786 .min_keysize = DES3_EDE_KEY_SIZE, 787 .max_keysize = DES3_EDE_KEY_SIZE, 788 .ivsize = DES3_EDE_BLOCK_SIZE, 789 .setkey = omap_des3_setkey, 790 .encrypt = omap_des_cbc_encrypt, 791 .decrypt = omap_des_cbc_decrypt, 792 .init = omap_des_init_tfm, 793 } 794 }; 795 796 static struct omap_des_algs_info omap_des_algs_info_ecb_cbc[] = { 797 { 798 .algs_list = algs_ecb_cbc, 799 .size = ARRAY_SIZE(algs_ecb_cbc), 800 }, 801 }; 802 803 #ifdef CONFIG_OF 804 static const struct omap_des_pdata omap_des_pdata_omap4 = { 805 .algs_info = omap_des_algs_info_ecb_cbc, 806 .algs_info_size = ARRAY_SIZE(omap_des_algs_info_ecb_cbc), 807 .trigger = omap_des_dma_trigger_omap4, 808 .key_ofs = 0x14, 809 .iv_ofs = 0x18, 810 .ctrl_ofs = 0x20, 811 .data_ofs = 0x28, 812 .rev_ofs = 0x30, 813 .mask_ofs = 0x34, 814 .irq_status_ofs = 0x3c, 815 .irq_enable_ofs = 0x40, 816 .dma_enable_in = BIT(5), 817 .dma_enable_out = BIT(6), 818 .major_mask = 0x0700, 819 .major_shift = 8, 820 .minor_mask = 0x003f, 821 .minor_shift = 0, 822 }; 823 824 static irqreturn_t omap_des_irq(int irq, void *dev_id) 825 { 826 struct omap_des_dev *dd = dev_id; 827 u32 status, i; 828 u32 *src, *dst; 829 830 status = omap_des_read(dd, DES_REG_IRQ_STATUS(dd)); 831 if (status & DES_REG_IRQ_DATA_IN) { 832 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0); 833 834 BUG_ON(!dd->in_sg); 835 836 BUG_ON(_calc_walked(in) > dd->in_sg->length); 837 838 src = sg_virt(dd->in_sg) + _calc_walked(in); 839 840 for (i = 0; i < DES_BLOCK_WORDS; i++) { 841 omap_des_write(dd, DES_REG_DATA_N(dd, i), *src); 842 843 scatterwalk_advance(&dd->in_walk, 4); 844 if (dd->in_sg->length == _calc_walked(in)) { 845 dd->in_sg = sg_next(dd->in_sg); 846 if (dd->in_sg) { 847 scatterwalk_start(&dd->in_walk, 848 dd->in_sg); 849 src = sg_virt(dd->in_sg) + 850 _calc_walked(in); 851 } 852 } else { 853 src++; 854 } 855 } 856 857 /* Clear IRQ status */ 858 status &= ~DES_REG_IRQ_DATA_IN; 859 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status); 860 861 /* Enable DATA_OUT interrupt */ 862 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x4); 863 864 } else if (status & DES_REG_IRQ_DATA_OUT) { 865 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0); 866 867 BUG_ON(!dd->out_sg); 868 869 BUG_ON(_calc_walked(out) > dd->out_sg->length); 870 871 dst = sg_virt(dd->out_sg) + _calc_walked(out); 872 873 for (i = 0; i < DES_BLOCK_WORDS; i++) { 874 *dst = omap_des_read(dd, DES_REG_DATA_N(dd, i)); 875 scatterwalk_advance(&dd->out_walk, 4); 876 if (dd->out_sg->length == _calc_walked(out)) { 877 dd->out_sg = sg_next(dd->out_sg); 878 if (dd->out_sg) { 879 scatterwalk_start(&dd->out_walk, 880 dd->out_sg); 881 dst = sg_virt(dd->out_sg) + 882 _calc_walked(out); 883 } 884 } else { 885 dst++; 886 } 887 } 888 889 BUG_ON(dd->total < DES_BLOCK_SIZE); 890 891 dd->total -= DES_BLOCK_SIZE; 892 893 /* Clear IRQ status */ 894 status &= ~DES_REG_IRQ_DATA_OUT; 895 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status); 896 897 if (!dd->total) 898 /* All bytes read! */ 899 tasklet_schedule(&dd->done_task); 900 else 901 /* Enable DATA_IN interrupt for next block */ 902 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2); 903 } 904 905 return IRQ_HANDLED; 906 } 907 908 static const struct of_device_id omap_des_of_match[] = { 909 { 910 .compatible = "ti,omap4-des", 911 .data = &omap_des_pdata_omap4, 912 }, 913 {}, 914 }; 915 MODULE_DEVICE_TABLE(of, omap_des_of_match); 916 917 static int omap_des_get_of(struct omap_des_dev *dd, 918 struct platform_device *pdev) 919 { 920 921 dd->pdata = of_device_get_match_data(&pdev->dev); 922 if (!dd->pdata) { 923 dev_err(&pdev->dev, "no compatible OF match\n"); 924 return -EINVAL; 925 } 926 927 return 0; 928 } 929 #else 930 static int omap_des_get_of(struct omap_des_dev *dd, 931 struct device *dev) 932 { 933 return -EINVAL; 934 } 935 #endif 936 937 static int omap_des_get_pdev(struct omap_des_dev *dd, 938 struct platform_device *pdev) 939 { 940 /* non-DT devices get pdata from pdev */ 941 dd->pdata = pdev->dev.platform_data; 942 943 return 0; 944 } 945 946 static int omap_des_probe(struct platform_device *pdev) 947 { 948 struct device *dev = &pdev->dev; 949 struct omap_des_dev *dd; 950 struct skcipher_alg *algp; 951 struct resource *res; 952 int err = -ENOMEM, i, j, irq = -1; 953 u32 reg; 954 955 dd = devm_kzalloc(dev, sizeof(struct omap_des_dev), GFP_KERNEL); 956 if (dd == NULL) { 957 dev_err(dev, "unable to alloc data struct.\n"); 958 goto err_data; 959 } 960 dd->dev = dev; 961 platform_set_drvdata(pdev, dd); 962 963 err = (dev->of_node) ? omap_des_get_of(dd, pdev) : 964 omap_des_get_pdev(dd, pdev); 965 if (err) 966 goto err_res; 967 968 dd->io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 969 if (IS_ERR(dd->io_base)) { 970 err = PTR_ERR(dd->io_base); 971 goto err_res; 972 } 973 dd->phys_base = res->start; 974 975 pm_runtime_use_autosuspend(dev); 976 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY); 977 978 pm_runtime_enable(dev); 979 err = pm_runtime_resume_and_get(dev); 980 if (err < 0) { 981 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err); 982 goto err_get; 983 } 984 985 omap_des_dma_stop(dd); 986 987 reg = omap_des_read(dd, DES_REG_REV(dd)); 988 989 pm_runtime_put_sync(dev); 990 991 dev_info(dev, "OMAP DES hw accel rev: %u.%u\n", 992 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift, 993 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift); 994 995 tasklet_init(&dd->done_task, omap_des_done_task, (unsigned long)dd); 996 997 err = omap_des_dma_init(dd); 998 if (err == -EPROBE_DEFER) { 999 goto err_irq; 1000 } else if (err && DES_REG_IRQ_STATUS(dd) && DES_REG_IRQ_ENABLE(dd)) { 1001 dd->pio_only = 1; 1002 1003 irq = platform_get_irq(pdev, 0); 1004 if (irq < 0) { 1005 err = irq; 1006 goto err_irq; 1007 } 1008 1009 err = devm_request_irq(dev, irq, omap_des_irq, 0, 1010 dev_name(dev), dd); 1011 if (err) { 1012 dev_err(dev, "Unable to grab omap-des IRQ\n"); 1013 goto err_irq; 1014 } 1015 } 1016 1017 1018 INIT_LIST_HEAD(&dd->list); 1019 spin_lock_bh(&list_lock); 1020 list_add_tail(&dd->list, &dev_list); 1021 spin_unlock_bh(&list_lock); 1022 1023 /* Initialize des crypto engine */ 1024 dd->engine = crypto_engine_alloc_init(dev, 1); 1025 if (!dd->engine) { 1026 err = -ENOMEM; 1027 goto err_engine; 1028 } 1029 1030 err = crypto_engine_start(dd->engine); 1031 if (err) 1032 goto err_engine; 1033 1034 for (i = 0; i < dd->pdata->algs_info_size; i++) { 1035 for (j = 0; j < dd->pdata->algs_info[i].size; j++) { 1036 algp = &dd->pdata->algs_info[i].algs_list[j]; 1037 1038 pr_debug("reg alg: %s\n", algp->base.cra_name); 1039 1040 err = crypto_register_skcipher(algp); 1041 if (err) 1042 goto err_algs; 1043 1044 dd->pdata->algs_info[i].registered++; 1045 } 1046 } 1047 1048 return 0; 1049 1050 err_algs: 1051 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1052 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1053 crypto_unregister_skcipher( 1054 &dd->pdata->algs_info[i].algs_list[j]); 1055 1056 err_engine: 1057 if (dd->engine) 1058 crypto_engine_exit(dd->engine); 1059 1060 omap_des_dma_cleanup(dd); 1061 err_irq: 1062 tasklet_kill(&dd->done_task); 1063 err_get: 1064 pm_runtime_disable(dev); 1065 err_res: 1066 dd = NULL; 1067 err_data: 1068 dev_err(dev, "initialization failed.\n"); 1069 return err; 1070 } 1071 1072 static int omap_des_remove(struct platform_device *pdev) 1073 { 1074 struct omap_des_dev *dd = platform_get_drvdata(pdev); 1075 int i, j; 1076 1077 spin_lock_bh(&list_lock); 1078 list_del(&dd->list); 1079 spin_unlock_bh(&list_lock); 1080 1081 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1082 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1083 crypto_unregister_skcipher( 1084 &dd->pdata->algs_info[i].algs_list[j]); 1085 1086 tasklet_kill(&dd->done_task); 1087 omap_des_dma_cleanup(dd); 1088 pm_runtime_disable(dd->dev); 1089 1090 return 0; 1091 } 1092 1093 #ifdef CONFIG_PM_SLEEP 1094 static int omap_des_suspend(struct device *dev) 1095 { 1096 pm_runtime_put_sync(dev); 1097 return 0; 1098 } 1099 1100 static int omap_des_resume(struct device *dev) 1101 { 1102 int err; 1103 1104 err = pm_runtime_resume_and_get(dev); 1105 if (err < 0) { 1106 dev_err(dev, "%s: failed to get_sync(%d)\n", __func__, err); 1107 return err; 1108 } 1109 return 0; 1110 } 1111 #endif 1112 1113 static SIMPLE_DEV_PM_OPS(omap_des_pm_ops, omap_des_suspend, omap_des_resume); 1114 1115 static struct platform_driver omap_des_driver = { 1116 .probe = omap_des_probe, 1117 .remove = omap_des_remove, 1118 .driver = { 1119 .name = "omap-des", 1120 .pm = &omap_des_pm_ops, 1121 .of_match_table = of_match_ptr(omap_des_of_match), 1122 }, 1123 }; 1124 1125 module_platform_driver(omap_des_driver); 1126 1127 MODULE_DESCRIPTION("OMAP DES hw acceleration support."); 1128 MODULE_LICENSE("GPL v2"); 1129 MODULE_AUTHOR("Joel Fernandes <joelf@ti.com>"); 1130