1 /* 2 * Support for OMAP DES and Triple DES HW acceleration. 3 * 4 * Copyright (c) 2013 Texas Instruments Incorporated 5 * Author: Joel Fernandes <joelf@ti.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as published 9 * by the Free Software Foundation. 10 * 11 */ 12 13 #define pr_fmt(fmt) "%s: " fmt, __func__ 14 15 #ifdef DEBUG 16 #define prn(num) printk(#num "=%d\n", num) 17 #define prx(num) printk(#num "=%x\n", num) 18 #else 19 #define prn(num) do { } while (0) 20 #define prx(num) do { } while (0) 21 #endif 22 23 #include <linux/err.h> 24 #include <linux/module.h> 25 #include <linux/init.h> 26 #include <linux/errno.h> 27 #include <linux/kernel.h> 28 #include <linux/platform_device.h> 29 #include <linux/scatterlist.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/dmaengine.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/of.h> 34 #include <linux/of_device.h> 35 #include <linux/of_address.h> 36 #include <linux/io.h> 37 #include <linux/crypto.h> 38 #include <linux/interrupt.h> 39 #include <crypto/scatterwalk.h> 40 #include <crypto/des.h> 41 #include <crypto/algapi.h> 42 #include <crypto/engine.h> 43 44 #include "omap-crypto.h" 45 46 #define DST_MAXBURST 2 47 48 #define DES_BLOCK_WORDS (DES_BLOCK_SIZE >> 2) 49 50 #define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset) 51 52 #define DES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \ 53 ((x ^ 0x01) * 0x04)) 54 55 #define DES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04)) 56 57 #define DES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs) 58 #define DES_REG_CTRL_CBC BIT(4) 59 #define DES_REG_CTRL_TDES BIT(3) 60 #define DES_REG_CTRL_DIRECTION BIT(2) 61 #define DES_REG_CTRL_INPUT_READY BIT(1) 62 #define DES_REG_CTRL_OUTPUT_READY BIT(0) 63 64 #define DES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04)) 65 66 #define DES_REG_REV(dd) ((dd)->pdata->rev_ofs) 67 68 #define DES_REG_MASK(dd) ((dd)->pdata->mask_ofs) 69 70 #define DES_REG_LENGTH_N(x) (0x24 + ((x) * 0x04)) 71 72 #define DES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs) 73 #define DES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs) 74 #define DES_REG_IRQ_DATA_IN BIT(1) 75 #define DES_REG_IRQ_DATA_OUT BIT(2) 76 77 #define FLAGS_MODE_MASK 0x000f 78 #define FLAGS_ENCRYPT BIT(0) 79 #define FLAGS_CBC BIT(1) 80 #define FLAGS_INIT BIT(4) 81 #define FLAGS_BUSY BIT(6) 82 83 #define DEFAULT_AUTOSUSPEND_DELAY 1000 84 85 #define FLAGS_IN_DATA_ST_SHIFT 8 86 #define FLAGS_OUT_DATA_ST_SHIFT 10 87 88 struct omap_des_ctx { 89 struct omap_des_dev *dd; 90 91 int keylen; 92 u32 key[(3 * DES_KEY_SIZE) / sizeof(u32)]; 93 unsigned long flags; 94 }; 95 96 struct omap_des_reqctx { 97 unsigned long mode; 98 }; 99 100 #define OMAP_DES_QUEUE_LENGTH 1 101 #define OMAP_DES_CACHE_SIZE 0 102 103 struct omap_des_algs_info { 104 struct crypto_alg *algs_list; 105 unsigned int size; 106 unsigned int registered; 107 }; 108 109 struct omap_des_pdata { 110 struct omap_des_algs_info *algs_info; 111 unsigned int algs_info_size; 112 113 void (*trigger)(struct omap_des_dev *dd, int length); 114 115 u32 key_ofs; 116 u32 iv_ofs; 117 u32 ctrl_ofs; 118 u32 data_ofs; 119 u32 rev_ofs; 120 u32 mask_ofs; 121 u32 irq_enable_ofs; 122 u32 irq_status_ofs; 123 124 u32 dma_enable_in; 125 u32 dma_enable_out; 126 u32 dma_start; 127 128 u32 major_mask; 129 u32 major_shift; 130 u32 minor_mask; 131 u32 minor_shift; 132 }; 133 134 struct omap_des_dev { 135 struct list_head list; 136 unsigned long phys_base; 137 void __iomem *io_base; 138 struct omap_des_ctx *ctx; 139 struct device *dev; 140 unsigned long flags; 141 int err; 142 143 struct tasklet_struct done_task; 144 145 struct ablkcipher_request *req; 146 struct crypto_engine *engine; 147 /* 148 * total is used by PIO mode for book keeping so introduce 149 * variable total_save as need it to calc page_order 150 */ 151 size_t total; 152 size_t total_save; 153 154 struct scatterlist *in_sg; 155 struct scatterlist *out_sg; 156 157 /* Buffers for copying for unaligned cases */ 158 struct scatterlist in_sgl; 159 struct scatterlist out_sgl; 160 struct scatterlist *orig_out; 161 162 struct scatter_walk in_walk; 163 struct scatter_walk out_walk; 164 struct dma_chan *dma_lch_in; 165 struct dma_chan *dma_lch_out; 166 int in_sg_len; 167 int out_sg_len; 168 int pio_only; 169 const struct omap_des_pdata *pdata; 170 }; 171 172 /* keep registered devices data here */ 173 static LIST_HEAD(dev_list); 174 static DEFINE_SPINLOCK(list_lock); 175 176 #ifdef DEBUG 177 #define omap_des_read(dd, offset) \ 178 ({ \ 179 int _read_ret; \ 180 _read_ret = __raw_readl(dd->io_base + offset); \ 181 pr_err("omap_des_read(" #offset "=%#x)= %#x\n", \ 182 offset, _read_ret); \ 183 _read_ret; \ 184 }) 185 #else 186 static inline u32 omap_des_read(struct omap_des_dev *dd, u32 offset) 187 { 188 return __raw_readl(dd->io_base + offset); 189 } 190 #endif 191 192 #ifdef DEBUG 193 #define omap_des_write(dd, offset, value) \ 194 do { \ 195 pr_err("omap_des_write(" #offset "=%#x) value=%#x\n", \ 196 offset, value); \ 197 __raw_writel(value, dd->io_base + offset); \ 198 } while (0) 199 #else 200 static inline void omap_des_write(struct omap_des_dev *dd, u32 offset, 201 u32 value) 202 { 203 __raw_writel(value, dd->io_base + offset); 204 } 205 #endif 206 207 static inline void omap_des_write_mask(struct omap_des_dev *dd, u32 offset, 208 u32 value, u32 mask) 209 { 210 u32 val; 211 212 val = omap_des_read(dd, offset); 213 val &= ~mask; 214 val |= value; 215 omap_des_write(dd, offset, val); 216 } 217 218 static void omap_des_write_n(struct omap_des_dev *dd, u32 offset, 219 u32 *value, int count) 220 { 221 for (; count--; value++, offset += 4) 222 omap_des_write(dd, offset, *value); 223 } 224 225 static int omap_des_hw_init(struct omap_des_dev *dd) 226 { 227 int err; 228 229 /* 230 * clocks are enabled when request starts and disabled when finished. 231 * It may be long delays between requests. 232 * Device might go to off mode to save power. 233 */ 234 err = pm_runtime_get_sync(dd->dev); 235 if (err < 0) { 236 pm_runtime_put_noidle(dd->dev); 237 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err); 238 return err; 239 } 240 241 if (!(dd->flags & FLAGS_INIT)) { 242 dd->flags |= FLAGS_INIT; 243 dd->err = 0; 244 } 245 246 return 0; 247 } 248 249 static int omap_des_write_ctrl(struct omap_des_dev *dd) 250 { 251 unsigned int key32; 252 int i, err; 253 u32 val = 0, mask = 0; 254 255 err = omap_des_hw_init(dd); 256 if (err) 257 return err; 258 259 key32 = dd->ctx->keylen / sizeof(u32); 260 261 /* it seems a key should always be set even if it has not changed */ 262 for (i = 0; i < key32; i++) { 263 omap_des_write(dd, DES_REG_KEY(dd, i), 264 __le32_to_cpu(dd->ctx->key[i])); 265 } 266 267 if ((dd->flags & FLAGS_CBC) && dd->req->info) 268 omap_des_write_n(dd, DES_REG_IV(dd, 0), dd->req->info, 2); 269 270 if (dd->flags & FLAGS_CBC) 271 val |= DES_REG_CTRL_CBC; 272 if (dd->flags & FLAGS_ENCRYPT) 273 val |= DES_REG_CTRL_DIRECTION; 274 if (key32 == 6) 275 val |= DES_REG_CTRL_TDES; 276 277 mask |= DES_REG_CTRL_CBC | DES_REG_CTRL_DIRECTION | DES_REG_CTRL_TDES; 278 279 omap_des_write_mask(dd, DES_REG_CTRL(dd), val, mask); 280 281 return 0; 282 } 283 284 static void omap_des_dma_trigger_omap4(struct omap_des_dev *dd, int length) 285 { 286 u32 mask, val; 287 288 omap_des_write(dd, DES_REG_LENGTH_N(0), length); 289 290 val = dd->pdata->dma_start; 291 292 if (dd->dma_lch_out != NULL) 293 val |= dd->pdata->dma_enable_out; 294 if (dd->dma_lch_in != NULL) 295 val |= dd->pdata->dma_enable_in; 296 297 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | 298 dd->pdata->dma_start; 299 300 omap_des_write_mask(dd, DES_REG_MASK(dd), val, mask); 301 } 302 303 static void omap_des_dma_stop(struct omap_des_dev *dd) 304 { 305 u32 mask; 306 307 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | 308 dd->pdata->dma_start; 309 310 omap_des_write_mask(dd, DES_REG_MASK(dd), 0, mask); 311 } 312 313 static struct omap_des_dev *omap_des_find_dev(struct omap_des_ctx *ctx) 314 { 315 struct omap_des_dev *dd = NULL, *tmp; 316 317 spin_lock_bh(&list_lock); 318 if (!ctx->dd) { 319 list_for_each_entry(tmp, &dev_list, list) { 320 /* FIXME: take fist available des core */ 321 dd = tmp; 322 break; 323 } 324 ctx->dd = dd; 325 } else { 326 /* already found before */ 327 dd = ctx->dd; 328 } 329 spin_unlock_bh(&list_lock); 330 331 return dd; 332 } 333 334 static void omap_des_dma_out_callback(void *data) 335 { 336 struct omap_des_dev *dd = data; 337 338 /* dma_lch_out - completed */ 339 tasklet_schedule(&dd->done_task); 340 } 341 342 static int omap_des_dma_init(struct omap_des_dev *dd) 343 { 344 int err; 345 346 dd->dma_lch_out = NULL; 347 dd->dma_lch_in = NULL; 348 349 dd->dma_lch_in = dma_request_chan(dd->dev, "rx"); 350 if (IS_ERR(dd->dma_lch_in)) { 351 dev_err(dd->dev, "Unable to request in DMA channel\n"); 352 return PTR_ERR(dd->dma_lch_in); 353 } 354 355 dd->dma_lch_out = dma_request_chan(dd->dev, "tx"); 356 if (IS_ERR(dd->dma_lch_out)) { 357 dev_err(dd->dev, "Unable to request out DMA channel\n"); 358 err = PTR_ERR(dd->dma_lch_out); 359 goto err_dma_out; 360 } 361 362 return 0; 363 364 err_dma_out: 365 dma_release_channel(dd->dma_lch_in); 366 367 return err; 368 } 369 370 static void omap_des_dma_cleanup(struct omap_des_dev *dd) 371 { 372 if (dd->pio_only) 373 return; 374 375 dma_release_channel(dd->dma_lch_out); 376 dma_release_channel(dd->dma_lch_in); 377 } 378 379 static int omap_des_crypt_dma(struct crypto_tfm *tfm, 380 struct scatterlist *in_sg, struct scatterlist *out_sg, 381 int in_sg_len, int out_sg_len) 382 { 383 struct omap_des_ctx *ctx = crypto_tfm_ctx(tfm); 384 struct omap_des_dev *dd = ctx->dd; 385 struct dma_async_tx_descriptor *tx_in, *tx_out; 386 struct dma_slave_config cfg; 387 int ret; 388 389 if (dd->pio_only) { 390 scatterwalk_start(&dd->in_walk, dd->in_sg); 391 scatterwalk_start(&dd->out_walk, dd->out_sg); 392 393 /* Enable DATAIN interrupt and let it take 394 care of the rest */ 395 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2); 396 return 0; 397 } 398 399 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE); 400 401 memset(&cfg, 0, sizeof(cfg)); 402 403 cfg.src_addr = dd->phys_base + DES_REG_DATA_N(dd, 0); 404 cfg.dst_addr = dd->phys_base + DES_REG_DATA_N(dd, 0); 405 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 406 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 407 cfg.src_maxburst = DST_MAXBURST; 408 cfg.dst_maxburst = DST_MAXBURST; 409 410 /* IN */ 411 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg); 412 if (ret) { 413 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n", 414 ret); 415 return ret; 416 } 417 418 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len, 419 DMA_MEM_TO_DEV, 420 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 421 if (!tx_in) { 422 dev_err(dd->dev, "IN prep_slave_sg() failed\n"); 423 return -EINVAL; 424 } 425 426 /* No callback necessary */ 427 tx_in->callback_param = dd; 428 429 /* OUT */ 430 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg); 431 if (ret) { 432 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n", 433 ret); 434 return ret; 435 } 436 437 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len, 438 DMA_DEV_TO_MEM, 439 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 440 if (!tx_out) { 441 dev_err(dd->dev, "OUT prep_slave_sg() failed\n"); 442 return -EINVAL; 443 } 444 445 tx_out->callback = omap_des_dma_out_callback; 446 tx_out->callback_param = dd; 447 448 dmaengine_submit(tx_in); 449 dmaengine_submit(tx_out); 450 451 dma_async_issue_pending(dd->dma_lch_in); 452 dma_async_issue_pending(dd->dma_lch_out); 453 454 /* start DMA */ 455 dd->pdata->trigger(dd, dd->total); 456 457 return 0; 458 } 459 460 static int omap_des_crypt_dma_start(struct omap_des_dev *dd) 461 { 462 struct crypto_tfm *tfm = crypto_ablkcipher_tfm( 463 crypto_ablkcipher_reqtfm(dd->req)); 464 int err; 465 466 pr_debug("total: %d\n", dd->total); 467 468 if (!dd->pio_only) { 469 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len, 470 DMA_TO_DEVICE); 471 if (!err) { 472 dev_err(dd->dev, "dma_map_sg() error\n"); 473 return -EINVAL; 474 } 475 476 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len, 477 DMA_FROM_DEVICE); 478 if (!err) { 479 dev_err(dd->dev, "dma_map_sg() error\n"); 480 return -EINVAL; 481 } 482 } 483 484 err = omap_des_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len, 485 dd->out_sg_len); 486 if (err && !dd->pio_only) { 487 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 488 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, 489 DMA_FROM_DEVICE); 490 } 491 492 return err; 493 } 494 495 static void omap_des_finish_req(struct omap_des_dev *dd, int err) 496 { 497 struct ablkcipher_request *req = dd->req; 498 499 pr_debug("err: %d\n", err); 500 501 crypto_finalize_cipher_request(dd->engine, req, err); 502 503 pm_runtime_mark_last_busy(dd->dev); 504 pm_runtime_put_autosuspend(dd->dev); 505 } 506 507 static int omap_des_crypt_dma_stop(struct omap_des_dev *dd) 508 { 509 pr_debug("total: %d\n", dd->total); 510 511 omap_des_dma_stop(dd); 512 513 dmaengine_terminate_all(dd->dma_lch_in); 514 dmaengine_terminate_all(dd->dma_lch_out); 515 516 return 0; 517 } 518 519 static int omap_des_handle_queue(struct omap_des_dev *dd, 520 struct ablkcipher_request *req) 521 { 522 if (req) 523 return crypto_transfer_cipher_request_to_engine(dd->engine, req); 524 525 return 0; 526 } 527 528 static int omap_des_prepare_req(struct crypto_engine *engine, 529 struct ablkcipher_request *req) 530 { 531 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx( 532 crypto_ablkcipher_reqtfm(req)); 533 struct omap_des_dev *dd = omap_des_find_dev(ctx); 534 struct omap_des_reqctx *rctx; 535 int ret; 536 u16 flags; 537 538 if (!dd) 539 return -ENODEV; 540 541 /* assign new request to device */ 542 dd->req = req; 543 dd->total = req->nbytes; 544 dd->total_save = req->nbytes; 545 dd->in_sg = req->src; 546 dd->out_sg = req->dst; 547 dd->orig_out = req->dst; 548 549 flags = OMAP_CRYPTO_COPY_DATA; 550 if (req->src == req->dst) 551 flags |= OMAP_CRYPTO_FORCE_COPY; 552 553 ret = omap_crypto_align_sg(&dd->in_sg, dd->total, DES_BLOCK_SIZE, 554 &dd->in_sgl, flags, 555 FLAGS_IN_DATA_ST_SHIFT, &dd->flags); 556 if (ret) 557 return ret; 558 559 ret = omap_crypto_align_sg(&dd->out_sg, dd->total, DES_BLOCK_SIZE, 560 &dd->out_sgl, 0, 561 FLAGS_OUT_DATA_ST_SHIFT, &dd->flags); 562 if (ret) 563 return ret; 564 565 dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total); 566 if (dd->in_sg_len < 0) 567 return dd->in_sg_len; 568 569 dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total); 570 if (dd->out_sg_len < 0) 571 return dd->out_sg_len; 572 573 rctx = ablkcipher_request_ctx(req); 574 ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req)); 575 rctx->mode &= FLAGS_MODE_MASK; 576 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode; 577 578 dd->ctx = ctx; 579 ctx->dd = dd; 580 581 return omap_des_write_ctrl(dd); 582 } 583 584 static int omap_des_crypt_req(struct crypto_engine *engine, 585 struct ablkcipher_request *req) 586 { 587 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx( 588 crypto_ablkcipher_reqtfm(req)); 589 struct omap_des_dev *dd = omap_des_find_dev(ctx); 590 591 if (!dd) 592 return -ENODEV; 593 594 return omap_des_crypt_dma_start(dd); 595 } 596 597 static void omap_des_done_task(unsigned long data) 598 { 599 struct omap_des_dev *dd = (struct omap_des_dev *)data; 600 601 pr_debug("enter done_task\n"); 602 603 if (!dd->pio_only) { 604 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len, 605 DMA_FROM_DEVICE); 606 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 607 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, 608 DMA_FROM_DEVICE); 609 omap_des_crypt_dma_stop(dd); 610 } 611 612 omap_crypto_cleanup(&dd->in_sgl, NULL, 0, dd->total_save, 613 FLAGS_IN_DATA_ST_SHIFT, dd->flags); 614 615 omap_crypto_cleanup(&dd->out_sgl, dd->orig_out, 0, dd->total_save, 616 FLAGS_OUT_DATA_ST_SHIFT, dd->flags); 617 618 omap_des_finish_req(dd, 0); 619 620 pr_debug("exit\n"); 621 } 622 623 static int omap_des_crypt(struct ablkcipher_request *req, unsigned long mode) 624 { 625 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx( 626 crypto_ablkcipher_reqtfm(req)); 627 struct omap_des_reqctx *rctx = ablkcipher_request_ctx(req); 628 struct omap_des_dev *dd; 629 630 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes, 631 !!(mode & FLAGS_ENCRYPT), 632 !!(mode & FLAGS_CBC)); 633 634 if (!IS_ALIGNED(req->nbytes, DES_BLOCK_SIZE)) { 635 pr_err("request size is not exact amount of DES blocks\n"); 636 return -EINVAL; 637 } 638 639 dd = omap_des_find_dev(ctx); 640 if (!dd) 641 return -ENODEV; 642 643 rctx->mode = mode; 644 645 return omap_des_handle_queue(dd, req); 646 } 647 648 /* ********************** ALG API ************************************ */ 649 650 static int omap_des_setkey(struct crypto_ablkcipher *cipher, const u8 *key, 651 unsigned int keylen) 652 { 653 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(cipher); 654 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher); 655 656 if (keylen != DES_KEY_SIZE && keylen != (3*DES_KEY_SIZE)) 657 return -EINVAL; 658 659 pr_debug("enter, keylen: %d\n", keylen); 660 661 /* Do we need to test against weak key? */ 662 if (tfm->crt_flags & CRYPTO_TFM_REQ_WEAK_KEY) { 663 u32 tmp[DES_EXPKEY_WORDS]; 664 int ret = des_ekey(tmp, key); 665 666 if (!ret) { 667 tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY; 668 return -EINVAL; 669 } 670 } 671 672 memcpy(ctx->key, key, keylen); 673 ctx->keylen = keylen; 674 675 return 0; 676 } 677 678 static int omap_des_ecb_encrypt(struct ablkcipher_request *req) 679 { 680 return omap_des_crypt(req, FLAGS_ENCRYPT); 681 } 682 683 static int omap_des_ecb_decrypt(struct ablkcipher_request *req) 684 { 685 return omap_des_crypt(req, 0); 686 } 687 688 static int omap_des_cbc_encrypt(struct ablkcipher_request *req) 689 { 690 return omap_des_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC); 691 } 692 693 static int omap_des_cbc_decrypt(struct ablkcipher_request *req) 694 { 695 return omap_des_crypt(req, FLAGS_CBC); 696 } 697 698 static int omap_des_cra_init(struct crypto_tfm *tfm) 699 { 700 pr_debug("enter\n"); 701 702 tfm->crt_ablkcipher.reqsize = sizeof(struct omap_des_reqctx); 703 704 return 0; 705 } 706 707 static void omap_des_cra_exit(struct crypto_tfm *tfm) 708 { 709 pr_debug("enter\n"); 710 } 711 712 /* ********************** ALGS ************************************ */ 713 714 static struct crypto_alg algs_ecb_cbc[] = { 715 { 716 .cra_name = "ecb(des)", 717 .cra_driver_name = "ecb-des-omap", 718 .cra_priority = 100, 719 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 720 CRYPTO_ALG_KERN_DRIVER_ONLY | 721 CRYPTO_ALG_ASYNC, 722 .cra_blocksize = DES_BLOCK_SIZE, 723 .cra_ctxsize = sizeof(struct omap_des_ctx), 724 .cra_alignmask = 0, 725 .cra_type = &crypto_ablkcipher_type, 726 .cra_module = THIS_MODULE, 727 .cra_init = omap_des_cra_init, 728 .cra_exit = omap_des_cra_exit, 729 .cra_u.ablkcipher = { 730 .min_keysize = DES_KEY_SIZE, 731 .max_keysize = DES_KEY_SIZE, 732 .setkey = omap_des_setkey, 733 .encrypt = omap_des_ecb_encrypt, 734 .decrypt = omap_des_ecb_decrypt, 735 } 736 }, 737 { 738 .cra_name = "cbc(des)", 739 .cra_driver_name = "cbc-des-omap", 740 .cra_priority = 100, 741 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 742 CRYPTO_ALG_KERN_DRIVER_ONLY | 743 CRYPTO_ALG_ASYNC, 744 .cra_blocksize = DES_BLOCK_SIZE, 745 .cra_ctxsize = sizeof(struct omap_des_ctx), 746 .cra_alignmask = 0, 747 .cra_type = &crypto_ablkcipher_type, 748 .cra_module = THIS_MODULE, 749 .cra_init = omap_des_cra_init, 750 .cra_exit = omap_des_cra_exit, 751 .cra_u.ablkcipher = { 752 .min_keysize = DES_KEY_SIZE, 753 .max_keysize = DES_KEY_SIZE, 754 .ivsize = DES_BLOCK_SIZE, 755 .setkey = omap_des_setkey, 756 .encrypt = omap_des_cbc_encrypt, 757 .decrypt = omap_des_cbc_decrypt, 758 } 759 }, 760 { 761 .cra_name = "ecb(des3_ede)", 762 .cra_driver_name = "ecb-des3-omap", 763 .cra_priority = 100, 764 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 765 CRYPTO_ALG_KERN_DRIVER_ONLY | 766 CRYPTO_ALG_ASYNC, 767 .cra_blocksize = DES_BLOCK_SIZE, 768 .cra_ctxsize = sizeof(struct omap_des_ctx), 769 .cra_alignmask = 0, 770 .cra_type = &crypto_ablkcipher_type, 771 .cra_module = THIS_MODULE, 772 .cra_init = omap_des_cra_init, 773 .cra_exit = omap_des_cra_exit, 774 .cra_u.ablkcipher = { 775 .min_keysize = 3*DES_KEY_SIZE, 776 .max_keysize = 3*DES_KEY_SIZE, 777 .setkey = omap_des_setkey, 778 .encrypt = omap_des_ecb_encrypt, 779 .decrypt = omap_des_ecb_decrypt, 780 } 781 }, 782 { 783 .cra_name = "cbc(des3_ede)", 784 .cra_driver_name = "cbc-des3-omap", 785 .cra_priority = 100, 786 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 787 CRYPTO_ALG_KERN_DRIVER_ONLY | 788 CRYPTO_ALG_ASYNC, 789 .cra_blocksize = DES_BLOCK_SIZE, 790 .cra_ctxsize = sizeof(struct omap_des_ctx), 791 .cra_alignmask = 0, 792 .cra_type = &crypto_ablkcipher_type, 793 .cra_module = THIS_MODULE, 794 .cra_init = omap_des_cra_init, 795 .cra_exit = omap_des_cra_exit, 796 .cra_u.ablkcipher = { 797 .min_keysize = 3*DES_KEY_SIZE, 798 .max_keysize = 3*DES_KEY_SIZE, 799 .ivsize = DES_BLOCK_SIZE, 800 .setkey = omap_des_setkey, 801 .encrypt = omap_des_cbc_encrypt, 802 .decrypt = omap_des_cbc_decrypt, 803 } 804 } 805 }; 806 807 static struct omap_des_algs_info omap_des_algs_info_ecb_cbc[] = { 808 { 809 .algs_list = algs_ecb_cbc, 810 .size = ARRAY_SIZE(algs_ecb_cbc), 811 }, 812 }; 813 814 #ifdef CONFIG_OF 815 static const struct omap_des_pdata omap_des_pdata_omap4 = { 816 .algs_info = omap_des_algs_info_ecb_cbc, 817 .algs_info_size = ARRAY_SIZE(omap_des_algs_info_ecb_cbc), 818 .trigger = omap_des_dma_trigger_omap4, 819 .key_ofs = 0x14, 820 .iv_ofs = 0x18, 821 .ctrl_ofs = 0x20, 822 .data_ofs = 0x28, 823 .rev_ofs = 0x30, 824 .mask_ofs = 0x34, 825 .irq_status_ofs = 0x3c, 826 .irq_enable_ofs = 0x40, 827 .dma_enable_in = BIT(5), 828 .dma_enable_out = BIT(6), 829 .major_mask = 0x0700, 830 .major_shift = 8, 831 .minor_mask = 0x003f, 832 .minor_shift = 0, 833 }; 834 835 static irqreturn_t omap_des_irq(int irq, void *dev_id) 836 { 837 struct omap_des_dev *dd = dev_id; 838 u32 status, i; 839 u32 *src, *dst; 840 841 status = omap_des_read(dd, DES_REG_IRQ_STATUS(dd)); 842 if (status & DES_REG_IRQ_DATA_IN) { 843 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0); 844 845 BUG_ON(!dd->in_sg); 846 847 BUG_ON(_calc_walked(in) > dd->in_sg->length); 848 849 src = sg_virt(dd->in_sg) + _calc_walked(in); 850 851 for (i = 0; i < DES_BLOCK_WORDS; i++) { 852 omap_des_write(dd, DES_REG_DATA_N(dd, i), *src); 853 854 scatterwalk_advance(&dd->in_walk, 4); 855 if (dd->in_sg->length == _calc_walked(in)) { 856 dd->in_sg = sg_next(dd->in_sg); 857 if (dd->in_sg) { 858 scatterwalk_start(&dd->in_walk, 859 dd->in_sg); 860 src = sg_virt(dd->in_sg) + 861 _calc_walked(in); 862 } 863 } else { 864 src++; 865 } 866 } 867 868 /* Clear IRQ status */ 869 status &= ~DES_REG_IRQ_DATA_IN; 870 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status); 871 872 /* Enable DATA_OUT interrupt */ 873 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x4); 874 875 } else if (status & DES_REG_IRQ_DATA_OUT) { 876 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0); 877 878 BUG_ON(!dd->out_sg); 879 880 BUG_ON(_calc_walked(out) > dd->out_sg->length); 881 882 dst = sg_virt(dd->out_sg) + _calc_walked(out); 883 884 for (i = 0; i < DES_BLOCK_WORDS; i++) { 885 *dst = omap_des_read(dd, DES_REG_DATA_N(dd, i)); 886 scatterwalk_advance(&dd->out_walk, 4); 887 if (dd->out_sg->length == _calc_walked(out)) { 888 dd->out_sg = sg_next(dd->out_sg); 889 if (dd->out_sg) { 890 scatterwalk_start(&dd->out_walk, 891 dd->out_sg); 892 dst = sg_virt(dd->out_sg) + 893 _calc_walked(out); 894 } 895 } else { 896 dst++; 897 } 898 } 899 900 BUG_ON(dd->total < DES_BLOCK_SIZE); 901 902 dd->total -= DES_BLOCK_SIZE; 903 904 /* Clear IRQ status */ 905 status &= ~DES_REG_IRQ_DATA_OUT; 906 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status); 907 908 if (!dd->total) 909 /* All bytes read! */ 910 tasklet_schedule(&dd->done_task); 911 else 912 /* Enable DATA_IN interrupt for next block */ 913 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2); 914 } 915 916 return IRQ_HANDLED; 917 } 918 919 static const struct of_device_id omap_des_of_match[] = { 920 { 921 .compatible = "ti,omap4-des", 922 .data = &omap_des_pdata_omap4, 923 }, 924 {}, 925 }; 926 MODULE_DEVICE_TABLE(of, omap_des_of_match); 927 928 static int omap_des_get_of(struct omap_des_dev *dd, 929 struct platform_device *pdev) 930 { 931 932 dd->pdata = of_device_get_match_data(&pdev->dev); 933 if (!dd->pdata) { 934 dev_err(&pdev->dev, "no compatible OF match\n"); 935 return -EINVAL; 936 } 937 938 return 0; 939 } 940 #else 941 static int omap_des_get_of(struct omap_des_dev *dd, 942 struct device *dev) 943 { 944 return -EINVAL; 945 } 946 #endif 947 948 static int omap_des_get_pdev(struct omap_des_dev *dd, 949 struct platform_device *pdev) 950 { 951 /* non-DT devices get pdata from pdev */ 952 dd->pdata = pdev->dev.platform_data; 953 954 return 0; 955 } 956 957 static int omap_des_probe(struct platform_device *pdev) 958 { 959 struct device *dev = &pdev->dev; 960 struct omap_des_dev *dd; 961 struct crypto_alg *algp; 962 struct resource *res; 963 int err = -ENOMEM, i, j, irq = -1; 964 u32 reg; 965 966 dd = devm_kzalloc(dev, sizeof(struct omap_des_dev), GFP_KERNEL); 967 if (dd == NULL) { 968 dev_err(dev, "unable to alloc data struct.\n"); 969 goto err_data; 970 } 971 dd->dev = dev; 972 platform_set_drvdata(pdev, dd); 973 974 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 975 if (!res) { 976 dev_err(dev, "no MEM resource info\n"); 977 goto err_res; 978 } 979 980 err = (dev->of_node) ? omap_des_get_of(dd, pdev) : 981 omap_des_get_pdev(dd, pdev); 982 if (err) 983 goto err_res; 984 985 dd->io_base = devm_ioremap_resource(dev, res); 986 if (IS_ERR(dd->io_base)) { 987 err = PTR_ERR(dd->io_base); 988 goto err_res; 989 } 990 dd->phys_base = res->start; 991 992 pm_runtime_use_autosuspend(dev); 993 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY); 994 995 pm_runtime_enable(dev); 996 err = pm_runtime_get_sync(dev); 997 if (err < 0) { 998 pm_runtime_put_noidle(dev); 999 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err); 1000 goto err_get; 1001 } 1002 1003 omap_des_dma_stop(dd); 1004 1005 reg = omap_des_read(dd, DES_REG_REV(dd)); 1006 1007 pm_runtime_put_sync(dev); 1008 1009 dev_info(dev, "OMAP DES hw accel rev: %u.%u\n", 1010 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift, 1011 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift); 1012 1013 tasklet_init(&dd->done_task, omap_des_done_task, (unsigned long)dd); 1014 1015 err = omap_des_dma_init(dd); 1016 if (err == -EPROBE_DEFER) { 1017 goto err_irq; 1018 } else if (err && DES_REG_IRQ_STATUS(dd) && DES_REG_IRQ_ENABLE(dd)) { 1019 dd->pio_only = 1; 1020 1021 irq = platform_get_irq(pdev, 0); 1022 if (irq < 0) { 1023 dev_err(dev, "can't get IRQ resource: %d\n", irq); 1024 err = irq; 1025 goto err_irq; 1026 } 1027 1028 err = devm_request_irq(dev, irq, omap_des_irq, 0, 1029 dev_name(dev), dd); 1030 if (err) { 1031 dev_err(dev, "Unable to grab omap-des IRQ\n"); 1032 goto err_irq; 1033 } 1034 } 1035 1036 1037 INIT_LIST_HEAD(&dd->list); 1038 spin_lock(&list_lock); 1039 list_add_tail(&dd->list, &dev_list); 1040 spin_unlock(&list_lock); 1041 1042 /* Initialize des crypto engine */ 1043 dd->engine = crypto_engine_alloc_init(dev, 1); 1044 if (!dd->engine) { 1045 err = -ENOMEM; 1046 goto err_engine; 1047 } 1048 1049 dd->engine->prepare_cipher_request = omap_des_prepare_req; 1050 dd->engine->cipher_one_request = omap_des_crypt_req; 1051 err = crypto_engine_start(dd->engine); 1052 if (err) 1053 goto err_engine; 1054 1055 for (i = 0; i < dd->pdata->algs_info_size; i++) { 1056 for (j = 0; j < dd->pdata->algs_info[i].size; j++) { 1057 algp = &dd->pdata->algs_info[i].algs_list[j]; 1058 1059 pr_debug("reg alg: %s\n", algp->cra_name); 1060 INIT_LIST_HEAD(&algp->cra_list); 1061 1062 err = crypto_register_alg(algp); 1063 if (err) 1064 goto err_algs; 1065 1066 dd->pdata->algs_info[i].registered++; 1067 } 1068 } 1069 1070 return 0; 1071 1072 err_algs: 1073 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1074 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1075 crypto_unregister_alg( 1076 &dd->pdata->algs_info[i].algs_list[j]); 1077 1078 err_engine: 1079 if (dd->engine) 1080 crypto_engine_exit(dd->engine); 1081 1082 omap_des_dma_cleanup(dd); 1083 err_irq: 1084 tasklet_kill(&dd->done_task); 1085 err_get: 1086 pm_runtime_disable(dev); 1087 err_res: 1088 dd = NULL; 1089 err_data: 1090 dev_err(dev, "initialization failed.\n"); 1091 return err; 1092 } 1093 1094 static int omap_des_remove(struct platform_device *pdev) 1095 { 1096 struct omap_des_dev *dd = platform_get_drvdata(pdev); 1097 int i, j; 1098 1099 if (!dd) 1100 return -ENODEV; 1101 1102 spin_lock(&list_lock); 1103 list_del(&dd->list); 1104 spin_unlock(&list_lock); 1105 1106 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) 1107 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) 1108 crypto_unregister_alg( 1109 &dd->pdata->algs_info[i].algs_list[j]); 1110 1111 tasklet_kill(&dd->done_task); 1112 omap_des_dma_cleanup(dd); 1113 pm_runtime_disable(dd->dev); 1114 dd = NULL; 1115 1116 return 0; 1117 } 1118 1119 #ifdef CONFIG_PM_SLEEP 1120 static int omap_des_suspend(struct device *dev) 1121 { 1122 pm_runtime_put_sync(dev); 1123 return 0; 1124 } 1125 1126 static int omap_des_resume(struct device *dev) 1127 { 1128 int err; 1129 1130 err = pm_runtime_get_sync(dev); 1131 if (err < 0) { 1132 pm_runtime_put_noidle(dev); 1133 dev_err(dev, "%s: failed to get_sync(%d)\n", __func__, err); 1134 return err; 1135 } 1136 return 0; 1137 } 1138 #endif 1139 1140 static SIMPLE_DEV_PM_OPS(omap_des_pm_ops, omap_des_suspend, omap_des_resume); 1141 1142 static struct platform_driver omap_des_driver = { 1143 .probe = omap_des_probe, 1144 .remove = omap_des_remove, 1145 .driver = { 1146 .name = "omap-des", 1147 .pm = &omap_des_pm_ops, 1148 .of_match_table = of_match_ptr(omap_des_of_match), 1149 }, 1150 }; 1151 1152 module_platform_driver(omap_des_driver); 1153 1154 MODULE_DESCRIPTION("OMAP DES hw acceleration support."); 1155 MODULE_LICENSE("GPL v2"); 1156 MODULE_AUTHOR("Joel Fernandes <joelf@ti.com>"); 1157