1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Cryptographic API. 4 * 5 * Support for OMAP AES HW acceleration. 6 * 7 * Copyright (c) 2010 Nokia Corporation 8 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> 9 * Copyright (c) 2011 Texas Instruments Incorporated 10 */ 11 12 #define pr_fmt(fmt) "%20s: " fmt, __func__ 13 #define prn(num) pr_debug(#num "=%d\n", num) 14 #define prx(num) pr_debug(#num "=%x\n", num) 15 16 #include <crypto/aes.h> 17 #include <crypto/gcm.h> 18 #include <crypto/internal/aead.h> 19 #include <crypto/internal/engine.h> 20 #include <crypto/internal/skcipher.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/dmaengine.h> 23 #include <linux/err.h> 24 #include <linux/init.h> 25 #include <linux/interrupt.h> 26 #include <linux/io.h> 27 #include <linux/kernel.h> 28 #include <linux/module.h> 29 #include <linux/of.h> 30 #include <linux/of_address.h> 31 #include <linux/platform_device.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/scatterlist.h> 34 #include <linux/string.h> 35 #include <linux/sysfs.h> 36 #include <linux/workqueue.h> 37 38 #include "omap-crypto.h" 39 #include "omap-aes.h" 40 41 /* keep registered devices data here */ 42 static LIST_HEAD(dev_list); 43 static DEFINE_SPINLOCK(list_lock); 44 45 static int aes_fallback_sz = 200; 46 47 #ifdef DEBUG 48 #define omap_aes_read(dd, offset) \ 49 ({ \ 50 int _read_ret; \ 51 _read_ret = __raw_readl(dd->io_base + offset); \ 52 pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n", \ 53 offset, _read_ret); \ 54 _read_ret; \ 55 }) 56 #else 57 inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset) 58 { 59 return __raw_readl(dd->io_base + offset); 60 } 61 #endif 62 63 #ifdef DEBUG 64 #define omap_aes_write(dd, offset, value) \ 65 do { \ 66 pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \ 67 offset, value); \ 68 __raw_writel(value, dd->io_base + offset); \ 69 } while (0) 70 #else 71 inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset, 72 u32 value) 73 { 74 __raw_writel(value, dd->io_base + offset); 75 } 76 #endif 77 78 static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset, 79 u32 value, u32 mask) 80 { 81 u32 val; 82 83 val = omap_aes_read(dd, offset); 84 val &= ~mask; 85 val |= value; 86 omap_aes_write(dd, offset, val); 87 } 88 89 static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset, 90 u32 *value, int count) 91 { 92 for (; count--; value++, offset += 4) 93 omap_aes_write(dd, offset, *value); 94 } 95 96 static int omap_aes_hw_init(struct omap_aes_dev *dd) 97 { 98 int err; 99 100 if (!(dd->flags & FLAGS_INIT)) { 101 dd->flags |= FLAGS_INIT; 102 dd->err = 0; 103 } 104 105 err = pm_runtime_resume_and_get(dd->dev); 106 if (err < 0) { 107 dev_err(dd->dev, "failed to get sync: %d\n", err); 108 return err; 109 } 110 111 return 0; 112 } 113 114 void omap_aes_clear_copy_flags(struct omap_aes_dev *dd) 115 { 116 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_IN_DATA_ST_SHIFT); 117 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_OUT_DATA_ST_SHIFT); 118 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_ASSOC_DATA_ST_SHIFT); 119 } 120 121 int omap_aes_write_ctrl(struct omap_aes_dev *dd) 122 { 123 struct omap_aes_reqctx *rctx; 124 unsigned int key32; 125 int i, err; 126 u32 val; 127 128 err = omap_aes_hw_init(dd); 129 if (err) 130 return err; 131 132 key32 = dd->ctx->keylen / sizeof(u32); 133 134 /* RESET the key as previous HASH keys should not get affected*/ 135 if (dd->flags & FLAGS_GCM) 136 for (i = 0; i < 0x40; i = i + 4) 137 omap_aes_write(dd, i, 0x0); 138 139 for (i = 0; i < key32; i++) { 140 omap_aes_write(dd, AES_REG_KEY(dd, i), 141 (__force u32)cpu_to_le32(dd->ctx->key[i])); 142 } 143 144 if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->iv) 145 omap_aes_write_n(dd, AES_REG_IV(dd, 0), (void *)dd->req->iv, 4); 146 147 if ((dd->flags & (FLAGS_GCM)) && dd->aead_req->iv) { 148 rctx = aead_request_ctx(dd->aead_req); 149 omap_aes_write_n(dd, AES_REG_IV(dd, 0), (u32 *)rctx->iv, 4); 150 } 151 152 val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3); 153 if (dd->flags & FLAGS_CBC) 154 val |= AES_REG_CTRL_CBC; 155 156 if (dd->flags & (FLAGS_CTR | FLAGS_GCM)) 157 val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128; 158 159 if (dd->flags & FLAGS_GCM) 160 val |= AES_REG_CTRL_GCM; 161 162 if (dd->flags & FLAGS_ENCRYPT) 163 val |= AES_REG_CTRL_DIRECTION; 164 165 omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, AES_REG_CTRL_MASK); 166 167 return 0; 168 } 169 170 static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length) 171 { 172 u32 mask, val; 173 174 val = dd->pdata->dma_start; 175 176 if (dd->dma_lch_out != NULL) 177 val |= dd->pdata->dma_enable_out; 178 if (dd->dma_lch_in != NULL) 179 val |= dd->pdata->dma_enable_in; 180 181 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | 182 dd->pdata->dma_start; 183 184 omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask); 185 186 } 187 188 static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length) 189 { 190 omap_aes_write(dd, AES_REG_LENGTH_N(0), length); 191 omap_aes_write(dd, AES_REG_LENGTH_N(1), 0); 192 if (dd->flags & FLAGS_GCM) 193 omap_aes_write(dd, AES_REG_A_LEN, dd->assoc_len); 194 195 omap_aes_dma_trigger_omap2(dd, length); 196 } 197 198 static void omap_aes_dma_stop(struct omap_aes_dev *dd) 199 { 200 u32 mask; 201 202 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | 203 dd->pdata->dma_start; 204 205 omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask); 206 } 207 208 struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_reqctx *rctx) 209 { 210 struct omap_aes_dev *dd; 211 212 spin_lock_bh(&list_lock); 213 dd = list_first_entry(&dev_list, struct omap_aes_dev, list); 214 list_move_tail(&dd->list, &dev_list); 215 rctx->dd = dd; 216 spin_unlock_bh(&list_lock); 217 218 return dd; 219 } 220 221 static void omap_aes_dma_out_callback(void *data) 222 { 223 struct omap_aes_dev *dd = data; 224 225 /* dma_lch_out - completed */ 226 queue_work(system_bh_wq, &dd->done_task); 227 } 228 229 static int omap_aes_dma_init(struct omap_aes_dev *dd) 230 { 231 int err; 232 233 dd->dma_lch_out = NULL; 234 dd->dma_lch_in = NULL; 235 236 dd->dma_lch_in = dma_request_chan(dd->dev, "rx"); 237 if (IS_ERR(dd->dma_lch_in)) { 238 dev_err(dd->dev, "Unable to request in DMA channel\n"); 239 return PTR_ERR(dd->dma_lch_in); 240 } 241 242 dd->dma_lch_out = dma_request_chan(dd->dev, "tx"); 243 if (IS_ERR(dd->dma_lch_out)) { 244 dev_err(dd->dev, "Unable to request out DMA channel\n"); 245 err = PTR_ERR(dd->dma_lch_out); 246 goto err_dma_out; 247 } 248 249 return 0; 250 251 err_dma_out: 252 dma_release_channel(dd->dma_lch_in); 253 254 return err; 255 } 256 257 static void omap_aes_dma_cleanup(struct omap_aes_dev *dd) 258 { 259 if (dd->pio_only) 260 return; 261 262 dma_release_channel(dd->dma_lch_out); 263 dma_release_channel(dd->dma_lch_in); 264 } 265 266 static int omap_aes_crypt_dma(struct omap_aes_dev *dd, 267 struct scatterlist *in_sg, 268 struct scatterlist *out_sg, 269 int in_sg_len, int out_sg_len) 270 { 271 struct dma_async_tx_descriptor *tx_in, *tx_out = NULL, *cb_desc; 272 struct dma_slave_config cfg; 273 int ret; 274 275 if (dd->pio_only) { 276 dd->in_sg_offset = 0; 277 if (out_sg_len) 278 dd->out_sg_offset = 0; 279 280 /* Enable DATAIN interrupt and let it take 281 care of the rest */ 282 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2); 283 return 0; 284 } 285 286 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE); 287 288 memset(&cfg, 0, sizeof(cfg)); 289 290 cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0); 291 cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0); 292 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 293 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 294 cfg.src_maxburst = DST_MAXBURST; 295 cfg.dst_maxburst = DST_MAXBURST; 296 297 /* IN */ 298 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg); 299 if (ret) { 300 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n", 301 ret); 302 return ret; 303 } 304 305 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len, 306 DMA_MEM_TO_DEV, 307 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 308 if (!tx_in) { 309 dev_err(dd->dev, "IN prep_slave_sg() failed\n"); 310 return -EINVAL; 311 } 312 313 /* No callback necessary */ 314 tx_in->callback_param = dd; 315 tx_in->callback = NULL; 316 317 /* OUT */ 318 if (out_sg_len) { 319 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg); 320 if (ret) { 321 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n", 322 ret); 323 return ret; 324 } 325 326 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, 327 out_sg_len, 328 DMA_DEV_TO_MEM, 329 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 330 if (!tx_out) { 331 dev_err(dd->dev, "OUT prep_slave_sg() failed\n"); 332 return -EINVAL; 333 } 334 335 cb_desc = tx_out; 336 } else { 337 cb_desc = tx_in; 338 } 339 340 if (dd->flags & FLAGS_GCM) 341 cb_desc->callback = omap_aes_gcm_dma_out_callback; 342 else 343 cb_desc->callback = omap_aes_dma_out_callback; 344 cb_desc->callback_param = dd; 345 346 347 dmaengine_submit(tx_in); 348 if (tx_out) 349 dmaengine_submit(tx_out); 350 351 dma_async_issue_pending(dd->dma_lch_in); 352 if (out_sg_len) 353 dma_async_issue_pending(dd->dma_lch_out); 354 355 /* start DMA */ 356 dd->pdata->trigger(dd, dd->total); 357 358 return 0; 359 } 360 361 int omap_aes_crypt_dma_start(struct omap_aes_dev *dd) 362 { 363 int err; 364 365 pr_debug("total: %zu\n", dd->total); 366 367 if (!dd->pio_only) { 368 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len, 369 DMA_TO_DEVICE); 370 if (!err) { 371 dev_err(dd->dev, "dma_map_sg() error\n"); 372 return -EINVAL; 373 } 374 375 if (dd->out_sg_len) { 376 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len, 377 DMA_FROM_DEVICE); 378 if (!err) { 379 dev_err(dd->dev, "dma_map_sg() error\n"); 380 return -EINVAL; 381 } 382 } 383 } 384 385 err = omap_aes_crypt_dma(dd, dd->in_sg, dd->out_sg, dd->in_sg_len, 386 dd->out_sg_len); 387 if (err && !dd->pio_only) { 388 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 389 if (dd->out_sg_len) 390 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, 391 DMA_FROM_DEVICE); 392 } 393 394 return err; 395 } 396 397 static void omap_aes_finish_req(struct omap_aes_dev *dd, int err) 398 { 399 struct skcipher_request *req = dd->req; 400 401 pr_debug("err: %d\n", err); 402 403 crypto_finalize_skcipher_request(dd->engine, req, err); 404 405 pm_runtime_put_autosuspend(dd->dev); 406 } 407 408 int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd) 409 { 410 pr_debug("total: %zu\n", dd->total); 411 412 omap_aes_dma_stop(dd); 413 414 415 return 0; 416 } 417 418 static int omap_aes_handle_queue(struct omap_aes_dev *dd, 419 struct skcipher_request *req) 420 { 421 if (req) 422 return crypto_transfer_skcipher_request_to_engine(dd->engine, req); 423 424 return 0; 425 } 426 427 static int omap_aes_prepare_req(struct skcipher_request *req, 428 struct omap_aes_dev *dd) 429 { 430 struct omap_aes_ctx *ctx = crypto_skcipher_ctx( 431 crypto_skcipher_reqtfm(req)); 432 struct omap_aes_reqctx *rctx = skcipher_request_ctx(req); 433 int ret; 434 u16 flags; 435 436 /* assign new request to device */ 437 dd->req = req; 438 dd->total = req->cryptlen; 439 dd->total_save = req->cryptlen; 440 dd->in_sg = req->src; 441 dd->out_sg = req->dst; 442 dd->orig_out = req->dst; 443 444 flags = OMAP_CRYPTO_COPY_DATA; 445 if (req->src == req->dst) 446 flags |= OMAP_CRYPTO_FORCE_COPY; 447 448 ret = omap_crypto_align_sg(&dd->in_sg, dd->total, AES_BLOCK_SIZE, 449 dd->in_sgl, flags, 450 FLAGS_IN_DATA_ST_SHIFT, &dd->flags); 451 if (ret) 452 return ret; 453 454 ret = omap_crypto_align_sg(&dd->out_sg, dd->total, AES_BLOCK_SIZE, 455 &dd->out_sgl, 0, 456 FLAGS_OUT_DATA_ST_SHIFT, &dd->flags); 457 if (ret) 458 return ret; 459 460 dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total); 461 if (dd->in_sg_len < 0) 462 return dd->in_sg_len; 463 464 dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total); 465 if (dd->out_sg_len < 0) 466 return dd->out_sg_len; 467 468 rctx->mode &= FLAGS_MODE_MASK; 469 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode; 470 471 dd->ctx = ctx; 472 rctx->dd = dd; 473 474 return omap_aes_write_ctrl(dd); 475 } 476 477 static int omap_aes_crypt_req(struct crypto_engine *engine, 478 void *areq) 479 { 480 struct skcipher_request *req = container_of(areq, struct skcipher_request, base); 481 struct omap_aes_reqctx *rctx = skcipher_request_ctx(req); 482 struct omap_aes_dev *dd = rctx->dd; 483 484 if (!dd) 485 return -ENODEV; 486 487 return omap_aes_prepare_req(req, dd) ?: 488 omap_aes_crypt_dma_start(dd); 489 } 490 491 static void omap_aes_copy_ivout(struct omap_aes_dev *dd, u8 *ivbuf) 492 { 493 int i; 494 495 for (i = 0; i < 4; i++) 496 ((u32 *)ivbuf)[i] = omap_aes_read(dd, AES_REG_IV(dd, i)); 497 } 498 499 static void omap_aes_done_task(struct work_struct *t) 500 { 501 struct omap_aes_dev *dd = from_work(dd, t, done_task); 502 503 pr_debug("enter done_task\n"); 504 505 if (!dd->pio_only) { 506 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len, 507 DMA_FROM_DEVICE); 508 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); 509 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, 510 DMA_FROM_DEVICE); 511 omap_aes_crypt_dma_stop(dd); 512 } 513 514 omap_crypto_cleanup(dd->in_sg, NULL, 0, dd->total_save, 515 FLAGS_IN_DATA_ST_SHIFT, dd->flags); 516 517 omap_crypto_cleanup(dd->out_sg, dd->orig_out, 0, dd->total_save, 518 FLAGS_OUT_DATA_ST_SHIFT, dd->flags); 519 520 /* Update IV output */ 521 if (dd->flags & (FLAGS_CBC | FLAGS_CTR)) 522 omap_aes_copy_ivout(dd, dd->req->iv); 523 524 omap_aes_finish_req(dd, 0); 525 526 pr_debug("exit\n"); 527 } 528 529 static int omap_aes_crypt(struct skcipher_request *req, unsigned long mode) 530 { 531 struct omap_aes_ctx *ctx = crypto_skcipher_ctx( 532 crypto_skcipher_reqtfm(req)); 533 struct omap_aes_reqctx *rctx = skcipher_request_ctx(req); 534 struct omap_aes_dev *dd; 535 int ret; 536 537 if ((req->cryptlen % AES_BLOCK_SIZE) && !(mode & FLAGS_CTR)) 538 return -EINVAL; 539 540 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->cryptlen, 541 !!(mode & FLAGS_ENCRYPT), 542 !!(mode & FLAGS_CBC)); 543 544 if (req->cryptlen < aes_fallback_sz) { 545 skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback); 546 skcipher_request_set_callback(&rctx->fallback_req, 547 req->base.flags, 548 req->base.complete, 549 req->base.data); 550 skcipher_request_set_crypt(&rctx->fallback_req, req->src, 551 req->dst, req->cryptlen, req->iv); 552 553 if (mode & FLAGS_ENCRYPT) 554 ret = crypto_skcipher_encrypt(&rctx->fallback_req); 555 else 556 ret = crypto_skcipher_decrypt(&rctx->fallback_req); 557 return ret; 558 } 559 dd = omap_aes_find_dev(rctx); 560 if (!dd) 561 return -ENODEV; 562 563 rctx->mode = mode; 564 565 return omap_aes_handle_queue(dd, req); 566 } 567 568 /* ********************** ALG API ************************************ */ 569 570 static int omap_aes_setkey(struct crypto_skcipher *tfm, const u8 *key, 571 unsigned int keylen) 572 { 573 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm); 574 int ret; 575 576 if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 && 577 keylen != AES_KEYSIZE_256) 578 return -EINVAL; 579 580 pr_debug("enter, keylen: %d\n", keylen); 581 582 memcpy(ctx->key, key, keylen); 583 ctx->keylen = keylen; 584 585 crypto_skcipher_clear_flags(ctx->fallback, CRYPTO_TFM_REQ_MASK); 586 crypto_skcipher_set_flags(ctx->fallback, tfm->base.crt_flags & 587 CRYPTO_TFM_REQ_MASK); 588 589 ret = crypto_skcipher_setkey(ctx->fallback, key, keylen); 590 if (!ret) 591 return 0; 592 593 return 0; 594 } 595 596 static int omap_aes_ecb_encrypt(struct skcipher_request *req) 597 { 598 return omap_aes_crypt(req, FLAGS_ENCRYPT); 599 } 600 601 static int omap_aes_ecb_decrypt(struct skcipher_request *req) 602 { 603 return omap_aes_crypt(req, 0); 604 } 605 606 static int omap_aes_cbc_encrypt(struct skcipher_request *req) 607 { 608 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC); 609 } 610 611 static int omap_aes_cbc_decrypt(struct skcipher_request *req) 612 { 613 return omap_aes_crypt(req, FLAGS_CBC); 614 } 615 616 static int omap_aes_ctr_encrypt(struct skcipher_request *req) 617 { 618 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR); 619 } 620 621 static int omap_aes_ctr_decrypt(struct skcipher_request *req) 622 { 623 return omap_aes_crypt(req, FLAGS_CTR); 624 } 625 626 static int omap_aes_init_tfm(struct crypto_skcipher *tfm) 627 { 628 const char *name = crypto_tfm_alg_name(&tfm->base); 629 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm); 630 struct crypto_skcipher *blk; 631 632 blk = crypto_alloc_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK); 633 if (IS_ERR(blk)) 634 return PTR_ERR(blk); 635 636 ctx->fallback = blk; 637 638 crypto_skcipher_set_reqsize(tfm, sizeof(struct omap_aes_reqctx) + 639 crypto_skcipher_reqsize(blk)); 640 641 return 0; 642 } 643 644 static void omap_aes_exit_tfm(struct crypto_skcipher *tfm) 645 { 646 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm); 647 648 if (ctx->fallback) 649 crypto_free_skcipher(ctx->fallback); 650 651 ctx->fallback = NULL; 652 } 653 654 /* ********************** ALGS ************************************ */ 655 656 static struct skcipher_engine_alg algs_ecb_cbc[] = { 657 { 658 .base = { 659 .base.cra_name = "ecb(aes)", 660 .base.cra_driver_name = "ecb-aes-omap", 661 .base.cra_priority = 300, 662 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 663 CRYPTO_ALG_ASYNC | 664 CRYPTO_ALG_NEED_FALLBACK, 665 .base.cra_blocksize = AES_BLOCK_SIZE, 666 .base.cra_ctxsize = sizeof(struct omap_aes_ctx), 667 .base.cra_module = THIS_MODULE, 668 669 .min_keysize = AES_MIN_KEY_SIZE, 670 .max_keysize = AES_MAX_KEY_SIZE, 671 .setkey = omap_aes_setkey, 672 .encrypt = omap_aes_ecb_encrypt, 673 .decrypt = omap_aes_ecb_decrypt, 674 .init = omap_aes_init_tfm, 675 .exit = omap_aes_exit_tfm, 676 }, 677 .op.do_one_request = omap_aes_crypt_req, 678 }, 679 { 680 .base = { 681 .base.cra_name = "cbc(aes)", 682 .base.cra_driver_name = "cbc-aes-omap", 683 .base.cra_priority = 300, 684 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 685 CRYPTO_ALG_ASYNC | 686 CRYPTO_ALG_NEED_FALLBACK, 687 .base.cra_blocksize = AES_BLOCK_SIZE, 688 .base.cra_ctxsize = sizeof(struct omap_aes_ctx), 689 .base.cra_module = THIS_MODULE, 690 691 .min_keysize = AES_MIN_KEY_SIZE, 692 .max_keysize = AES_MAX_KEY_SIZE, 693 .ivsize = AES_BLOCK_SIZE, 694 .setkey = omap_aes_setkey, 695 .encrypt = omap_aes_cbc_encrypt, 696 .decrypt = omap_aes_cbc_decrypt, 697 .init = omap_aes_init_tfm, 698 .exit = omap_aes_exit_tfm, 699 }, 700 .op.do_one_request = omap_aes_crypt_req, 701 } 702 }; 703 704 static struct skcipher_engine_alg algs_ctr[] = { 705 { 706 .base = { 707 .base.cra_name = "ctr(aes)", 708 .base.cra_driver_name = "ctr-aes-omap", 709 .base.cra_priority = 300, 710 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 711 CRYPTO_ALG_ASYNC | 712 CRYPTO_ALG_NEED_FALLBACK, 713 .base.cra_blocksize = 1, 714 .base.cra_ctxsize = sizeof(struct omap_aes_ctx), 715 .base.cra_module = THIS_MODULE, 716 717 .min_keysize = AES_MIN_KEY_SIZE, 718 .max_keysize = AES_MAX_KEY_SIZE, 719 .ivsize = AES_BLOCK_SIZE, 720 .setkey = omap_aes_setkey, 721 .encrypt = omap_aes_ctr_encrypt, 722 .decrypt = omap_aes_ctr_decrypt, 723 .init = omap_aes_init_tfm, 724 .exit = omap_aes_exit_tfm, 725 }, 726 .op.do_one_request = omap_aes_crypt_req, 727 } 728 }; 729 730 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = { 731 { 732 .algs_list = algs_ecb_cbc, 733 .size = ARRAY_SIZE(algs_ecb_cbc), 734 }, 735 }; 736 737 static struct aead_engine_alg algs_aead_gcm[] = { 738 { 739 .base = { 740 .base = { 741 .cra_name = "gcm(aes)", 742 .cra_driver_name = "gcm-aes-omap", 743 .cra_priority = 300, 744 .cra_flags = CRYPTO_ALG_ASYNC | 745 CRYPTO_ALG_KERN_DRIVER_ONLY, 746 .cra_blocksize = 1, 747 .cra_ctxsize = sizeof(struct omap_aes_gcm_ctx), 748 .cra_alignmask = 0xf, 749 .cra_module = THIS_MODULE, 750 }, 751 .init = omap_aes_gcm_cra_init, 752 .ivsize = GCM_AES_IV_SIZE, 753 .maxauthsize = AES_BLOCK_SIZE, 754 .setkey = omap_aes_gcm_setkey, 755 .setauthsize = omap_aes_gcm_setauthsize, 756 .encrypt = omap_aes_gcm_encrypt, 757 .decrypt = omap_aes_gcm_decrypt, 758 }, 759 .op.do_one_request = omap_aes_gcm_crypt_req, 760 }, 761 { 762 .base = { 763 .base = { 764 .cra_name = "rfc4106(gcm(aes))", 765 .cra_driver_name = "rfc4106-gcm-aes-omap", 766 .cra_priority = 300, 767 .cra_flags = CRYPTO_ALG_ASYNC | 768 CRYPTO_ALG_KERN_DRIVER_ONLY, 769 .cra_blocksize = 1, 770 .cra_ctxsize = sizeof(struct omap_aes_gcm_ctx), 771 .cra_alignmask = 0xf, 772 .cra_module = THIS_MODULE, 773 }, 774 .init = omap_aes_gcm_cra_init, 775 .maxauthsize = AES_BLOCK_SIZE, 776 .ivsize = GCM_RFC4106_IV_SIZE, 777 .setkey = omap_aes_4106gcm_setkey, 778 .setauthsize = omap_aes_4106gcm_setauthsize, 779 .encrypt = omap_aes_4106gcm_encrypt, 780 .decrypt = omap_aes_4106gcm_decrypt, 781 }, 782 .op.do_one_request = omap_aes_gcm_crypt_req, 783 }, 784 }; 785 786 static struct omap_aes_aead_algs omap_aes_aead_info = { 787 .algs_list = algs_aead_gcm, 788 .size = ARRAY_SIZE(algs_aead_gcm), 789 }; 790 791 static const struct omap_aes_pdata omap_aes_pdata_omap2 = { 792 .algs_info = omap_aes_algs_info_ecb_cbc, 793 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc), 794 .trigger = omap_aes_dma_trigger_omap2, 795 .key_ofs = 0x1c, 796 .iv_ofs = 0x20, 797 .ctrl_ofs = 0x30, 798 .data_ofs = 0x34, 799 .rev_ofs = 0x44, 800 .mask_ofs = 0x48, 801 .dma_enable_in = BIT(2), 802 .dma_enable_out = BIT(3), 803 .dma_start = BIT(5), 804 .major_mask = 0xf0, 805 .major_shift = 4, 806 .minor_mask = 0x0f, 807 .minor_shift = 0, 808 }; 809 810 #ifdef CONFIG_OF 811 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = { 812 { 813 .algs_list = algs_ecb_cbc, 814 .size = ARRAY_SIZE(algs_ecb_cbc), 815 }, 816 { 817 .algs_list = algs_ctr, 818 .size = ARRAY_SIZE(algs_ctr), 819 }, 820 }; 821 822 static const struct omap_aes_pdata omap_aes_pdata_omap3 = { 823 .algs_info = omap_aes_algs_info_ecb_cbc_ctr, 824 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr), 825 .trigger = omap_aes_dma_trigger_omap2, 826 .key_ofs = 0x1c, 827 .iv_ofs = 0x20, 828 .ctrl_ofs = 0x30, 829 .data_ofs = 0x34, 830 .rev_ofs = 0x44, 831 .mask_ofs = 0x48, 832 .dma_enable_in = BIT(2), 833 .dma_enable_out = BIT(3), 834 .dma_start = BIT(5), 835 .major_mask = 0xf0, 836 .major_shift = 4, 837 .minor_mask = 0x0f, 838 .minor_shift = 0, 839 }; 840 841 static const struct omap_aes_pdata omap_aes_pdata_omap4 = { 842 .algs_info = omap_aes_algs_info_ecb_cbc_ctr, 843 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr), 844 .aead_algs_info = &omap_aes_aead_info, 845 .trigger = omap_aes_dma_trigger_omap4, 846 .key_ofs = 0x3c, 847 .iv_ofs = 0x40, 848 .ctrl_ofs = 0x50, 849 .data_ofs = 0x60, 850 .rev_ofs = 0x80, 851 .mask_ofs = 0x84, 852 .irq_status_ofs = 0x8c, 853 .irq_enable_ofs = 0x90, 854 .dma_enable_in = BIT(5), 855 .dma_enable_out = BIT(6), 856 .major_mask = 0x0700, 857 .major_shift = 8, 858 .minor_mask = 0x003f, 859 .minor_shift = 0, 860 }; 861 862 static irqreturn_t omap_aes_irq(int irq, void *dev_id) 863 { 864 struct omap_aes_dev *dd = dev_id; 865 u32 status, i; 866 u32 *src, *dst; 867 868 status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd)); 869 if (status & AES_REG_IRQ_DATA_IN) { 870 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0); 871 872 BUG_ON(!dd->in_sg); 873 874 BUG_ON(dd->in_sg_offset > dd->in_sg->length); 875 876 src = sg_virt(dd->in_sg) + dd->in_sg_offset; 877 878 for (i = 0; i < AES_BLOCK_WORDS; i++) { 879 omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src); 880 dd->in_sg_offset += 4; 881 if (dd->in_sg_offset == dd->in_sg->length) { 882 dd->in_sg = sg_next(dd->in_sg); 883 if (dd->in_sg) { 884 dd->in_sg_offset = 0; 885 src = sg_virt(dd->in_sg); 886 } 887 } else { 888 src++; 889 } 890 } 891 892 /* Clear IRQ status */ 893 status &= ~AES_REG_IRQ_DATA_IN; 894 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status); 895 896 /* Enable DATA_OUT interrupt */ 897 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4); 898 899 } else if (status & AES_REG_IRQ_DATA_OUT) { 900 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0); 901 902 BUG_ON(!dd->out_sg); 903 904 BUG_ON(dd->out_sg_offset > dd->out_sg->length); 905 906 dst = sg_virt(dd->out_sg) + dd->out_sg_offset; 907 908 for (i = 0; i < AES_BLOCK_WORDS; i++) { 909 *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i)); 910 dd->out_sg_offset += 4; 911 if (dd->out_sg_offset == dd->out_sg->length) { 912 dd->out_sg = sg_next(dd->out_sg); 913 if (dd->out_sg) { 914 dd->out_sg_offset = 0; 915 dst = sg_virt(dd->out_sg); 916 } 917 } else { 918 dst++; 919 } 920 } 921 922 dd->total -= min_t(size_t, AES_BLOCK_SIZE, dd->total); 923 924 /* Clear IRQ status */ 925 status &= ~AES_REG_IRQ_DATA_OUT; 926 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status); 927 928 if (!dd->total) 929 /* All bytes read! */ 930 queue_work(system_bh_wq, &dd->done_task); 931 else 932 /* Enable DATA_IN interrupt for next block */ 933 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2); 934 } 935 936 return IRQ_HANDLED; 937 } 938 939 static const struct of_device_id omap_aes_of_match[] = { 940 { 941 .compatible = "ti,omap2-aes", 942 .data = &omap_aes_pdata_omap2, 943 }, 944 { 945 .compatible = "ti,omap3-aes", 946 .data = &omap_aes_pdata_omap3, 947 }, 948 { 949 .compatible = "ti,omap4-aes", 950 .data = &omap_aes_pdata_omap4, 951 }, 952 {}, 953 }; 954 MODULE_DEVICE_TABLE(of, omap_aes_of_match); 955 956 static int omap_aes_get_res_of(struct omap_aes_dev *dd, 957 struct device *dev, struct resource *res) 958 { 959 struct device_node *node = dev->of_node; 960 int err = 0; 961 962 dd->pdata = of_device_get_match_data(dev); 963 if (!dd->pdata) { 964 dev_err(dev, "no compatible OF match\n"); 965 err = -EINVAL; 966 goto err; 967 } 968 969 err = of_address_to_resource(node, 0, res); 970 if (err < 0) { 971 dev_err(dev, "can't translate OF node address\n"); 972 err = -EINVAL; 973 goto err; 974 } 975 976 err: 977 return err; 978 } 979 #else 980 static const struct of_device_id omap_aes_of_match[] = { 981 {}, 982 }; 983 984 static int omap_aes_get_res_of(struct omap_aes_dev *dd, 985 struct device *dev, struct resource *res) 986 { 987 return -EINVAL; 988 } 989 #endif 990 991 static int omap_aes_get_res_pdev(struct omap_aes_dev *dd, 992 struct platform_device *pdev, struct resource *res) 993 { 994 struct device *dev = &pdev->dev; 995 struct resource *r; 996 int err = 0; 997 998 /* Get the base address */ 999 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1000 if (!r) { 1001 dev_err(dev, "no MEM resource info\n"); 1002 err = -ENODEV; 1003 goto err; 1004 } 1005 memcpy(res, r, sizeof(*res)); 1006 1007 /* Only OMAP2/3 can be non-DT */ 1008 dd->pdata = &omap_aes_pdata_omap2; 1009 1010 err: 1011 return err; 1012 } 1013 1014 static ssize_t fallback_show(struct device *dev, struct device_attribute *attr, 1015 char *buf) 1016 { 1017 return sprintf(buf, "%d\n", aes_fallback_sz); 1018 } 1019 1020 static ssize_t fallback_store(struct device *dev, struct device_attribute *attr, 1021 const char *buf, size_t size) 1022 { 1023 ssize_t status; 1024 long value; 1025 1026 status = kstrtol(buf, 0, &value); 1027 if (status) 1028 return status; 1029 1030 /* HW accelerator only works with buffers > 9 */ 1031 if (value < 9) { 1032 dev_err(dev, "minimum fallback size 9\n"); 1033 return -EINVAL; 1034 } 1035 1036 aes_fallback_sz = value; 1037 1038 return size; 1039 } 1040 1041 static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr, 1042 char *buf) 1043 { 1044 struct omap_aes_dev *dd = dev_get_drvdata(dev); 1045 1046 return sysfs_emit(buf, "%d\n", dd->engine->queue.max_qlen); 1047 } 1048 1049 static ssize_t queue_len_store(struct device *dev, 1050 struct device_attribute *attr, const char *buf, 1051 size_t size) 1052 { 1053 struct omap_aes_dev *dd; 1054 ssize_t status; 1055 long value; 1056 unsigned long flags; 1057 1058 status = kstrtol(buf, 0, &value); 1059 if (status) 1060 return status; 1061 1062 if (value < 1) 1063 return -EINVAL; 1064 1065 /* 1066 * Changing the queue size in fly is safe, if size becomes smaller 1067 * than current size, it will just not accept new entries until 1068 * it has shrank enough. 1069 */ 1070 spin_lock_bh(&list_lock); 1071 list_for_each_entry(dd, &dev_list, list) { 1072 spin_lock_irqsave(&dd->lock, flags); 1073 dd->engine->queue.max_qlen = value; 1074 dd->aead_queue.base.max_qlen = value; 1075 spin_unlock_irqrestore(&dd->lock, flags); 1076 } 1077 spin_unlock_bh(&list_lock); 1078 1079 return size; 1080 } 1081 1082 static DEVICE_ATTR_RW(queue_len); 1083 static DEVICE_ATTR_RW(fallback); 1084 1085 static struct attribute *omap_aes_attrs[] = { 1086 &dev_attr_queue_len.attr, 1087 &dev_attr_fallback.attr, 1088 NULL, 1089 }; 1090 ATTRIBUTE_GROUPS(omap_aes); 1091 1092 static void omap_aes_unregister_algs(const struct omap_aes_pdata *pdata) 1093 { 1094 struct omap_aes_algs_info *alg_info; 1095 int i; 1096 1097 for (i = pdata->algs_info_size - 1; i >= 0; i--) { 1098 alg_info = &pdata->algs_info[i]; 1099 1100 crypto_engine_unregister_skciphers(alg_info->algs_list, 1101 alg_info->registered); 1102 alg_info->registered = 0; 1103 } 1104 } 1105 1106 static int omap_aes_probe(struct platform_device *pdev) 1107 { 1108 struct device *dev = &pdev->dev; 1109 struct omap_aes_dev *dd; 1110 struct skcipher_engine_alg *algp; 1111 struct aead_engine_alg *aalg; 1112 struct resource res; 1113 int err = -ENOMEM, i, j, irq = -1; 1114 u32 reg; 1115 1116 dd = devm_kzalloc(dev, sizeof(struct omap_aes_dev), GFP_KERNEL); 1117 if (dd == NULL) { 1118 dev_err(dev, "unable to alloc data struct.\n"); 1119 goto err_data; 1120 } 1121 dd->dev = dev; 1122 platform_set_drvdata(pdev, dd); 1123 1124 aead_init_queue(&dd->aead_queue, OMAP_AES_QUEUE_LENGTH); 1125 1126 err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) : 1127 omap_aes_get_res_pdev(dd, pdev, &res); 1128 if (err) 1129 goto err_res; 1130 1131 dd->io_base = devm_ioremap_resource(dev, &res); 1132 if (IS_ERR(dd->io_base)) { 1133 err = PTR_ERR(dd->io_base); 1134 goto err_res; 1135 } 1136 dd->phys_base = res.start; 1137 1138 pm_runtime_use_autosuspend(dev); 1139 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY); 1140 1141 pm_runtime_enable(dev); 1142 err = pm_runtime_resume_and_get(dev); 1143 if (err < 0) { 1144 dev_err(dev, "%s: failed to get_sync(%d)\n", 1145 __func__, err); 1146 goto err_pm_disable; 1147 } 1148 1149 omap_aes_dma_stop(dd); 1150 1151 reg = omap_aes_read(dd, AES_REG_REV(dd)); 1152 1153 pm_runtime_put_sync(dev); 1154 1155 dev_info(dev, "OMAP AES hw accel rev: %u.%u\n", 1156 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift, 1157 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift); 1158 1159 INIT_WORK(&dd->done_task, omap_aes_done_task); 1160 1161 err = omap_aes_dma_init(dd); 1162 if (err == -EPROBE_DEFER) { 1163 goto err_irq; 1164 } else if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) { 1165 dd->pio_only = 1; 1166 1167 irq = platform_get_irq(pdev, 0); 1168 if (irq < 0) { 1169 err = irq; 1170 goto err_irq; 1171 } 1172 1173 err = devm_request_irq(dev, irq, omap_aes_irq, 0, 1174 dev_name(dev), dd); 1175 if (err) { 1176 dev_err(dev, "Unable to grab omap-aes IRQ\n"); 1177 goto err_irq; 1178 } 1179 } 1180 1181 spin_lock_init(&dd->lock); 1182 1183 INIT_LIST_HEAD(&dd->list); 1184 spin_lock_bh(&list_lock); 1185 list_add_tail(&dd->list, &dev_list); 1186 spin_unlock_bh(&list_lock); 1187 1188 /* Initialize crypto engine */ 1189 dd->engine = crypto_engine_alloc_init(dev, 1); 1190 if (!dd->engine) { 1191 err = -ENOMEM; 1192 goto err_engine; 1193 } 1194 1195 err = crypto_engine_start(dd->engine); 1196 if (err) 1197 goto err_engine; 1198 1199 for (i = 0; i < dd->pdata->algs_info_size; i++) { 1200 if (!dd->pdata->algs_info[i].registered) { 1201 for (j = 0; j < dd->pdata->algs_info[i].size; j++) { 1202 algp = &dd->pdata->algs_info[i].algs_list[j]; 1203 1204 pr_debug("reg alg: %s\n", algp->base.base.cra_name); 1205 1206 err = crypto_engine_register_skcipher(algp); 1207 if (err) 1208 goto err_algs; 1209 1210 dd->pdata->algs_info[i].registered++; 1211 } 1212 } 1213 } 1214 1215 if (dd->pdata->aead_algs_info && 1216 !dd->pdata->aead_algs_info->registered) { 1217 for (i = 0; i < dd->pdata->aead_algs_info->size; i++) { 1218 aalg = &dd->pdata->aead_algs_info->algs_list[i]; 1219 1220 pr_debug("reg alg: %s\n", aalg->base.base.cra_name); 1221 1222 err = crypto_engine_register_aead(aalg); 1223 if (err) 1224 goto err_aead_algs; 1225 1226 dd->pdata->aead_algs_info->registered++; 1227 } 1228 } 1229 1230 return 0; 1231 err_aead_algs: 1232 crypto_engine_unregister_aeads(dd->pdata->aead_algs_info->algs_list, 1233 dd->pdata->aead_algs_info->registered); 1234 dd->pdata->aead_algs_info->registered = 0; 1235 err_algs: 1236 omap_aes_unregister_algs(dd->pdata); 1237 1238 err_engine: 1239 if (dd->engine) 1240 crypto_engine_exit(dd->engine); 1241 1242 omap_aes_dma_cleanup(dd); 1243 err_irq: 1244 cancel_work_sync(&dd->done_task); 1245 err_pm_disable: 1246 pm_runtime_disable(dev); 1247 err_res: 1248 dd = NULL; 1249 err_data: 1250 dev_err(dev, "initialization failed.\n"); 1251 return err; 1252 } 1253 1254 static void omap_aes_remove(struct platform_device *pdev) 1255 { 1256 struct omap_aes_dev *dd = platform_get_drvdata(pdev); 1257 1258 spin_lock_bh(&list_lock); 1259 list_del(&dd->list); 1260 spin_unlock_bh(&list_lock); 1261 1262 omap_aes_unregister_algs(dd->pdata); 1263 1264 crypto_engine_unregister_aeads(dd->pdata->aead_algs_info->algs_list, 1265 dd->pdata->aead_algs_info->registered); 1266 dd->pdata->aead_algs_info->registered = 0; 1267 1268 crypto_engine_exit(dd->engine); 1269 1270 cancel_work_sync(&dd->done_task); 1271 omap_aes_dma_cleanup(dd); 1272 pm_runtime_disable(dd->dev); 1273 } 1274 1275 #ifdef CONFIG_PM_SLEEP 1276 static int omap_aes_suspend(struct device *dev) 1277 { 1278 pm_runtime_put_sync(dev); 1279 return 0; 1280 } 1281 1282 static int omap_aes_resume(struct device *dev) 1283 { 1284 pm_runtime_get_sync(dev); 1285 return 0; 1286 } 1287 #endif 1288 1289 static SIMPLE_DEV_PM_OPS(omap_aes_pm_ops, omap_aes_suspend, omap_aes_resume); 1290 1291 static struct platform_driver omap_aes_driver = { 1292 .probe = omap_aes_probe, 1293 .remove = omap_aes_remove, 1294 .driver = { 1295 .name = "omap-aes", 1296 .pm = &omap_aes_pm_ops, 1297 .of_match_table = omap_aes_of_match, 1298 .dev_groups = omap_aes_groups, 1299 }, 1300 }; 1301 1302 module_platform_driver(omap_aes_driver); 1303 1304 MODULE_DESCRIPTION("OMAP AES hw acceleration support."); 1305 MODULE_LICENSE("GPL v2"); 1306 MODULE_AUTHOR("Dmitry Kasatkin"); 1307 1308