xref: /linux/drivers/crypto/nx/nx-842.h (revision 63b47f026cc841bd3d3438dd6fccbc394dfead87)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 
3 #ifndef __NX_842_H__
4 #define __NX_842_H__
5 
6 #include <crypto/algapi.h>
7 #include <linux/kernel.h>
8 #include <linux/init.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/slab.h>
12 #include <linux/io.h>
13 #include <linux/mm.h>
14 #include <linux/ratelimit.h>
15 
16 /* Restrictions on Data Descriptor List (DDL) and Entry (DDE) buffers
17  *
18  * From NX P8 workbook, sec 4.9.1 "842 details"
19  *   Each DDE buffer is 128 byte aligned
20  *   Each DDE buffer size is a multiple of 32 bytes (except the last)
21  *   The last DDE buffer size is a multiple of 8 bytes
22  */
23 #define DDE_BUFFER_ALIGN	(128)
24 #define DDE_BUFFER_SIZE_MULT	(32)
25 #define DDE_BUFFER_LAST_MULT	(8)
26 
27 /* Arbitrary DDL length limit
28  * Allows max buffer size of MAX-1 to MAX pages
29  * (depending on alignment)
30  */
31 #define DDL_LEN_MAX		(17)
32 
33 /* CCW 842 CI/FC masks
34  * NX P8 workbook, section 4.3.1, figure 4-6
35  * "CI/FC Boundary by NX CT type"
36  */
37 #define CCW_CI_842		(0x00003ff8)
38 #define CCW_FC_842		(0x00000007)
39 
40 /* CCW Function Codes (FC) for 842
41  * NX P8 workbook, section 4.9, table 4-28
42  * "Function Code Definitions for 842 Memory Compression"
43  */
44 #define CCW_FC_842_COMP_NOCRC	(0)
45 #define CCW_FC_842_COMP_CRC	(1)
46 #define CCW_FC_842_DECOMP_NOCRC	(2)
47 #define CCW_FC_842_DECOMP_CRC	(3)
48 #define CCW_FC_842_MOVE		(4)
49 
50 /* CSB CC Error Types for 842
51  * NX P8 workbook, section 4.10.3, table 4-30
52  * "Reported Error Types Summary Table"
53  */
54 /* These are all duplicates of existing codes defined in icswx.h. */
55 #define CSB_CC_TRANSLATION_DUP1	(80)
56 #define CSB_CC_TRANSLATION_DUP2	(82)
57 #define CSB_CC_TRANSLATION_DUP3	(84)
58 #define CSB_CC_TRANSLATION_DUP4	(86)
59 #define CSB_CC_TRANSLATION_DUP5	(92)
60 #define CSB_CC_TRANSLATION_DUP6	(94)
61 #define CSB_CC_PROTECTION_DUP1	(81)
62 #define CSB_CC_PROTECTION_DUP2	(83)
63 #define CSB_CC_PROTECTION_DUP3	(85)
64 #define CSB_CC_PROTECTION_DUP4	(87)
65 #define CSB_CC_PROTECTION_DUP5	(93)
66 #define CSB_CC_PROTECTION_DUP6	(95)
67 #define CSB_CC_RD_EXTERNAL_DUP1	(89)
68 #define CSB_CC_RD_EXTERNAL_DUP2	(90)
69 #define CSB_CC_RD_EXTERNAL_DUP3	(91)
70 /* These are specific to NX */
71 /* 842 codes */
72 #define CSB_CC_TPBC_GT_SPBC	(64) /* no error, but >1 comp ratio */
73 #define CSB_CC_CRC_MISMATCH	(65) /* decomp crc mismatch */
74 #define CSB_CC_TEMPL_INVALID	(66) /* decomp invalid template value */
75 #define CSB_CC_TEMPL_OVERFLOW	(67) /* decomp template shows data after end */
76 /* sym crypt codes */
77 #define CSB_CC_DECRYPT_OVERFLOW	(64)
78 /* asym crypt codes */
79 #define CSB_CC_MINV_OVERFLOW	(128)
80 /*
81  * HW error - Job did not finish in the maximum time allowed.
82  * Job terminated.
83  */
84 #define CSB_CC_HW_EXPIRED_TIMER		(224)
85 /* These are reserved for hypervisor use */
86 #define CSB_CC_HYP_RESERVE_START	(240)
87 #define CSB_CC_HYP_RESERVE_END		(253)
88 #define CSB_CC_HYP_RESERVE_P9_END	(251)
89 /* No valid interrupt server (P9 or later). */
90 #define CSB_CC_HYP_RESERVE_NO_INTR_SERVER	(252)
91 #define CSB_CC_HYP_NO_HW		(254)
92 #define CSB_CC_HYP_HANG_ABORTED		(255)
93 
94 /* CCB Completion Modes (CM) for 842
95  * NX P8 workbook, section 4.3, figure 4-5
96  * "CRB Details - Normal Cop_Req (CL=00, C=1)"
97  */
98 #define CCB_CM_EXTRA_WRITE	(CCB_CM0_ALL_COMPLETIONS & CCB_CM12_STORE)
99 #define CCB_CM_INTERRUPT	(CCB_CM0_ALL_COMPLETIONS & CCB_CM12_INTERRUPT)
100 
101 #define LEN_ON_SIZE(pa, size)	((size) - ((pa) & ((size) - 1)))
102 #define LEN_ON_PAGE(pa)		LEN_ON_SIZE(pa, PAGE_SIZE)
103 
104 static inline unsigned long nx842_get_pa(void *addr)
105 {
106 	if (!is_vmalloc_addr(addr))
107 		return __pa(addr);
108 
109 	return page_to_phys(vmalloc_to_page(addr)) + offset_in_page(addr);
110 }
111 
112 /**
113  * This provides the driver's constraints.  Different nx842 implementations
114  * may have varying requirements.  The constraints are:
115  *   @alignment:	All buffers should be aligned to this
116  *   @multiple:		All buffer lengths should be a multiple of this
117  *   @minimum:		Buffer lengths must not be less than this amount
118  *   @maximum:		Buffer lengths must not be more than this amount
119  *
120  * The constraints apply to all buffers and lengths, both input and output,
121  * for both compression and decompression, except for the minimum which
122  * only applies to compression input and decompression output; the
123  * compressed data can be less than the minimum constraint.  It can be
124  * assumed that compressed data will always adhere to the multiple
125  * constraint.
126  *
127  * The driver may succeed even if these constraints are violated;
128  * however the driver can return failure or suffer reduced performance
129  * if any constraint is not met.
130  */
131 struct nx842_constraints {
132 	int alignment;
133 	int multiple;
134 	int minimum;
135 	int maximum;
136 };
137 
138 struct nx842_driver {
139 	char *name;
140 	struct module *owner;
141 	size_t workmem_size;
142 
143 	struct nx842_constraints *constraints;
144 
145 	int (*compress)(const unsigned char *in, unsigned int in_len,
146 			unsigned char *out, unsigned int *out_len,
147 			void *wrkmem);
148 	int (*decompress)(const unsigned char *in, unsigned int in_len,
149 			  unsigned char *out, unsigned int *out_len,
150 			  void *wrkmem);
151 };
152 
153 struct nx842_crypto_header_group {
154 	__be16 padding;			/* unused bytes at start of group */
155 	__be32 compressed_length;	/* compressed bytes in group */
156 	__be32 uncompressed_length;	/* bytes after decompression */
157 } __packed;
158 
159 struct nx842_crypto_header {
160 	struct_group_tagged(nx842_crypto_header_hdr, hdr,
161 		__be16 magic;		/* NX842_CRYPTO_MAGIC */
162 		__be16 ignore;		/* decompressed end bytes to ignore */
163 		u8 groups;		/* total groups in this header */
164 	);
165 	struct nx842_crypto_header_group group[];
166 } __packed;
167 
168 #define NX842_CRYPTO_GROUP_MAX	(0x20)
169 
170 struct nx842_crypto_ctx {
171 	spinlock_t lock;
172 
173 	u8 *wmem;
174 	u8 *sbounce, *dbounce;
175 
176 	struct nx842_crypto_header_hdr header;
177 	struct nx842_crypto_header_group group[NX842_CRYPTO_GROUP_MAX];
178 
179 	struct nx842_driver *driver;
180 };
181 
182 int nx842_crypto_init(struct crypto_tfm *tfm, struct nx842_driver *driver);
183 void nx842_crypto_exit(struct crypto_tfm *tfm);
184 int nx842_crypto_compress(struct crypto_tfm *tfm,
185 			  const u8 *src, unsigned int slen,
186 			  u8 *dst, unsigned int *dlen);
187 int nx842_crypto_decompress(struct crypto_tfm *tfm,
188 			    const u8 *src, unsigned int slen,
189 			    u8 *dst, unsigned int *dlen);
190 
191 #endif /* __NX_842_H__ */
192