1 /* 2 * Freescale i.MX23/i.MX28 Data Co-Processor driver 3 * 4 * Copyright (C) 2013 Marek Vasut <marex@denx.de> 5 * 6 * The code contained herein is licensed under the GNU General Public 7 * License. You may obtain a copy of the GNU General Public License 8 * Version 2 or later at the following locations: 9 * 10 * http://www.opensource.org/licenses/gpl-license.html 11 * http://www.gnu.org/copyleft/gpl.html 12 */ 13 14 #include <linux/dma-mapping.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/kernel.h> 18 #include <linux/kthread.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/platform_device.h> 22 #include <linux/stmp_device.h> 23 24 #include <crypto/aes.h> 25 #include <crypto/sha.h> 26 #include <crypto/internal/hash.h> 27 #include <crypto/internal/skcipher.h> 28 29 #define DCP_MAX_CHANS 4 30 #define DCP_BUF_SZ PAGE_SIZE 31 32 #define DCP_ALIGNMENT 64 33 34 /* DCP DMA descriptor. */ 35 struct dcp_dma_desc { 36 uint32_t next_cmd_addr; 37 uint32_t control0; 38 uint32_t control1; 39 uint32_t source; 40 uint32_t destination; 41 uint32_t size; 42 uint32_t payload; 43 uint32_t status; 44 }; 45 46 /* Coherent aligned block for bounce buffering. */ 47 struct dcp_coherent_block { 48 uint8_t aes_in_buf[DCP_BUF_SZ]; 49 uint8_t aes_out_buf[DCP_BUF_SZ]; 50 uint8_t sha_in_buf[DCP_BUF_SZ]; 51 52 uint8_t aes_key[2 * AES_KEYSIZE_128]; 53 54 struct dcp_dma_desc desc[DCP_MAX_CHANS]; 55 }; 56 57 struct dcp { 58 struct device *dev; 59 void __iomem *base; 60 61 uint32_t caps; 62 63 struct dcp_coherent_block *coh; 64 65 struct completion completion[DCP_MAX_CHANS]; 66 struct mutex mutex[DCP_MAX_CHANS]; 67 struct task_struct *thread[DCP_MAX_CHANS]; 68 struct crypto_queue queue[DCP_MAX_CHANS]; 69 }; 70 71 enum dcp_chan { 72 DCP_CHAN_HASH_SHA = 0, 73 DCP_CHAN_CRYPTO = 2, 74 }; 75 76 struct dcp_async_ctx { 77 /* Common context */ 78 enum dcp_chan chan; 79 uint32_t fill; 80 81 /* SHA Hash-specific context */ 82 struct mutex mutex; 83 uint32_t alg; 84 unsigned int hot:1; 85 86 /* Crypto-specific context */ 87 struct crypto_sync_skcipher *fallback; 88 unsigned int key_len; 89 uint8_t key[AES_KEYSIZE_128]; 90 }; 91 92 struct dcp_aes_req_ctx { 93 unsigned int enc:1; 94 unsigned int ecb:1; 95 }; 96 97 struct dcp_sha_req_ctx { 98 unsigned int init:1; 99 unsigned int fini:1; 100 }; 101 102 /* 103 * There can even be only one instance of the MXS DCP due to the 104 * design of Linux Crypto API. 105 */ 106 static struct dcp *global_sdcp; 107 108 /* DCP register layout. */ 109 #define MXS_DCP_CTRL 0x00 110 #define MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES (1 << 23) 111 #define MXS_DCP_CTRL_ENABLE_CONTEXT_CACHING (1 << 22) 112 113 #define MXS_DCP_STAT 0x10 114 #define MXS_DCP_STAT_CLR 0x18 115 #define MXS_DCP_STAT_IRQ_MASK 0xf 116 117 #define MXS_DCP_CHANNELCTRL 0x20 118 #define MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK 0xff 119 120 #define MXS_DCP_CAPABILITY1 0x40 121 #define MXS_DCP_CAPABILITY1_SHA256 (4 << 16) 122 #define MXS_DCP_CAPABILITY1_SHA1 (1 << 16) 123 #define MXS_DCP_CAPABILITY1_AES128 (1 << 0) 124 125 #define MXS_DCP_CONTEXT 0x50 126 127 #define MXS_DCP_CH_N_CMDPTR(n) (0x100 + ((n) * 0x40)) 128 129 #define MXS_DCP_CH_N_SEMA(n) (0x110 + ((n) * 0x40)) 130 131 #define MXS_DCP_CH_N_STAT(n) (0x120 + ((n) * 0x40)) 132 #define MXS_DCP_CH_N_STAT_CLR(n) (0x128 + ((n) * 0x40)) 133 134 /* DMA descriptor bits. */ 135 #define MXS_DCP_CONTROL0_HASH_TERM (1 << 13) 136 #define MXS_DCP_CONTROL0_HASH_INIT (1 << 12) 137 #define MXS_DCP_CONTROL0_PAYLOAD_KEY (1 << 11) 138 #define MXS_DCP_CONTROL0_CIPHER_ENCRYPT (1 << 8) 139 #define MXS_DCP_CONTROL0_CIPHER_INIT (1 << 9) 140 #define MXS_DCP_CONTROL0_ENABLE_HASH (1 << 6) 141 #define MXS_DCP_CONTROL0_ENABLE_CIPHER (1 << 5) 142 #define MXS_DCP_CONTROL0_DECR_SEMAPHORE (1 << 1) 143 #define MXS_DCP_CONTROL0_INTERRUPT (1 << 0) 144 145 #define MXS_DCP_CONTROL1_HASH_SELECT_SHA256 (2 << 16) 146 #define MXS_DCP_CONTROL1_HASH_SELECT_SHA1 (0 << 16) 147 #define MXS_DCP_CONTROL1_CIPHER_MODE_CBC (1 << 4) 148 #define MXS_DCP_CONTROL1_CIPHER_MODE_ECB (0 << 4) 149 #define MXS_DCP_CONTROL1_CIPHER_SELECT_AES128 (0 << 0) 150 151 static int mxs_dcp_start_dma(struct dcp_async_ctx *actx) 152 { 153 struct dcp *sdcp = global_sdcp; 154 const int chan = actx->chan; 155 uint32_t stat; 156 unsigned long ret; 157 struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan]; 158 159 dma_addr_t desc_phys = dma_map_single(sdcp->dev, desc, sizeof(*desc), 160 DMA_TO_DEVICE); 161 162 reinit_completion(&sdcp->completion[chan]); 163 164 /* Clear status register. */ 165 writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(chan)); 166 167 /* Load the DMA descriptor. */ 168 writel(desc_phys, sdcp->base + MXS_DCP_CH_N_CMDPTR(chan)); 169 170 /* Increment the semaphore to start the DMA transfer. */ 171 writel(1, sdcp->base + MXS_DCP_CH_N_SEMA(chan)); 172 173 ret = wait_for_completion_timeout(&sdcp->completion[chan], 174 msecs_to_jiffies(1000)); 175 if (!ret) { 176 dev_err(sdcp->dev, "Channel %i timeout (DCP_STAT=0x%08x)\n", 177 chan, readl(sdcp->base + MXS_DCP_STAT)); 178 return -ETIMEDOUT; 179 } 180 181 stat = readl(sdcp->base + MXS_DCP_CH_N_STAT(chan)); 182 if (stat & 0xff) { 183 dev_err(sdcp->dev, "Channel %i error (CH_STAT=0x%08x)\n", 184 chan, stat); 185 return -EINVAL; 186 } 187 188 dma_unmap_single(sdcp->dev, desc_phys, sizeof(*desc), DMA_TO_DEVICE); 189 190 return 0; 191 } 192 193 /* 194 * Encryption (AES128) 195 */ 196 static int mxs_dcp_run_aes(struct dcp_async_ctx *actx, 197 struct ablkcipher_request *req, int init) 198 { 199 struct dcp *sdcp = global_sdcp; 200 struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan]; 201 struct dcp_aes_req_ctx *rctx = ablkcipher_request_ctx(req); 202 int ret; 203 204 dma_addr_t key_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_key, 205 2 * AES_KEYSIZE_128, 206 DMA_TO_DEVICE); 207 dma_addr_t src_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_in_buf, 208 DCP_BUF_SZ, DMA_TO_DEVICE); 209 dma_addr_t dst_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_out_buf, 210 DCP_BUF_SZ, DMA_FROM_DEVICE); 211 212 /* Fill in the DMA descriptor. */ 213 desc->control0 = MXS_DCP_CONTROL0_DECR_SEMAPHORE | 214 MXS_DCP_CONTROL0_INTERRUPT | 215 MXS_DCP_CONTROL0_ENABLE_CIPHER; 216 217 /* Payload contains the key. */ 218 desc->control0 |= MXS_DCP_CONTROL0_PAYLOAD_KEY; 219 220 if (rctx->enc) 221 desc->control0 |= MXS_DCP_CONTROL0_CIPHER_ENCRYPT; 222 if (init) 223 desc->control0 |= MXS_DCP_CONTROL0_CIPHER_INIT; 224 225 desc->control1 = MXS_DCP_CONTROL1_CIPHER_SELECT_AES128; 226 227 if (rctx->ecb) 228 desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_ECB; 229 else 230 desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_CBC; 231 232 desc->next_cmd_addr = 0; 233 desc->source = src_phys; 234 desc->destination = dst_phys; 235 desc->size = actx->fill; 236 desc->payload = key_phys; 237 desc->status = 0; 238 239 ret = mxs_dcp_start_dma(actx); 240 241 dma_unmap_single(sdcp->dev, key_phys, 2 * AES_KEYSIZE_128, 242 DMA_TO_DEVICE); 243 dma_unmap_single(sdcp->dev, src_phys, DCP_BUF_SZ, DMA_TO_DEVICE); 244 dma_unmap_single(sdcp->dev, dst_phys, DCP_BUF_SZ, DMA_FROM_DEVICE); 245 246 return ret; 247 } 248 249 static int mxs_dcp_aes_block_crypt(struct crypto_async_request *arq) 250 { 251 struct dcp *sdcp = global_sdcp; 252 253 struct ablkcipher_request *req = ablkcipher_request_cast(arq); 254 struct dcp_async_ctx *actx = crypto_tfm_ctx(arq->tfm); 255 struct dcp_aes_req_ctx *rctx = ablkcipher_request_ctx(req); 256 257 struct scatterlist *dst = req->dst; 258 struct scatterlist *src = req->src; 259 const int nents = sg_nents(req->src); 260 261 const int out_off = DCP_BUF_SZ; 262 uint8_t *in_buf = sdcp->coh->aes_in_buf; 263 uint8_t *out_buf = sdcp->coh->aes_out_buf; 264 265 uint8_t *out_tmp, *src_buf, *dst_buf = NULL; 266 uint32_t dst_off = 0; 267 268 uint8_t *key = sdcp->coh->aes_key; 269 270 int ret = 0; 271 int split = 0; 272 unsigned int i, len, clen, rem = 0; 273 int init = 0; 274 275 actx->fill = 0; 276 277 /* Copy the key from the temporary location. */ 278 memcpy(key, actx->key, actx->key_len); 279 280 if (!rctx->ecb) { 281 /* Copy the CBC IV just past the key. */ 282 memcpy(key + AES_KEYSIZE_128, req->info, AES_KEYSIZE_128); 283 /* CBC needs the INIT set. */ 284 init = 1; 285 } else { 286 memset(key + AES_KEYSIZE_128, 0, AES_KEYSIZE_128); 287 } 288 289 for_each_sg(req->src, src, nents, i) { 290 src_buf = sg_virt(src); 291 len = sg_dma_len(src); 292 293 do { 294 if (actx->fill + len > out_off) 295 clen = out_off - actx->fill; 296 else 297 clen = len; 298 299 memcpy(in_buf + actx->fill, src_buf, clen); 300 len -= clen; 301 src_buf += clen; 302 actx->fill += clen; 303 304 /* 305 * If we filled the buffer or this is the last SG, 306 * submit the buffer. 307 */ 308 if (actx->fill == out_off || sg_is_last(src)) { 309 ret = mxs_dcp_run_aes(actx, req, init); 310 if (ret) 311 return ret; 312 init = 0; 313 314 out_tmp = out_buf; 315 while (dst && actx->fill) { 316 if (!split) { 317 dst_buf = sg_virt(dst); 318 dst_off = 0; 319 } 320 rem = min(sg_dma_len(dst) - dst_off, 321 actx->fill); 322 323 memcpy(dst_buf + dst_off, out_tmp, rem); 324 out_tmp += rem; 325 dst_off += rem; 326 actx->fill -= rem; 327 328 if (dst_off == sg_dma_len(dst)) { 329 dst = sg_next(dst); 330 split = 0; 331 } else { 332 split = 1; 333 } 334 } 335 } 336 } while (len); 337 } 338 339 return ret; 340 } 341 342 static int dcp_chan_thread_aes(void *data) 343 { 344 struct dcp *sdcp = global_sdcp; 345 const int chan = DCP_CHAN_CRYPTO; 346 347 struct crypto_async_request *backlog; 348 struct crypto_async_request *arq; 349 350 int ret; 351 352 do { 353 __set_current_state(TASK_INTERRUPTIBLE); 354 355 mutex_lock(&sdcp->mutex[chan]); 356 backlog = crypto_get_backlog(&sdcp->queue[chan]); 357 arq = crypto_dequeue_request(&sdcp->queue[chan]); 358 mutex_unlock(&sdcp->mutex[chan]); 359 360 if (backlog) 361 backlog->complete(backlog, -EINPROGRESS); 362 363 if (arq) { 364 ret = mxs_dcp_aes_block_crypt(arq); 365 arq->complete(arq, ret); 366 continue; 367 } 368 369 schedule(); 370 } while (!kthread_should_stop()); 371 372 return 0; 373 } 374 375 static int mxs_dcp_block_fallback(struct ablkcipher_request *req, int enc) 376 { 377 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req); 378 struct dcp_async_ctx *ctx = crypto_ablkcipher_ctx(tfm); 379 SYNC_SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback); 380 int ret; 381 382 skcipher_request_set_sync_tfm(subreq, ctx->fallback); 383 skcipher_request_set_callback(subreq, req->base.flags, NULL, NULL); 384 skcipher_request_set_crypt(subreq, req->src, req->dst, 385 req->nbytes, req->info); 386 387 if (enc) 388 ret = crypto_skcipher_encrypt(subreq); 389 else 390 ret = crypto_skcipher_decrypt(subreq); 391 392 skcipher_request_zero(subreq); 393 394 return ret; 395 } 396 397 static int mxs_dcp_aes_enqueue(struct ablkcipher_request *req, int enc, int ecb) 398 { 399 struct dcp *sdcp = global_sdcp; 400 struct crypto_async_request *arq = &req->base; 401 struct dcp_async_ctx *actx = crypto_tfm_ctx(arq->tfm); 402 struct dcp_aes_req_ctx *rctx = ablkcipher_request_ctx(req); 403 int ret; 404 405 if (unlikely(actx->key_len != AES_KEYSIZE_128)) 406 return mxs_dcp_block_fallback(req, enc); 407 408 rctx->enc = enc; 409 rctx->ecb = ecb; 410 actx->chan = DCP_CHAN_CRYPTO; 411 412 mutex_lock(&sdcp->mutex[actx->chan]); 413 ret = crypto_enqueue_request(&sdcp->queue[actx->chan], &req->base); 414 mutex_unlock(&sdcp->mutex[actx->chan]); 415 416 wake_up_process(sdcp->thread[actx->chan]); 417 418 return -EINPROGRESS; 419 } 420 421 static int mxs_dcp_aes_ecb_decrypt(struct ablkcipher_request *req) 422 { 423 return mxs_dcp_aes_enqueue(req, 0, 1); 424 } 425 426 static int mxs_dcp_aes_ecb_encrypt(struct ablkcipher_request *req) 427 { 428 return mxs_dcp_aes_enqueue(req, 1, 1); 429 } 430 431 static int mxs_dcp_aes_cbc_decrypt(struct ablkcipher_request *req) 432 { 433 return mxs_dcp_aes_enqueue(req, 0, 0); 434 } 435 436 static int mxs_dcp_aes_cbc_encrypt(struct ablkcipher_request *req) 437 { 438 return mxs_dcp_aes_enqueue(req, 1, 0); 439 } 440 441 static int mxs_dcp_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key, 442 unsigned int len) 443 { 444 struct dcp_async_ctx *actx = crypto_ablkcipher_ctx(tfm); 445 unsigned int ret; 446 447 /* 448 * AES 128 is supposed by the hardware, store key into temporary 449 * buffer and exit. We must use the temporary buffer here, since 450 * there can still be an operation in progress. 451 */ 452 actx->key_len = len; 453 if (len == AES_KEYSIZE_128) { 454 memcpy(actx->key, key, len); 455 return 0; 456 } 457 458 /* 459 * If the requested AES key size is not supported by the hardware, 460 * but is supported by in-kernel software implementation, we use 461 * software fallback. 462 */ 463 crypto_sync_skcipher_clear_flags(actx->fallback, CRYPTO_TFM_REQ_MASK); 464 crypto_sync_skcipher_set_flags(actx->fallback, 465 tfm->base.crt_flags & CRYPTO_TFM_REQ_MASK); 466 467 ret = crypto_sync_skcipher_setkey(actx->fallback, key, len); 468 if (!ret) 469 return 0; 470 471 tfm->base.crt_flags &= ~CRYPTO_TFM_RES_MASK; 472 tfm->base.crt_flags |= crypto_sync_skcipher_get_flags(actx->fallback) & 473 CRYPTO_TFM_RES_MASK; 474 475 return ret; 476 } 477 478 static int mxs_dcp_aes_fallback_init(struct crypto_tfm *tfm) 479 { 480 const char *name = crypto_tfm_alg_name(tfm); 481 struct dcp_async_ctx *actx = crypto_tfm_ctx(tfm); 482 struct crypto_sync_skcipher *blk; 483 484 blk = crypto_alloc_sync_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK); 485 if (IS_ERR(blk)) 486 return PTR_ERR(blk); 487 488 actx->fallback = blk; 489 tfm->crt_ablkcipher.reqsize = sizeof(struct dcp_aes_req_ctx); 490 return 0; 491 } 492 493 static void mxs_dcp_aes_fallback_exit(struct crypto_tfm *tfm) 494 { 495 struct dcp_async_ctx *actx = crypto_tfm_ctx(tfm); 496 497 crypto_free_sync_skcipher(actx->fallback); 498 } 499 500 /* 501 * Hashing (SHA1/SHA256) 502 */ 503 static int mxs_dcp_run_sha(struct ahash_request *req) 504 { 505 struct dcp *sdcp = global_sdcp; 506 int ret; 507 508 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 509 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm); 510 struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req); 511 struct hash_alg_common *halg = crypto_hash_alg_common(tfm); 512 513 struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan]; 514 515 dma_addr_t digest_phys = 0; 516 dma_addr_t buf_phys = dma_map_single(sdcp->dev, sdcp->coh->sha_in_buf, 517 DCP_BUF_SZ, DMA_TO_DEVICE); 518 519 /* Fill in the DMA descriptor. */ 520 desc->control0 = MXS_DCP_CONTROL0_DECR_SEMAPHORE | 521 MXS_DCP_CONTROL0_INTERRUPT | 522 MXS_DCP_CONTROL0_ENABLE_HASH; 523 if (rctx->init) 524 desc->control0 |= MXS_DCP_CONTROL0_HASH_INIT; 525 526 desc->control1 = actx->alg; 527 desc->next_cmd_addr = 0; 528 desc->source = buf_phys; 529 desc->destination = 0; 530 desc->size = actx->fill; 531 desc->payload = 0; 532 desc->status = 0; 533 534 /* Set HASH_TERM bit for last transfer block. */ 535 if (rctx->fini) { 536 digest_phys = dma_map_single(sdcp->dev, req->result, 537 halg->digestsize, DMA_FROM_DEVICE); 538 desc->control0 |= MXS_DCP_CONTROL0_HASH_TERM; 539 desc->payload = digest_phys; 540 } 541 542 ret = mxs_dcp_start_dma(actx); 543 544 if (rctx->fini) 545 dma_unmap_single(sdcp->dev, digest_phys, halg->digestsize, 546 DMA_FROM_DEVICE); 547 548 dma_unmap_single(sdcp->dev, buf_phys, DCP_BUF_SZ, DMA_TO_DEVICE); 549 550 return ret; 551 } 552 553 static int dcp_sha_req_to_buf(struct crypto_async_request *arq) 554 { 555 struct dcp *sdcp = global_sdcp; 556 557 struct ahash_request *req = ahash_request_cast(arq); 558 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 559 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm); 560 struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req); 561 struct hash_alg_common *halg = crypto_hash_alg_common(tfm); 562 const int nents = sg_nents(req->src); 563 564 uint8_t *in_buf = sdcp->coh->sha_in_buf; 565 566 uint8_t *src_buf; 567 568 struct scatterlist *src; 569 570 unsigned int i, len, clen; 571 int ret; 572 573 int fin = rctx->fini; 574 if (fin) 575 rctx->fini = 0; 576 577 for_each_sg(req->src, src, nents, i) { 578 src_buf = sg_virt(src); 579 len = sg_dma_len(src); 580 581 do { 582 if (actx->fill + len > DCP_BUF_SZ) 583 clen = DCP_BUF_SZ - actx->fill; 584 else 585 clen = len; 586 587 memcpy(in_buf + actx->fill, src_buf, clen); 588 len -= clen; 589 src_buf += clen; 590 actx->fill += clen; 591 592 /* 593 * If we filled the buffer and still have some 594 * more data, submit the buffer. 595 */ 596 if (len && actx->fill == DCP_BUF_SZ) { 597 ret = mxs_dcp_run_sha(req); 598 if (ret) 599 return ret; 600 actx->fill = 0; 601 rctx->init = 0; 602 } 603 } while (len); 604 } 605 606 if (fin) { 607 rctx->fini = 1; 608 609 /* Submit whatever is left. */ 610 if (!req->result) 611 return -EINVAL; 612 613 ret = mxs_dcp_run_sha(req); 614 if (ret) 615 return ret; 616 617 actx->fill = 0; 618 619 /* For some reason, the result is flipped. */ 620 for (i = 0; i < halg->digestsize / 2; i++) { 621 swap(req->result[i], 622 req->result[halg->digestsize - i - 1]); 623 } 624 } 625 626 return 0; 627 } 628 629 static int dcp_chan_thread_sha(void *data) 630 { 631 struct dcp *sdcp = global_sdcp; 632 const int chan = DCP_CHAN_HASH_SHA; 633 634 struct crypto_async_request *backlog; 635 struct crypto_async_request *arq; 636 637 struct dcp_sha_req_ctx *rctx; 638 639 struct ahash_request *req; 640 int ret, fini; 641 642 do { 643 __set_current_state(TASK_INTERRUPTIBLE); 644 645 mutex_lock(&sdcp->mutex[chan]); 646 backlog = crypto_get_backlog(&sdcp->queue[chan]); 647 arq = crypto_dequeue_request(&sdcp->queue[chan]); 648 mutex_unlock(&sdcp->mutex[chan]); 649 650 if (backlog) 651 backlog->complete(backlog, -EINPROGRESS); 652 653 if (arq) { 654 req = ahash_request_cast(arq); 655 rctx = ahash_request_ctx(req); 656 657 ret = dcp_sha_req_to_buf(arq); 658 fini = rctx->fini; 659 arq->complete(arq, ret); 660 if (!fini) 661 continue; 662 } 663 664 schedule(); 665 } while (!kthread_should_stop()); 666 667 return 0; 668 } 669 670 static int dcp_sha_init(struct ahash_request *req) 671 { 672 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 673 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm); 674 675 struct hash_alg_common *halg = crypto_hash_alg_common(tfm); 676 677 /* 678 * Start hashing session. The code below only inits the 679 * hashing session context, nothing more. 680 */ 681 memset(actx, 0, sizeof(*actx)); 682 683 if (strcmp(halg->base.cra_name, "sha1") == 0) 684 actx->alg = MXS_DCP_CONTROL1_HASH_SELECT_SHA1; 685 else 686 actx->alg = MXS_DCP_CONTROL1_HASH_SELECT_SHA256; 687 688 actx->fill = 0; 689 actx->hot = 0; 690 actx->chan = DCP_CHAN_HASH_SHA; 691 692 mutex_init(&actx->mutex); 693 694 return 0; 695 } 696 697 static int dcp_sha_update_fx(struct ahash_request *req, int fini) 698 { 699 struct dcp *sdcp = global_sdcp; 700 701 struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req); 702 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 703 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm); 704 705 int ret; 706 707 /* 708 * Ignore requests that have no data in them and are not 709 * the trailing requests in the stream of requests. 710 */ 711 if (!req->nbytes && !fini) 712 return 0; 713 714 mutex_lock(&actx->mutex); 715 716 rctx->fini = fini; 717 718 if (!actx->hot) { 719 actx->hot = 1; 720 rctx->init = 1; 721 } 722 723 mutex_lock(&sdcp->mutex[actx->chan]); 724 ret = crypto_enqueue_request(&sdcp->queue[actx->chan], &req->base); 725 mutex_unlock(&sdcp->mutex[actx->chan]); 726 727 wake_up_process(sdcp->thread[actx->chan]); 728 mutex_unlock(&actx->mutex); 729 730 return -EINPROGRESS; 731 } 732 733 static int dcp_sha_update(struct ahash_request *req) 734 { 735 return dcp_sha_update_fx(req, 0); 736 } 737 738 static int dcp_sha_final(struct ahash_request *req) 739 { 740 ahash_request_set_crypt(req, NULL, req->result, 0); 741 req->nbytes = 0; 742 return dcp_sha_update_fx(req, 1); 743 } 744 745 static int dcp_sha_finup(struct ahash_request *req) 746 { 747 return dcp_sha_update_fx(req, 1); 748 } 749 750 static int dcp_sha_digest(struct ahash_request *req) 751 { 752 int ret; 753 754 ret = dcp_sha_init(req); 755 if (ret) 756 return ret; 757 758 return dcp_sha_finup(req); 759 } 760 761 static int dcp_sha_noimport(struct ahash_request *req, const void *in) 762 { 763 return -ENOSYS; 764 } 765 766 static int dcp_sha_noexport(struct ahash_request *req, void *out) 767 { 768 return -ENOSYS; 769 } 770 771 static int dcp_sha_cra_init(struct crypto_tfm *tfm) 772 { 773 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), 774 sizeof(struct dcp_sha_req_ctx)); 775 return 0; 776 } 777 778 static void dcp_sha_cra_exit(struct crypto_tfm *tfm) 779 { 780 } 781 782 /* AES 128 ECB and AES 128 CBC */ 783 static struct crypto_alg dcp_aes_algs[] = { 784 { 785 .cra_name = "ecb(aes)", 786 .cra_driver_name = "ecb-aes-dcp", 787 .cra_priority = 400, 788 .cra_alignmask = 15, 789 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 790 CRYPTO_ALG_ASYNC | 791 CRYPTO_ALG_NEED_FALLBACK, 792 .cra_init = mxs_dcp_aes_fallback_init, 793 .cra_exit = mxs_dcp_aes_fallback_exit, 794 .cra_blocksize = AES_BLOCK_SIZE, 795 .cra_ctxsize = sizeof(struct dcp_async_ctx), 796 .cra_type = &crypto_ablkcipher_type, 797 .cra_module = THIS_MODULE, 798 .cra_u = { 799 .ablkcipher = { 800 .min_keysize = AES_MIN_KEY_SIZE, 801 .max_keysize = AES_MAX_KEY_SIZE, 802 .setkey = mxs_dcp_aes_setkey, 803 .encrypt = mxs_dcp_aes_ecb_encrypt, 804 .decrypt = mxs_dcp_aes_ecb_decrypt 805 }, 806 }, 807 }, { 808 .cra_name = "cbc(aes)", 809 .cra_driver_name = "cbc-aes-dcp", 810 .cra_priority = 400, 811 .cra_alignmask = 15, 812 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | 813 CRYPTO_ALG_ASYNC | 814 CRYPTO_ALG_NEED_FALLBACK, 815 .cra_init = mxs_dcp_aes_fallback_init, 816 .cra_exit = mxs_dcp_aes_fallback_exit, 817 .cra_blocksize = AES_BLOCK_SIZE, 818 .cra_ctxsize = sizeof(struct dcp_async_ctx), 819 .cra_type = &crypto_ablkcipher_type, 820 .cra_module = THIS_MODULE, 821 .cra_u = { 822 .ablkcipher = { 823 .min_keysize = AES_MIN_KEY_SIZE, 824 .max_keysize = AES_MAX_KEY_SIZE, 825 .setkey = mxs_dcp_aes_setkey, 826 .encrypt = mxs_dcp_aes_cbc_encrypt, 827 .decrypt = mxs_dcp_aes_cbc_decrypt, 828 .ivsize = AES_BLOCK_SIZE, 829 }, 830 }, 831 }, 832 }; 833 834 /* SHA1 */ 835 static struct ahash_alg dcp_sha1_alg = { 836 .init = dcp_sha_init, 837 .update = dcp_sha_update, 838 .final = dcp_sha_final, 839 .finup = dcp_sha_finup, 840 .digest = dcp_sha_digest, 841 .import = dcp_sha_noimport, 842 .export = dcp_sha_noexport, 843 .halg = { 844 .digestsize = SHA1_DIGEST_SIZE, 845 .base = { 846 .cra_name = "sha1", 847 .cra_driver_name = "sha1-dcp", 848 .cra_priority = 400, 849 .cra_alignmask = 63, 850 .cra_flags = CRYPTO_ALG_ASYNC, 851 .cra_blocksize = SHA1_BLOCK_SIZE, 852 .cra_ctxsize = sizeof(struct dcp_async_ctx), 853 .cra_module = THIS_MODULE, 854 .cra_init = dcp_sha_cra_init, 855 .cra_exit = dcp_sha_cra_exit, 856 }, 857 }, 858 }; 859 860 /* SHA256 */ 861 static struct ahash_alg dcp_sha256_alg = { 862 .init = dcp_sha_init, 863 .update = dcp_sha_update, 864 .final = dcp_sha_final, 865 .finup = dcp_sha_finup, 866 .digest = dcp_sha_digest, 867 .import = dcp_sha_noimport, 868 .export = dcp_sha_noexport, 869 .halg = { 870 .digestsize = SHA256_DIGEST_SIZE, 871 .base = { 872 .cra_name = "sha256", 873 .cra_driver_name = "sha256-dcp", 874 .cra_priority = 400, 875 .cra_alignmask = 63, 876 .cra_flags = CRYPTO_ALG_ASYNC, 877 .cra_blocksize = SHA256_BLOCK_SIZE, 878 .cra_ctxsize = sizeof(struct dcp_async_ctx), 879 .cra_module = THIS_MODULE, 880 .cra_init = dcp_sha_cra_init, 881 .cra_exit = dcp_sha_cra_exit, 882 }, 883 }, 884 }; 885 886 static irqreturn_t mxs_dcp_irq(int irq, void *context) 887 { 888 struct dcp *sdcp = context; 889 uint32_t stat; 890 int i; 891 892 stat = readl(sdcp->base + MXS_DCP_STAT); 893 stat &= MXS_DCP_STAT_IRQ_MASK; 894 if (!stat) 895 return IRQ_NONE; 896 897 /* Clear the interrupts. */ 898 writel(stat, sdcp->base + MXS_DCP_STAT_CLR); 899 900 /* Complete the DMA requests that finished. */ 901 for (i = 0; i < DCP_MAX_CHANS; i++) 902 if (stat & (1 << i)) 903 complete(&sdcp->completion[i]); 904 905 return IRQ_HANDLED; 906 } 907 908 static int mxs_dcp_probe(struct platform_device *pdev) 909 { 910 struct device *dev = &pdev->dev; 911 struct dcp *sdcp = NULL; 912 int i, ret; 913 914 struct resource *iores; 915 int dcp_vmi_irq, dcp_irq; 916 917 if (global_sdcp) { 918 dev_err(dev, "Only one DCP instance allowed!\n"); 919 return -ENODEV; 920 } 921 922 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 923 dcp_vmi_irq = platform_get_irq(pdev, 0); 924 if (dcp_vmi_irq < 0) { 925 dev_err(dev, "Failed to get IRQ: (%d)!\n", dcp_vmi_irq); 926 return dcp_vmi_irq; 927 } 928 929 dcp_irq = platform_get_irq(pdev, 1); 930 if (dcp_irq < 0) { 931 dev_err(dev, "Failed to get IRQ: (%d)!\n", dcp_irq); 932 return dcp_irq; 933 } 934 935 sdcp = devm_kzalloc(dev, sizeof(*sdcp), GFP_KERNEL); 936 if (!sdcp) 937 return -ENOMEM; 938 939 sdcp->dev = dev; 940 sdcp->base = devm_ioremap_resource(dev, iores); 941 if (IS_ERR(sdcp->base)) 942 return PTR_ERR(sdcp->base); 943 944 945 ret = devm_request_irq(dev, dcp_vmi_irq, mxs_dcp_irq, 0, 946 "dcp-vmi-irq", sdcp); 947 if (ret) { 948 dev_err(dev, "Failed to claim DCP VMI IRQ!\n"); 949 return ret; 950 } 951 952 ret = devm_request_irq(dev, dcp_irq, mxs_dcp_irq, 0, 953 "dcp-irq", sdcp); 954 if (ret) { 955 dev_err(dev, "Failed to claim DCP IRQ!\n"); 956 return ret; 957 } 958 959 /* Allocate coherent helper block. */ 960 sdcp->coh = devm_kzalloc(dev, sizeof(*sdcp->coh) + DCP_ALIGNMENT, 961 GFP_KERNEL); 962 if (!sdcp->coh) 963 return -ENOMEM; 964 965 /* Re-align the structure so it fits the DCP constraints. */ 966 sdcp->coh = PTR_ALIGN(sdcp->coh, DCP_ALIGNMENT); 967 968 /* Restart the DCP block. */ 969 ret = stmp_reset_block(sdcp->base); 970 if (ret) 971 return ret; 972 973 /* Initialize control register. */ 974 writel(MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES | 975 MXS_DCP_CTRL_ENABLE_CONTEXT_CACHING | 0xf, 976 sdcp->base + MXS_DCP_CTRL); 977 978 /* Enable all DCP DMA channels. */ 979 writel(MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK, 980 sdcp->base + MXS_DCP_CHANNELCTRL); 981 982 /* 983 * We do not enable context switching. Give the context buffer a 984 * pointer to an illegal address so if context switching is 985 * inadvertantly enabled, the DCP will return an error instead of 986 * trashing good memory. The DCP DMA cannot access ROM, so any ROM 987 * address will do. 988 */ 989 writel(0xffff0000, sdcp->base + MXS_DCP_CONTEXT); 990 for (i = 0; i < DCP_MAX_CHANS; i++) 991 writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(i)); 992 writel(0xffffffff, sdcp->base + MXS_DCP_STAT_CLR); 993 994 global_sdcp = sdcp; 995 996 platform_set_drvdata(pdev, sdcp); 997 998 for (i = 0; i < DCP_MAX_CHANS; i++) { 999 mutex_init(&sdcp->mutex[i]); 1000 init_completion(&sdcp->completion[i]); 1001 crypto_init_queue(&sdcp->queue[i], 50); 1002 } 1003 1004 /* Create the SHA and AES handler threads. */ 1005 sdcp->thread[DCP_CHAN_HASH_SHA] = kthread_run(dcp_chan_thread_sha, 1006 NULL, "mxs_dcp_chan/sha"); 1007 if (IS_ERR(sdcp->thread[DCP_CHAN_HASH_SHA])) { 1008 dev_err(dev, "Error starting SHA thread!\n"); 1009 return PTR_ERR(sdcp->thread[DCP_CHAN_HASH_SHA]); 1010 } 1011 1012 sdcp->thread[DCP_CHAN_CRYPTO] = kthread_run(dcp_chan_thread_aes, 1013 NULL, "mxs_dcp_chan/aes"); 1014 if (IS_ERR(sdcp->thread[DCP_CHAN_CRYPTO])) { 1015 dev_err(dev, "Error starting SHA thread!\n"); 1016 ret = PTR_ERR(sdcp->thread[DCP_CHAN_CRYPTO]); 1017 goto err_destroy_sha_thread; 1018 } 1019 1020 /* Register the various crypto algorithms. */ 1021 sdcp->caps = readl(sdcp->base + MXS_DCP_CAPABILITY1); 1022 1023 if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128) { 1024 ret = crypto_register_algs(dcp_aes_algs, 1025 ARRAY_SIZE(dcp_aes_algs)); 1026 if (ret) { 1027 /* Failed to register algorithm. */ 1028 dev_err(dev, "Failed to register AES crypto!\n"); 1029 goto err_destroy_aes_thread; 1030 } 1031 } 1032 1033 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1) { 1034 ret = crypto_register_ahash(&dcp_sha1_alg); 1035 if (ret) { 1036 dev_err(dev, "Failed to register %s hash!\n", 1037 dcp_sha1_alg.halg.base.cra_name); 1038 goto err_unregister_aes; 1039 } 1040 } 1041 1042 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA256) { 1043 ret = crypto_register_ahash(&dcp_sha256_alg); 1044 if (ret) { 1045 dev_err(dev, "Failed to register %s hash!\n", 1046 dcp_sha256_alg.halg.base.cra_name); 1047 goto err_unregister_sha1; 1048 } 1049 } 1050 1051 return 0; 1052 1053 err_unregister_sha1: 1054 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1) 1055 crypto_unregister_ahash(&dcp_sha1_alg); 1056 1057 err_unregister_aes: 1058 if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128) 1059 crypto_unregister_algs(dcp_aes_algs, ARRAY_SIZE(dcp_aes_algs)); 1060 1061 err_destroy_aes_thread: 1062 kthread_stop(sdcp->thread[DCP_CHAN_CRYPTO]); 1063 1064 err_destroy_sha_thread: 1065 kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]); 1066 return ret; 1067 } 1068 1069 static int mxs_dcp_remove(struct platform_device *pdev) 1070 { 1071 struct dcp *sdcp = platform_get_drvdata(pdev); 1072 1073 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA256) 1074 crypto_unregister_ahash(&dcp_sha256_alg); 1075 1076 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1) 1077 crypto_unregister_ahash(&dcp_sha1_alg); 1078 1079 if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128) 1080 crypto_unregister_algs(dcp_aes_algs, ARRAY_SIZE(dcp_aes_algs)); 1081 1082 kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]); 1083 kthread_stop(sdcp->thread[DCP_CHAN_CRYPTO]); 1084 1085 platform_set_drvdata(pdev, NULL); 1086 1087 global_sdcp = NULL; 1088 1089 return 0; 1090 } 1091 1092 static const struct of_device_id mxs_dcp_dt_ids[] = { 1093 { .compatible = "fsl,imx23-dcp", .data = NULL, }, 1094 { .compatible = "fsl,imx28-dcp", .data = NULL, }, 1095 { /* sentinel */ } 1096 }; 1097 1098 MODULE_DEVICE_TABLE(of, mxs_dcp_dt_ids); 1099 1100 static struct platform_driver mxs_dcp_driver = { 1101 .probe = mxs_dcp_probe, 1102 .remove = mxs_dcp_remove, 1103 .driver = { 1104 .name = "mxs-dcp", 1105 .of_match_table = mxs_dcp_dt_ids, 1106 }, 1107 }; 1108 1109 module_platform_driver(mxs_dcp_driver); 1110 1111 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 1112 MODULE_DESCRIPTION("Freescale MXS DCP Driver"); 1113 MODULE_LICENSE("GPL"); 1114 MODULE_ALIAS("platform:mxs-dcp"); 1115