1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Freescale i.MX23/i.MX28 Data Co-Processor driver 4 * 5 * Copyright (C) 2013 Marek Vasut <marex@denx.de> 6 */ 7 8 #include <linux/dma-mapping.h> 9 #include <linux/interrupt.h> 10 #include <linux/io.h> 11 #include <linux/kernel.h> 12 #include <linux/kthread.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/stmp_device.h> 17 #include <linux/clk.h> 18 #include <soc/fsl/dcp.h> 19 20 #include <crypto/aes.h> 21 #include <crypto/sha1.h> 22 #include <crypto/sha2.h> 23 #include <crypto/internal/hash.h> 24 #include <crypto/internal/skcipher.h> 25 #include <crypto/scatterwalk.h> 26 27 #define DCP_MAX_CHANS 4 28 #define DCP_BUF_SZ PAGE_SIZE 29 #define DCP_SHA_PAY_SZ 64 30 31 #define DCP_ALIGNMENT 64 32 33 /* 34 * Null hashes to align with hw behavior on imx6sl and ull 35 * these are flipped for consistency with hw output 36 */ 37 static const uint8_t sha1_null_hash[] = 38 "\x09\x07\xd8\xaf\x90\x18\x60\x95\xef\xbf" 39 "\x55\x32\x0d\x4b\x6b\x5e\xee\xa3\x39\xda"; 40 41 static const uint8_t sha256_null_hash[] = 42 "\x55\xb8\x52\x78\x1b\x99\x95\xa4" 43 "\x4c\x93\x9b\x64\xe4\x41\xae\x27" 44 "\x24\xb9\x6f\x99\xc8\xf4\xfb\x9a" 45 "\x14\x1c\xfc\x98\x42\xc4\xb0\xe3"; 46 47 /* DCP DMA descriptor. */ 48 struct dcp_dma_desc { 49 uint32_t next_cmd_addr; 50 uint32_t control0; 51 uint32_t control1; 52 uint32_t source; 53 uint32_t destination; 54 uint32_t size; 55 uint32_t payload; 56 uint32_t status; 57 }; 58 59 /* Coherent aligned block for bounce buffering. */ 60 struct dcp_coherent_block { 61 uint8_t aes_in_buf[DCP_BUF_SZ]; 62 uint8_t aes_out_buf[DCP_BUF_SZ]; 63 uint8_t sha_in_buf[DCP_BUF_SZ]; 64 uint8_t sha_out_buf[DCP_SHA_PAY_SZ]; 65 66 uint8_t aes_key[2 * AES_KEYSIZE_128]; 67 68 struct dcp_dma_desc desc[DCP_MAX_CHANS]; 69 }; 70 71 struct dcp { 72 struct device *dev; 73 void __iomem *base; 74 75 uint32_t caps; 76 77 struct dcp_coherent_block *coh; 78 79 struct completion completion[DCP_MAX_CHANS]; 80 spinlock_t lock[DCP_MAX_CHANS]; 81 struct task_struct *thread[DCP_MAX_CHANS]; 82 struct crypto_queue queue[DCP_MAX_CHANS]; 83 struct clk *dcp_clk; 84 }; 85 86 enum dcp_chan { 87 DCP_CHAN_HASH_SHA = 0, 88 DCP_CHAN_CRYPTO = 2, 89 }; 90 91 struct dcp_async_ctx { 92 /* Common context */ 93 enum dcp_chan chan; 94 uint32_t fill; 95 96 /* SHA Hash-specific context */ 97 struct mutex mutex; 98 uint32_t alg; 99 unsigned int hot:1; 100 101 /* Crypto-specific context */ 102 struct crypto_skcipher *fallback; 103 unsigned int key_len; 104 uint8_t key[AES_KEYSIZE_128]; 105 bool key_referenced; 106 }; 107 108 struct dcp_aes_req_ctx { 109 unsigned int enc:1; 110 unsigned int ecb:1; 111 struct skcipher_request fallback_req; // keep at the end 112 }; 113 114 struct dcp_sha_req_ctx { 115 unsigned int init:1; 116 unsigned int fini:1; 117 }; 118 119 struct dcp_export_state { 120 struct dcp_sha_req_ctx req_ctx; 121 struct dcp_async_ctx async_ctx; 122 }; 123 124 /* 125 * There can even be only one instance of the MXS DCP due to the 126 * design of Linux Crypto API. 127 */ 128 static struct dcp *global_sdcp; 129 130 /* DCP register layout. */ 131 #define MXS_DCP_CTRL 0x00 132 #define MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES (1 << 23) 133 #define MXS_DCP_CTRL_ENABLE_CONTEXT_CACHING (1 << 22) 134 135 #define MXS_DCP_STAT 0x10 136 #define MXS_DCP_STAT_CLR 0x18 137 #define MXS_DCP_STAT_IRQ_MASK 0xf 138 139 #define MXS_DCP_CHANNELCTRL 0x20 140 #define MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK 0xff 141 142 #define MXS_DCP_CAPABILITY1 0x40 143 #define MXS_DCP_CAPABILITY1_SHA256 (4 << 16) 144 #define MXS_DCP_CAPABILITY1_SHA1 (1 << 16) 145 #define MXS_DCP_CAPABILITY1_AES128 (1 << 0) 146 147 #define MXS_DCP_CONTEXT 0x50 148 149 #define MXS_DCP_CH_N_CMDPTR(n) (0x100 + ((n) * 0x40)) 150 151 #define MXS_DCP_CH_N_SEMA(n) (0x110 + ((n) * 0x40)) 152 153 #define MXS_DCP_CH_N_STAT(n) (0x120 + ((n) * 0x40)) 154 #define MXS_DCP_CH_N_STAT_CLR(n) (0x128 + ((n) * 0x40)) 155 156 /* DMA descriptor bits. */ 157 #define MXS_DCP_CONTROL0_HASH_TERM (1 << 13) 158 #define MXS_DCP_CONTROL0_HASH_INIT (1 << 12) 159 #define MXS_DCP_CONTROL0_PAYLOAD_KEY (1 << 11) 160 #define MXS_DCP_CONTROL0_OTP_KEY (1 << 10) 161 #define MXS_DCP_CONTROL0_CIPHER_ENCRYPT (1 << 8) 162 #define MXS_DCP_CONTROL0_CIPHER_INIT (1 << 9) 163 #define MXS_DCP_CONTROL0_ENABLE_HASH (1 << 6) 164 #define MXS_DCP_CONTROL0_ENABLE_CIPHER (1 << 5) 165 #define MXS_DCP_CONTROL0_DECR_SEMAPHORE (1 << 1) 166 #define MXS_DCP_CONTROL0_INTERRUPT (1 << 0) 167 168 #define MXS_DCP_CONTROL1_HASH_SELECT_SHA256 (2 << 16) 169 #define MXS_DCP_CONTROL1_HASH_SELECT_SHA1 (0 << 16) 170 #define MXS_DCP_CONTROL1_CIPHER_MODE_CBC (1 << 4) 171 #define MXS_DCP_CONTROL1_CIPHER_MODE_ECB (0 << 4) 172 #define MXS_DCP_CONTROL1_CIPHER_SELECT_AES128 (0 << 0) 173 174 #define MXS_DCP_CONTROL1_KEY_SELECT_SHIFT 8 175 176 static int mxs_dcp_start_dma(struct dcp_async_ctx *actx) 177 { 178 int dma_err; 179 struct dcp *sdcp = global_sdcp; 180 const int chan = actx->chan; 181 uint32_t stat; 182 unsigned long ret; 183 struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan]; 184 dma_addr_t desc_phys = dma_map_single(sdcp->dev, desc, sizeof(*desc), 185 DMA_TO_DEVICE); 186 187 dma_err = dma_mapping_error(sdcp->dev, desc_phys); 188 if (dma_err) 189 return dma_err; 190 191 reinit_completion(&sdcp->completion[chan]); 192 193 /* Clear status register. */ 194 writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(chan)); 195 196 /* Load the DMA descriptor. */ 197 writel(desc_phys, sdcp->base + MXS_DCP_CH_N_CMDPTR(chan)); 198 199 /* Increment the semaphore to start the DMA transfer. */ 200 writel(1, sdcp->base + MXS_DCP_CH_N_SEMA(chan)); 201 202 ret = wait_for_completion_timeout(&sdcp->completion[chan], 203 msecs_to_jiffies(1000)); 204 if (!ret) { 205 dev_err(sdcp->dev, "Channel %i timeout (DCP_STAT=0x%08x)\n", 206 chan, readl(sdcp->base + MXS_DCP_STAT)); 207 return -ETIMEDOUT; 208 } 209 210 stat = readl(sdcp->base + MXS_DCP_CH_N_STAT(chan)); 211 if (stat & 0xff) { 212 dev_err(sdcp->dev, "Channel %i error (CH_STAT=0x%08x)\n", 213 chan, stat); 214 return -EINVAL; 215 } 216 217 dma_unmap_single(sdcp->dev, desc_phys, sizeof(*desc), DMA_TO_DEVICE); 218 219 return 0; 220 } 221 222 /* 223 * Encryption (AES128) 224 */ 225 static int mxs_dcp_run_aes(struct dcp_async_ctx *actx, 226 struct skcipher_request *req, int init) 227 { 228 dma_addr_t key_phys, src_phys, dst_phys; 229 struct dcp *sdcp = global_sdcp; 230 struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan]; 231 struct dcp_aes_req_ctx *rctx = skcipher_request_ctx(req); 232 bool key_referenced = actx->key_referenced; 233 int ret; 234 235 if (key_referenced) 236 key_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_key + AES_KEYSIZE_128, 237 AES_KEYSIZE_128, DMA_TO_DEVICE); 238 else 239 key_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_key, 240 2 * AES_KEYSIZE_128, DMA_TO_DEVICE); 241 ret = dma_mapping_error(sdcp->dev, key_phys); 242 if (ret) 243 return ret; 244 245 src_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_in_buf, 246 DCP_BUF_SZ, DMA_TO_DEVICE); 247 ret = dma_mapping_error(sdcp->dev, src_phys); 248 if (ret) 249 goto err_src; 250 251 dst_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_out_buf, 252 DCP_BUF_SZ, DMA_FROM_DEVICE); 253 ret = dma_mapping_error(sdcp->dev, dst_phys); 254 if (ret) 255 goto err_dst; 256 257 if (actx->fill % AES_BLOCK_SIZE) { 258 dev_err(sdcp->dev, "Invalid block size!\n"); 259 ret = -EINVAL; 260 goto aes_done_run; 261 } 262 263 /* Fill in the DMA descriptor. */ 264 desc->control0 = MXS_DCP_CONTROL0_DECR_SEMAPHORE | 265 MXS_DCP_CONTROL0_INTERRUPT | 266 MXS_DCP_CONTROL0_ENABLE_CIPHER; 267 268 if (!key_referenced) 269 /* Payload contains the key. */ 270 desc->control0 |= MXS_DCP_CONTROL0_PAYLOAD_KEY; 271 else if (actx->key[0] == DCP_PAES_KEY_OTP) 272 /* Set OTP key bit to select the key via KEY_SELECT. */ 273 desc->control0 |= MXS_DCP_CONTROL0_OTP_KEY; 274 275 if (rctx->enc) 276 desc->control0 |= MXS_DCP_CONTROL0_CIPHER_ENCRYPT; 277 if (init) 278 desc->control0 |= MXS_DCP_CONTROL0_CIPHER_INIT; 279 280 desc->control1 = MXS_DCP_CONTROL1_CIPHER_SELECT_AES128; 281 282 if (rctx->ecb) 283 desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_ECB; 284 else 285 desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_CBC; 286 287 if (key_referenced) 288 desc->control1 |= sdcp->coh->aes_key[0] << MXS_DCP_CONTROL1_KEY_SELECT_SHIFT; 289 290 desc->next_cmd_addr = 0; 291 desc->source = src_phys; 292 desc->destination = dst_phys; 293 desc->size = actx->fill; 294 desc->payload = key_phys; 295 desc->status = 0; 296 297 ret = mxs_dcp_start_dma(actx); 298 299 aes_done_run: 300 dma_unmap_single(sdcp->dev, dst_phys, DCP_BUF_SZ, DMA_FROM_DEVICE); 301 err_dst: 302 dma_unmap_single(sdcp->dev, src_phys, DCP_BUF_SZ, DMA_TO_DEVICE); 303 err_src: 304 if (key_referenced) 305 dma_unmap_single(sdcp->dev, key_phys, AES_KEYSIZE_128, 306 DMA_TO_DEVICE); 307 else 308 dma_unmap_single(sdcp->dev, key_phys, 2 * AES_KEYSIZE_128, 309 DMA_TO_DEVICE); 310 return ret; 311 } 312 313 static int mxs_dcp_aes_block_crypt(struct crypto_async_request *arq) 314 { 315 struct dcp *sdcp = global_sdcp; 316 317 struct skcipher_request *req = skcipher_request_cast(arq); 318 struct dcp_async_ctx *actx = crypto_tfm_ctx(arq->tfm); 319 struct dcp_aes_req_ctx *rctx = skcipher_request_ctx(req); 320 321 struct scatterlist *dst = req->dst; 322 struct scatterlist *src = req->src; 323 int dst_nents = sg_nents(dst); 324 325 const int out_off = DCP_BUF_SZ; 326 uint8_t *in_buf = sdcp->coh->aes_in_buf; 327 uint8_t *out_buf = sdcp->coh->aes_out_buf; 328 329 uint32_t dst_off = 0; 330 uint8_t *src_buf = NULL; 331 uint32_t last_out_len = 0; 332 333 uint8_t *key = sdcp->coh->aes_key; 334 335 int ret = 0; 336 unsigned int i, len, clen, tlen = 0; 337 int init = 0; 338 bool limit_hit = false; 339 340 actx->fill = 0; 341 342 /* Copy the key from the temporary location. */ 343 memcpy(key, actx->key, actx->key_len); 344 345 if (!rctx->ecb) { 346 /* Copy the CBC IV just past the key. */ 347 memcpy(key + AES_KEYSIZE_128, req->iv, AES_KEYSIZE_128); 348 /* CBC needs the INIT set. */ 349 init = 1; 350 } else { 351 memset(key + AES_KEYSIZE_128, 0, AES_KEYSIZE_128); 352 } 353 354 for_each_sg(req->src, src, sg_nents(req->src), i) { 355 src_buf = sg_virt(src); 356 len = src->length; 357 tlen += len; 358 limit_hit = tlen > req->cryptlen; 359 360 if (limit_hit) 361 len = req->cryptlen - (tlen - len); 362 363 do { 364 if (actx->fill + len > out_off) 365 clen = out_off - actx->fill; 366 else 367 clen = len; 368 369 memcpy(in_buf + actx->fill, src_buf, clen); 370 len -= clen; 371 src_buf += clen; 372 actx->fill += clen; 373 374 /* 375 * If we filled the buffer or this is the last SG, 376 * submit the buffer. 377 */ 378 if (actx->fill == out_off || sg_is_last(src) || 379 limit_hit) { 380 ret = mxs_dcp_run_aes(actx, req, init); 381 if (ret) 382 return ret; 383 init = 0; 384 385 sg_pcopy_from_buffer(dst, dst_nents, out_buf, 386 actx->fill, dst_off); 387 dst_off += actx->fill; 388 last_out_len = actx->fill; 389 actx->fill = 0; 390 } 391 } while (len); 392 393 if (limit_hit) 394 break; 395 } 396 397 /* Copy the IV for CBC for chaining */ 398 if (!rctx->ecb) { 399 if (rctx->enc) 400 memcpy(req->iv, out_buf+(last_out_len-AES_BLOCK_SIZE), 401 AES_BLOCK_SIZE); 402 else 403 memcpy(req->iv, in_buf+(last_out_len-AES_BLOCK_SIZE), 404 AES_BLOCK_SIZE); 405 } 406 407 return ret; 408 } 409 410 static int dcp_chan_thread_aes(void *data) 411 { 412 struct dcp *sdcp = global_sdcp; 413 const int chan = DCP_CHAN_CRYPTO; 414 415 struct crypto_async_request *backlog; 416 struct crypto_async_request *arq; 417 418 int ret; 419 420 while (!kthread_should_stop()) { 421 set_current_state(TASK_INTERRUPTIBLE); 422 423 spin_lock(&sdcp->lock[chan]); 424 backlog = crypto_get_backlog(&sdcp->queue[chan]); 425 arq = crypto_dequeue_request(&sdcp->queue[chan]); 426 spin_unlock(&sdcp->lock[chan]); 427 428 if (!backlog && !arq) { 429 schedule(); 430 continue; 431 } 432 433 set_current_state(TASK_RUNNING); 434 435 if (backlog) 436 crypto_request_complete(backlog, -EINPROGRESS); 437 438 if (arq) { 439 ret = mxs_dcp_aes_block_crypt(arq); 440 crypto_request_complete(arq, ret); 441 } 442 } 443 444 return 0; 445 } 446 447 static int mxs_dcp_block_fallback(struct skcipher_request *req, int enc) 448 { 449 struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); 450 struct dcp_aes_req_ctx *rctx = skcipher_request_ctx(req); 451 struct dcp_async_ctx *ctx = crypto_skcipher_ctx(tfm); 452 int ret; 453 454 skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback); 455 skcipher_request_set_callback(&rctx->fallback_req, req->base.flags, 456 req->base.complete, req->base.data); 457 skcipher_request_set_crypt(&rctx->fallback_req, req->src, req->dst, 458 req->cryptlen, req->iv); 459 460 if (enc) 461 ret = crypto_skcipher_encrypt(&rctx->fallback_req); 462 else 463 ret = crypto_skcipher_decrypt(&rctx->fallback_req); 464 465 return ret; 466 } 467 468 static int mxs_dcp_aes_enqueue(struct skcipher_request *req, int enc, int ecb) 469 { 470 struct dcp *sdcp = global_sdcp; 471 struct crypto_async_request *arq = &req->base; 472 struct dcp_async_ctx *actx = crypto_tfm_ctx(arq->tfm); 473 struct dcp_aes_req_ctx *rctx = skcipher_request_ctx(req); 474 int ret; 475 476 if (!req->cryptlen) 477 return 0; 478 479 if (unlikely(actx->key_len != AES_KEYSIZE_128 && !actx->key_referenced)) 480 return mxs_dcp_block_fallback(req, enc); 481 482 rctx->enc = enc; 483 rctx->ecb = ecb; 484 actx->chan = DCP_CHAN_CRYPTO; 485 486 spin_lock(&sdcp->lock[actx->chan]); 487 ret = crypto_enqueue_request(&sdcp->queue[actx->chan], &req->base); 488 spin_unlock(&sdcp->lock[actx->chan]); 489 490 wake_up_process(sdcp->thread[actx->chan]); 491 492 return ret; 493 } 494 495 static int mxs_dcp_aes_ecb_decrypt(struct skcipher_request *req) 496 { 497 return mxs_dcp_aes_enqueue(req, 0, 1); 498 } 499 500 static int mxs_dcp_aes_ecb_encrypt(struct skcipher_request *req) 501 { 502 return mxs_dcp_aes_enqueue(req, 1, 1); 503 } 504 505 static int mxs_dcp_aes_cbc_decrypt(struct skcipher_request *req) 506 { 507 return mxs_dcp_aes_enqueue(req, 0, 0); 508 } 509 510 static int mxs_dcp_aes_cbc_encrypt(struct skcipher_request *req) 511 { 512 return mxs_dcp_aes_enqueue(req, 1, 0); 513 } 514 515 static int mxs_dcp_aes_setkey(struct crypto_skcipher *tfm, const u8 *key, 516 unsigned int len) 517 { 518 struct dcp_async_ctx *actx = crypto_skcipher_ctx(tfm); 519 520 /* 521 * AES 128 is supposed by the hardware, store key into temporary 522 * buffer and exit. We must use the temporary buffer here, since 523 * there can still be an operation in progress. 524 */ 525 actx->key_len = len; 526 actx->key_referenced = false; 527 if (len == AES_KEYSIZE_128) { 528 memcpy(actx->key, key, len); 529 return 0; 530 } 531 532 /* 533 * If the requested AES key size is not supported by the hardware, 534 * but is supported by in-kernel software implementation, we use 535 * software fallback. 536 */ 537 crypto_skcipher_clear_flags(actx->fallback, CRYPTO_TFM_REQ_MASK); 538 crypto_skcipher_set_flags(actx->fallback, 539 tfm->base.crt_flags & CRYPTO_TFM_REQ_MASK); 540 return crypto_skcipher_setkey(actx->fallback, key, len); 541 } 542 543 static int mxs_dcp_aes_setrefkey(struct crypto_skcipher *tfm, const u8 *key, 544 unsigned int len) 545 { 546 struct dcp_async_ctx *actx = crypto_skcipher_ctx(tfm); 547 548 if (len != DCP_PAES_KEYSIZE) 549 return -EINVAL; 550 551 switch (key[0]) { 552 case DCP_PAES_KEY_SLOT0: 553 case DCP_PAES_KEY_SLOT1: 554 case DCP_PAES_KEY_SLOT2: 555 case DCP_PAES_KEY_SLOT3: 556 case DCP_PAES_KEY_UNIQUE: 557 case DCP_PAES_KEY_OTP: 558 memcpy(actx->key, key, len); 559 actx->key_len = len; 560 actx->key_referenced = true; 561 break; 562 default: 563 return -EINVAL; 564 } 565 566 return 0; 567 } 568 569 static int mxs_dcp_aes_fallback_init_tfm(struct crypto_skcipher *tfm) 570 { 571 const char *name = crypto_tfm_alg_name(crypto_skcipher_tfm(tfm)); 572 struct dcp_async_ctx *actx = crypto_skcipher_ctx(tfm); 573 struct crypto_skcipher *blk; 574 575 blk = crypto_alloc_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK); 576 if (IS_ERR(blk)) 577 return PTR_ERR(blk); 578 579 actx->fallback = blk; 580 crypto_skcipher_set_reqsize(tfm, sizeof(struct dcp_aes_req_ctx) + 581 crypto_skcipher_reqsize(blk)); 582 return 0; 583 } 584 585 static void mxs_dcp_aes_fallback_exit_tfm(struct crypto_skcipher *tfm) 586 { 587 struct dcp_async_ctx *actx = crypto_skcipher_ctx(tfm); 588 589 crypto_free_skcipher(actx->fallback); 590 } 591 592 static int mxs_dcp_paes_init_tfm(struct crypto_skcipher *tfm) 593 { 594 crypto_skcipher_set_reqsize(tfm, sizeof(struct dcp_aes_req_ctx)); 595 596 return 0; 597 } 598 599 /* 600 * Hashing (SHA1/SHA256) 601 */ 602 static int mxs_dcp_run_sha(struct ahash_request *req) 603 { 604 struct dcp *sdcp = global_sdcp; 605 int ret; 606 607 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 608 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm); 609 struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req); 610 struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan]; 611 612 dma_addr_t digest_phys = 0; 613 dma_addr_t buf_phys = dma_map_single(sdcp->dev, sdcp->coh->sha_in_buf, 614 DCP_BUF_SZ, DMA_TO_DEVICE); 615 616 ret = dma_mapping_error(sdcp->dev, buf_phys); 617 if (ret) 618 return ret; 619 620 /* Fill in the DMA descriptor. */ 621 desc->control0 = MXS_DCP_CONTROL0_DECR_SEMAPHORE | 622 MXS_DCP_CONTROL0_INTERRUPT | 623 MXS_DCP_CONTROL0_ENABLE_HASH; 624 if (rctx->init) 625 desc->control0 |= MXS_DCP_CONTROL0_HASH_INIT; 626 627 desc->control1 = actx->alg; 628 desc->next_cmd_addr = 0; 629 desc->source = buf_phys; 630 desc->destination = 0; 631 desc->size = actx->fill; 632 desc->payload = 0; 633 desc->status = 0; 634 635 /* 636 * Align driver with hw behavior when generating null hashes 637 */ 638 if (rctx->init && rctx->fini && desc->size == 0) { 639 struct hash_alg_common *halg = crypto_hash_alg_common(tfm); 640 const uint8_t *sha_buf = 641 (actx->alg == MXS_DCP_CONTROL1_HASH_SELECT_SHA1) ? 642 sha1_null_hash : sha256_null_hash; 643 memcpy(sdcp->coh->sha_out_buf, sha_buf, halg->digestsize); 644 ret = 0; 645 goto done_run; 646 } 647 648 /* Set HASH_TERM bit for last transfer block. */ 649 if (rctx->fini) { 650 digest_phys = dma_map_single(sdcp->dev, sdcp->coh->sha_out_buf, 651 DCP_SHA_PAY_SZ, DMA_FROM_DEVICE); 652 ret = dma_mapping_error(sdcp->dev, digest_phys); 653 if (ret) 654 goto done_run; 655 656 desc->control0 |= MXS_DCP_CONTROL0_HASH_TERM; 657 desc->payload = digest_phys; 658 } 659 660 ret = mxs_dcp_start_dma(actx); 661 662 if (rctx->fini) 663 dma_unmap_single(sdcp->dev, digest_phys, DCP_SHA_PAY_SZ, 664 DMA_FROM_DEVICE); 665 666 done_run: 667 dma_unmap_single(sdcp->dev, buf_phys, DCP_BUF_SZ, DMA_TO_DEVICE); 668 669 return ret; 670 } 671 672 static int dcp_sha_req_to_buf(struct crypto_async_request *arq) 673 { 674 struct dcp *sdcp = global_sdcp; 675 676 struct ahash_request *req = ahash_request_cast(arq); 677 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 678 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm); 679 struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req); 680 struct hash_alg_common *halg = crypto_hash_alg_common(tfm); 681 682 uint8_t *in_buf = sdcp->coh->sha_in_buf; 683 uint8_t *out_buf = sdcp->coh->sha_out_buf; 684 685 struct scatterlist *src; 686 687 unsigned int i, len, clen, oft = 0; 688 int ret; 689 690 int fin = rctx->fini; 691 if (fin) 692 rctx->fini = 0; 693 694 src = req->src; 695 len = req->nbytes; 696 697 while (len) { 698 if (actx->fill + len > DCP_BUF_SZ) 699 clen = DCP_BUF_SZ - actx->fill; 700 else 701 clen = len; 702 703 scatterwalk_map_and_copy(in_buf + actx->fill, src, oft, clen, 704 0); 705 706 len -= clen; 707 oft += clen; 708 actx->fill += clen; 709 710 /* 711 * If we filled the buffer and still have some 712 * more data, submit the buffer. 713 */ 714 if (len && actx->fill == DCP_BUF_SZ) { 715 ret = mxs_dcp_run_sha(req); 716 if (ret) 717 return ret; 718 actx->fill = 0; 719 rctx->init = 0; 720 } 721 } 722 723 if (fin) { 724 rctx->fini = 1; 725 726 /* Submit whatever is left. */ 727 if (!req->result) 728 return -EINVAL; 729 730 ret = mxs_dcp_run_sha(req); 731 if (ret) 732 return ret; 733 734 actx->fill = 0; 735 736 /* For some reason the result is flipped */ 737 for (i = 0; i < halg->digestsize; i++) 738 req->result[i] = out_buf[halg->digestsize - i - 1]; 739 } 740 741 return 0; 742 } 743 744 static int dcp_chan_thread_sha(void *data) 745 { 746 struct dcp *sdcp = global_sdcp; 747 const int chan = DCP_CHAN_HASH_SHA; 748 749 struct crypto_async_request *backlog; 750 struct crypto_async_request *arq; 751 int ret; 752 753 while (!kthread_should_stop()) { 754 set_current_state(TASK_INTERRUPTIBLE); 755 756 spin_lock(&sdcp->lock[chan]); 757 backlog = crypto_get_backlog(&sdcp->queue[chan]); 758 arq = crypto_dequeue_request(&sdcp->queue[chan]); 759 spin_unlock(&sdcp->lock[chan]); 760 761 if (!backlog && !arq) { 762 schedule(); 763 continue; 764 } 765 766 set_current_state(TASK_RUNNING); 767 768 if (backlog) 769 crypto_request_complete(backlog, -EINPROGRESS); 770 771 if (arq) { 772 ret = dcp_sha_req_to_buf(arq); 773 crypto_request_complete(arq, ret); 774 } 775 } 776 777 return 0; 778 } 779 780 static int dcp_sha_init(struct ahash_request *req) 781 { 782 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 783 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm); 784 785 struct hash_alg_common *halg = crypto_hash_alg_common(tfm); 786 787 /* 788 * Start hashing session. The code below only inits the 789 * hashing session context, nothing more. 790 */ 791 memset(actx, 0, sizeof(*actx)); 792 793 if (strcmp(halg->base.cra_name, "sha1") == 0) 794 actx->alg = MXS_DCP_CONTROL1_HASH_SELECT_SHA1; 795 else 796 actx->alg = MXS_DCP_CONTROL1_HASH_SELECT_SHA256; 797 798 actx->fill = 0; 799 actx->hot = 0; 800 actx->chan = DCP_CHAN_HASH_SHA; 801 802 mutex_init(&actx->mutex); 803 804 return 0; 805 } 806 807 static int dcp_sha_update_fx(struct ahash_request *req, int fini) 808 { 809 struct dcp *sdcp = global_sdcp; 810 811 struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req); 812 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 813 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm); 814 815 int ret; 816 817 /* 818 * Ignore requests that have no data in them and are not 819 * the trailing requests in the stream of requests. 820 */ 821 if (!req->nbytes && !fini) 822 return 0; 823 824 mutex_lock(&actx->mutex); 825 826 rctx->fini = fini; 827 828 if (!actx->hot) { 829 actx->hot = 1; 830 rctx->init = 1; 831 } 832 833 spin_lock(&sdcp->lock[actx->chan]); 834 ret = crypto_enqueue_request(&sdcp->queue[actx->chan], &req->base); 835 spin_unlock(&sdcp->lock[actx->chan]); 836 837 wake_up_process(sdcp->thread[actx->chan]); 838 mutex_unlock(&actx->mutex); 839 840 return ret; 841 } 842 843 static int dcp_sha_update(struct ahash_request *req) 844 { 845 return dcp_sha_update_fx(req, 0); 846 } 847 848 static int dcp_sha_final(struct ahash_request *req) 849 { 850 ahash_request_set_crypt(req, NULL, req->result, 0); 851 req->nbytes = 0; 852 return dcp_sha_update_fx(req, 1); 853 } 854 855 static int dcp_sha_finup(struct ahash_request *req) 856 { 857 return dcp_sha_update_fx(req, 1); 858 } 859 860 static int dcp_sha_digest(struct ahash_request *req) 861 { 862 int ret; 863 864 ret = dcp_sha_init(req); 865 if (ret) 866 return ret; 867 868 return dcp_sha_finup(req); 869 } 870 871 static int dcp_sha_import(struct ahash_request *req, const void *in) 872 { 873 struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req); 874 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 875 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm); 876 const struct dcp_export_state *export = in; 877 878 memset(rctx, 0, sizeof(struct dcp_sha_req_ctx)); 879 memset(actx, 0, sizeof(struct dcp_async_ctx)); 880 memcpy(rctx, &export->req_ctx, sizeof(struct dcp_sha_req_ctx)); 881 memcpy(actx, &export->async_ctx, sizeof(struct dcp_async_ctx)); 882 883 return 0; 884 } 885 886 static int dcp_sha_export(struct ahash_request *req, void *out) 887 { 888 struct dcp_sha_req_ctx *rctx_state = ahash_request_ctx(req); 889 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 890 struct dcp_async_ctx *actx_state = crypto_ahash_ctx(tfm); 891 struct dcp_export_state *export = out; 892 893 memcpy(&export->req_ctx, rctx_state, sizeof(struct dcp_sha_req_ctx)); 894 memcpy(&export->async_ctx, actx_state, sizeof(struct dcp_async_ctx)); 895 896 return 0; 897 } 898 899 static int dcp_sha_cra_init(struct crypto_tfm *tfm) 900 { 901 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), 902 sizeof(struct dcp_sha_req_ctx)); 903 return 0; 904 } 905 906 static void dcp_sha_cra_exit(struct crypto_tfm *tfm) 907 { 908 } 909 910 /* AES 128 ECB and AES 128 CBC */ 911 static struct skcipher_alg dcp_aes_algs[] = { 912 { 913 .base.cra_name = "ecb(aes)", 914 .base.cra_driver_name = "ecb-aes-dcp", 915 .base.cra_priority = 400, 916 .base.cra_alignmask = 15, 917 .base.cra_flags = CRYPTO_ALG_ASYNC | 918 CRYPTO_ALG_NEED_FALLBACK, 919 .base.cra_blocksize = AES_BLOCK_SIZE, 920 .base.cra_ctxsize = sizeof(struct dcp_async_ctx), 921 .base.cra_module = THIS_MODULE, 922 923 .min_keysize = AES_MIN_KEY_SIZE, 924 .max_keysize = AES_MAX_KEY_SIZE, 925 .setkey = mxs_dcp_aes_setkey, 926 .encrypt = mxs_dcp_aes_ecb_encrypt, 927 .decrypt = mxs_dcp_aes_ecb_decrypt, 928 .init = mxs_dcp_aes_fallback_init_tfm, 929 .exit = mxs_dcp_aes_fallback_exit_tfm, 930 }, { 931 .base.cra_name = "cbc(aes)", 932 .base.cra_driver_name = "cbc-aes-dcp", 933 .base.cra_priority = 400, 934 .base.cra_alignmask = 15, 935 .base.cra_flags = CRYPTO_ALG_ASYNC | 936 CRYPTO_ALG_NEED_FALLBACK, 937 .base.cra_blocksize = AES_BLOCK_SIZE, 938 .base.cra_ctxsize = sizeof(struct dcp_async_ctx), 939 .base.cra_module = THIS_MODULE, 940 941 .min_keysize = AES_MIN_KEY_SIZE, 942 .max_keysize = AES_MAX_KEY_SIZE, 943 .setkey = mxs_dcp_aes_setkey, 944 .encrypt = mxs_dcp_aes_cbc_encrypt, 945 .decrypt = mxs_dcp_aes_cbc_decrypt, 946 .ivsize = AES_BLOCK_SIZE, 947 .init = mxs_dcp_aes_fallback_init_tfm, 948 .exit = mxs_dcp_aes_fallback_exit_tfm, 949 }, { 950 .base.cra_name = "ecb(paes)", 951 .base.cra_driver_name = "ecb-paes-dcp", 952 .base.cra_priority = 401, 953 .base.cra_alignmask = 15, 954 .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_INTERNAL, 955 .base.cra_blocksize = AES_BLOCK_SIZE, 956 .base.cra_ctxsize = sizeof(struct dcp_async_ctx), 957 .base.cra_module = THIS_MODULE, 958 959 .min_keysize = DCP_PAES_KEYSIZE, 960 .max_keysize = DCP_PAES_KEYSIZE, 961 .setkey = mxs_dcp_aes_setrefkey, 962 .encrypt = mxs_dcp_aes_ecb_encrypt, 963 .decrypt = mxs_dcp_aes_ecb_decrypt, 964 .init = mxs_dcp_paes_init_tfm, 965 }, { 966 .base.cra_name = "cbc(paes)", 967 .base.cra_driver_name = "cbc-paes-dcp", 968 .base.cra_priority = 401, 969 .base.cra_alignmask = 15, 970 .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_INTERNAL, 971 .base.cra_blocksize = AES_BLOCK_SIZE, 972 .base.cra_ctxsize = sizeof(struct dcp_async_ctx), 973 .base.cra_module = THIS_MODULE, 974 975 .min_keysize = DCP_PAES_KEYSIZE, 976 .max_keysize = DCP_PAES_KEYSIZE, 977 .setkey = mxs_dcp_aes_setrefkey, 978 .encrypt = mxs_dcp_aes_cbc_encrypt, 979 .decrypt = mxs_dcp_aes_cbc_decrypt, 980 .ivsize = AES_BLOCK_SIZE, 981 .init = mxs_dcp_paes_init_tfm, 982 }, 983 }; 984 985 /* SHA1 */ 986 static struct ahash_alg dcp_sha1_alg = { 987 .init = dcp_sha_init, 988 .update = dcp_sha_update, 989 .final = dcp_sha_final, 990 .finup = dcp_sha_finup, 991 .digest = dcp_sha_digest, 992 .import = dcp_sha_import, 993 .export = dcp_sha_export, 994 .halg = { 995 .digestsize = SHA1_DIGEST_SIZE, 996 .statesize = sizeof(struct dcp_export_state), 997 .base = { 998 .cra_name = "sha1", 999 .cra_driver_name = "sha1-dcp", 1000 .cra_priority = 400, 1001 .cra_flags = CRYPTO_ALG_ASYNC, 1002 .cra_blocksize = SHA1_BLOCK_SIZE, 1003 .cra_ctxsize = sizeof(struct dcp_async_ctx), 1004 .cra_module = THIS_MODULE, 1005 .cra_init = dcp_sha_cra_init, 1006 .cra_exit = dcp_sha_cra_exit, 1007 }, 1008 }, 1009 }; 1010 1011 /* SHA256 */ 1012 static struct ahash_alg dcp_sha256_alg = { 1013 .init = dcp_sha_init, 1014 .update = dcp_sha_update, 1015 .final = dcp_sha_final, 1016 .finup = dcp_sha_finup, 1017 .digest = dcp_sha_digest, 1018 .import = dcp_sha_import, 1019 .export = dcp_sha_export, 1020 .halg = { 1021 .digestsize = SHA256_DIGEST_SIZE, 1022 .statesize = sizeof(struct dcp_export_state), 1023 .base = { 1024 .cra_name = "sha256", 1025 .cra_driver_name = "sha256-dcp", 1026 .cra_priority = 400, 1027 .cra_flags = CRYPTO_ALG_ASYNC, 1028 .cra_blocksize = SHA256_BLOCK_SIZE, 1029 .cra_ctxsize = sizeof(struct dcp_async_ctx), 1030 .cra_module = THIS_MODULE, 1031 .cra_init = dcp_sha_cra_init, 1032 .cra_exit = dcp_sha_cra_exit, 1033 }, 1034 }, 1035 }; 1036 1037 static irqreturn_t mxs_dcp_irq(int irq, void *context) 1038 { 1039 struct dcp *sdcp = context; 1040 uint32_t stat; 1041 int i; 1042 1043 stat = readl(sdcp->base + MXS_DCP_STAT); 1044 stat &= MXS_DCP_STAT_IRQ_MASK; 1045 if (!stat) 1046 return IRQ_NONE; 1047 1048 /* Clear the interrupts. */ 1049 writel(stat, sdcp->base + MXS_DCP_STAT_CLR); 1050 1051 /* Complete the DMA requests that finished. */ 1052 for (i = 0; i < DCP_MAX_CHANS; i++) 1053 if (stat & (1 << i)) 1054 complete(&sdcp->completion[i]); 1055 1056 return IRQ_HANDLED; 1057 } 1058 1059 static int mxs_dcp_probe(struct platform_device *pdev) 1060 { 1061 struct device *dev = &pdev->dev; 1062 struct dcp *sdcp = NULL; 1063 int i, ret; 1064 int dcp_vmi_irq, dcp_irq; 1065 1066 if (global_sdcp) { 1067 dev_err(dev, "Only one DCP instance allowed!\n"); 1068 return -ENODEV; 1069 } 1070 1071 dcp_vmi_irq = platform_get_irq(pdev, 0); 1072 if (dcp_vmi_irq < 0) 1073 return dcp_vmi_irq; 1074 1075 dcp_irq = platform_get_irq(pdev, 1); 1076 if (dcp_irq < 0) 1077 return dcp_irq; 1078 1079 sdcp = devm_kzalloc(dev, sizeof(*sdcp), GFP_KERNEL); 1080 if (!sdcp) 1081 return -ENOMEM; 1082 1083 sdcp->dev = dev; 1084 sdcp->base = devm_platform_ioremap_resource(pdev, 0); 1085 if (IS_ERR(sdcp->base)) 1086 return PTR_ERR(sdcp->base); 1087 1088 1089 ret = devm_request_irq(dev, dcp_vmi_irq, mxs_dcp_irq, 0, 1090 "dcp-vmi-irq", sdcp); 1091 if (ret) 1092 return ret; 1093 1094 ret = devm_request_irq(dev, dcp_irq, mxs_dcp_irq, 0, 1095 "dcp-irq", sdcp); 1096 if (ret) 1097 return ret; 1098 1099 /* Allocate coherent helper block. */ 1100 sdcp->coh = devm_kzalloc(dev, sizeof(*sdcp->coh) + DCP_ALIGNMENT, 1101 GFP_KERNEL); 1102 if (!sdcp->coh) 1103 return -ENOMEM; 1104 1105 /* Re-align the structure so it fits the DCP constraints. */ 1106 sdcp->coh = PTR_ALIGN(sdcp->coh, DCP_ALIGNMENT); 1107 1108 /* DCP clock is optional, only used on some SOCs */ 1109 sdcp->dcp_clk = devm_clk_get_optional_enabled(dev, "dcp"); 1110 if (IS_ERR(sdcp->dcp_clk)) 1111 return PTR_ERR(sdcp->dcp_clk); 1112 1113 /* Restart the DCP block. */ 1114 ret = stmp_reset_block(sdcp->base); 1115 if (ret) { 1116 dev_err(dev, "Failed reset\n"); 1117 return ret; 1118 } 1119 1120 /* Initialize control register. */ 1121 writel(MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES | 1122 MXS_DCP_CTRL_ENABLE_CONTEXT_CACHING | 0xf, 1123 sdcp->base + MXS_DCP_CTRL); 1124 1125 /* Enable all DCP DMA channels. */ 1126 writel(MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK, 1127 sdcp->base + MXS_DCP_CHANNELCTRL); 1128 1129 /* 1130 * We do not enable context switching. Give the context buffer a 1131 * pointer to an illegal address so if context switching is 1132 * inadvertantly enabled, the DCP will return an error instead of 1133 * trashing good memory. The DCP DMA cannot access ROM, so any ROM 1134 * address will do. 1135 */ 1136 writel(0xffff0000, sdcp->base + MXS_DCP_CONTEXT); 1137 for (i = 0; i < DCP_MAX_CHANS; i++) 1138 writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(i)); 1139 writel(0xffffffff, sdcp->base + MXS_DCP_STAT_CLR); 1140 1141 global_sdcp = sdcp; 1142 1143 platform_set_drvdata(pdev, sdcp); 1144 1145 for (i = 0; i < DCP_MAX_CHANS; i++) { 1146 spin_lock_init(&sdcp->lock[i]); 1147 init_completion(&sdcp->completion[i]); 1148 crypto_init_queue(&sdcp->queue[i], 50); 1149 } 1150 1151 /* Create the SHA and AES handler threads. */ 1152 sdcp->thread[DCP_CHAN_HASH_SHA] = kthread_run(dcp_chan_thread_sha, 1153 NULL, "mxs_dcp_chan/sha"); 1154 if (IS_ERR(sdcp->thread[DCP_CHAN_HASH_SHA])) { 1155 dev_err(dev, "Error starting SHA thread!\n"); 1156 ret = PTR_ERR(sdcp->thread[DCP_CHAN_HASH_SHA]); 1157 return ret; 1158 } 1159 1160 sdcp->thread[DCP_CHAN_CRYPTO] = kthread_run(dcp_chan_thread_aes, 1161 NULL, "mxs_dcp_chan/aes"); 1162 if (IS_ERR(sdcp->thread[DCP_CHAN_CRYPTO])) { 1163 dev_err(dev, "Error starting SHA thread!\n"); 1164 ret = PTR_ERR(sdcp->thread[DCP_CHAN_CRYPTO]); 1165 goto err_destroy_sha_thread; 1166 } 1167 1168 /* Register the various crypto algorithms. */ 1169 sdcp->caps = readl(sdcp->base + MXS_DCP_CAPABILITY1); 1170 1171 if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128) { 1172 ret = crypto_register_skciphers(dcp_aes_algs, 1173 ARRAY_SIZE(dcp_aes_algs)); 1174 if (ret) { 1175 /* Failed to register algorithm. */ 1176 dev_err(dev, "Failed to register AES crypto!\n"); 1177 goto err_destroy_aes_thread; 1178 } 1179 } 1180 1181 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1) { 1182 ret = crypto_register_ahash(&dcp_sha1_alg); 1183 if (ret) { 1184 dev_err(dev, "Failed to register %s hash!\n", 1185 dcp_sha1_alg.halg.base.cra_name); 1186 goto err_unregister_aes; 1187 } 1188 } 1189 1190 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA256) { 1191 ret = crypto_register_ahash(&dcp_sha256_alg); 1192 if (ret) { 1193 dev_err(dev, "Failed to register %s hash!\n", 1194 dcp_sha256_alg.halg.base.cra_name); 1195 goto err_unregister_sha1; 1196 } 1197 } 1198 1199 return 0; 1200 1201 err_unregister_sha1: 1202 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1) 1203 crypto_unregister_ahash(&dcp_sha1_alg); 1204 1205 err_unregister_aes: 1206 if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128) 1207 crypto_unregister_skciphers(dcp_aes_algs, ARRAY_SIZE(dcp_aes_algs)); 1208 1209 err_destroy_aes_thread: 1210 kthread_stop(sdcp->thread[DCP_CHAN_CRYPTO]); 1211 1212 err_destroy_sha_thread: 1213 kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]); 1214 1215 return ret; 1216 } 1217 1218 static void mxs_dcp_remove(struct platform_device *pdev) 1219 { 1220 struct dcp *sdcp = platform_get_drvdata(pdev); 1221 1222 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA256) 1223 crypto_unregister_ahash(&dcp_sha256_alg); 1224 1225 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1) 1226 crypto_unregister_ahash(&dcp_sha1_alg); 1227 1228 if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128) 1229 crypto_unregister_skciphers(dcp_aes_algs, ARRAY_SIZE(dcp_aes_algs)); 1230 1231 kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]); 1232 kthread_stop(sdcp->thread[DCP_CHAN_CRYPTO]); 1233 1234 platform_set_drvdata(pdev, NULL); 1235 1236 global_sdcp = NULL; 1237 } 1238 1239 static const struct of_device_id mxs_dcp_dt_ids[] = { 1240 { .compatible = "fsl,imx23-dcp", .data = NULL, }, 1241 { .compatible = "fsl,imx28-dcp", .data = NULL, }, 1242 { /* sentinel */ } 1243 }; 1244 1245 MODULE_DEVICE_TABLE(of, mxs_dcp_dt_ids); 1246 1247 static struct platform_driver mxs_dcp_driver = { 1248 .probe = mxs_dcp_probe, 1249 .remove = mxs_dcp_remove, 1250 .driver = { 1251 .name = "mxs-dcp", 1252 .of_match_table = mxs_dcp_dt_ids, 1253 }, 1254 }; 1255 1256 module_platform_driver(mxs_dcp_driver); 1257 1258 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 1259 MODULE_DESCRIPTION("Freescale MXS DCP Driver"); 1260 MODULE_LICENSE("GPL"); 1261 MODULE_ALIAS("platform:mxs-dcp"); 1262