1fed8f4d5SSrujana Challa // SPDX-License-Identifier: GPL-2.0-only 2fed8f4d5SSrujana Challa /* Copyright (C) 2021 Marvell. */ 3fed8f4d5SSrujana Challa 4fed8f4d5SSrujana Challa #include "otx2_cpt_devlink.h" 5fed8f4d5SSrujana Challa 6fed8f4d5SSrujana Challa static int otx2_cpt_dl_egrp_create(struct devlink *dl, u32 id, 7*5625ca56SMateusz Polchlopek struct devlink_param_gset_ctx *ctx, 8*5625ca56SMateusz Polchlopek struct netlink_ext_ack *extack) 9fed8f4d5SSrujana Challa { 10fed8f4d5SSrujana Challa struct otx2_cpt_devlink *cpt_dl = devlink_priv(dl); 11fed8f4d5SSrujana Challa struct otx2_cptpf_dev *cptpf = cpt_dl->cptpf; 12fed8f4d5SSrujana Challa 13fed8f4d5SSrujana Challa return otx2_cpt_dl_custom_egrp_create(cptpf, ctx); 14fed8f4d5SSrujana Challa } 15fed8f4d5SSrujana Challa 16fed8f4d5SSrujana Challa static int otx2_cpt_dl_egrp_delete(struct devlink *dl, u32 id, 17*5625ca56SMateusz Polchlopek struct devlink_param_gset_ctx *ctx, 18*5625ca56SMateusz Polchlopek struct netlink_ext_ack *extack) 19fed8f4d5SSrujana Challa { 20fed8f4d5SSrujana Challa struct otx2_cpt_devlink *cpt_dl = devlink_priv(dl); 21fed8f4d5SSrujana Challa struct otx2_cptpf_dev *cptpf = cpt_dl->cptpf; 22fed8f4d5SSrujana Challa 23fed8f4d5SSrujana Challa return otx2_cpt_dl_custom_egrp_delete(cptpf, ctx); 24fed8f4d5SSrujana Challa } 25fed8f4d5SSrujana Challa 26fed8f4d5SSrujana Challa static int otx2_cpt_dl_uc_info(struct devlink *dl, u32 id, 27fed8f4d5SSrujana Challa struct devlink_param_gset_ctx *ctx) 28fed8f4d5SSrujana Challa { 2982f89f1aSSrujana Challa ctx->val.vstr[0] = '\0'; 3082f89f1aSSrujana Challa 3182f89f1aSSrujana Challa return 0; 3282f89f1aSSrujana Challa } 3382f89f1aSSrujana Challa 3482f89f1aSSrujana Challa static int otx2_cpt_dl_t106_mode_get(struct devlink *dl, u32 id, 3582f89f1aSSrujana Challa struct devlink_param_gset_ctx *ctx) 3682f89f1aSSrujana Challa { 37fed8f4d5SSrujana Challa struct otx2_cpt_devlink *cpt_dl = devlink_priv(dl); 38fed8f4d5SSrujana Challa struct otx2_cptpf_dev *cptpf = cpt_dl->cptpf; 3982f89f1aSSrujana Challa struct pci_dev *pdev = cptpf->pdev; 4082f89f1aSSrujana Challa u64 reg_val = 0; 41fed8f4d5SSrujana Challa 4282f89f1aSSrujana Challa otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL, ®_val, 4382f89f1aSSrujana Challa BLKADDR_CPT0); 4482f89f1aSSrujana Challa ctx->val.vu8 = (reg_val >> 18) & 0x1; 4582f89f1aSSrujana Challa 4682f89f1aSSrujana Challa return 0; 4782f89f1aSSrujana Challa } 4882f89f1aSSrujana Challa 4982f89f1aSSrujana Challa static int otx2_cpt_dl_t106_mode_set(struct devlink *dl, u32 id, 50*5625ca56SMateusz Polchlopek struct devlink_param_gset_ctx *ctx, 51*5625ca56SMateusz Polchlopek struct netlink_ext_ack *extack) 5282f89f1aSSrujana Challa { 5382f89f1aSSrujana Challa struct otx2_cpt_devlink *cpt_dl = devlink_priv(dl); 5482f89f1aSSrujana Challa struct otx2_cptpf_dev *cptpf = cpt_dl->cptpf; 5582f89f1aSSrujana Challa struct pci_dev *pdev = cptpf->pdev; 5682f89f1aSSrujana Challa u64 reg_val = 0; 5782f89f1aSSrujana Challa 5882f89f1aSSrujana Challa if (cptpf->enabled_vfs != 0 || cptpf->eng_grps.is_grps_created) 5982f89f1aSSrujana Challa return -EPERM; 6082f89f1aSSrujana Challa 6182f89f1aSSrujana Challa if (cpt_feature_sgv2(pdev)) { 6282f89f1aSSrujana Challa otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL, 6382f89f1aSSrujana Challa ®_val, BLKADDR_CPT0); 6482f89f1aSSrujana Challa reg_val &= ~(0x1ULL << 18); 6582f89f1aSSrujana Challa reg_val |= ((u64)ctx->val.vu8 & 0x1) << 18; 6682f89f1aSSrujana Challa return otx2_cpt_write_af_reg(&cptpf->afpf_mbox, pdev, 6782f89f1aSSrujana Challa CPT_AF_CTL, reg_val, BLKADDR_CPT0); 6882f89f1aSSrujana Challa } 69fed8f4d5SSrujana Challa 70fed8f4d5SSrujana Challa return 0; 71fed8f4d5SSrujana Challa } 72fed8f4d5SSrujana Challa 73fed8f4d5SSrujana Challa enum otx2_cpt_dl_param_id { 74fed8f4d5SSrujana Challa OTX2_CPT_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX, 75fed8f4d5SSrujana Challa OTX2_CPT_DEVLINK_PARAM_ID_EGRP_CREATE, 76fed8f4d5SSrujana Challa OTX2_CPT_DEVLINK_PARAM_ID_EGRP_DELETE, 7782f89f1aSSrujana Challa OTX2_CPT_DEVLINK_PARAM_ID_T106_MODE, 78fed8f4d5SSrujana Challa }; 79fed8f4d5SSrujana Challa 80fed8f4d5SSrujana Challa static const struct devlink_param otx2_cpt_dl_params[] = { 81fed8f4d5SSrujana Challa DEVLINK_PARAM_DRIVER(OTX2_CPT_DEVLINK_PARAM_ID_EGRP_CREATE, 82fed8f4d5SSrujana Challa "egrp_create", DEVLINK_PARAM_TYPE_STRING, 83fed8f4d5SSrujana Challa BIT(DEVLINK_PARAM_CMODE_RUNTIME), 84fed8f4d5SSrujana Challa otx2_cpt_dl_uc_info, otx2_cpt_dl_egrp_create, 85fed8f4d5SSrujana Challa NULL), 86fed8f4d5SSrujana Challa DEVLINK_PARAM_DRIVER(OTX2_CPT_DEVLINK_PARAM_ID_EGRP_DELETE, 87fed8f4d5SSrujana Challa "egrp_delete", DEVLINK_PARAM_TYPE_STRING, 88fed8f4d5SSrujana Challa BIT(DEVLINK_PARAM_CMODE_RUNTIME), 89fed8f4d5SSrujana Challa otx2_cpt_dl_uc_info, otx2_cpt_dl_egrp_delete, 90fed8f4d5SSrujana Challa NULL), 9182f89f1aSSrujana Challa DEVLINK_PARAM_DRIVER(OTX2_CPT_DEVLINK_PARAM_ID_T106_MODE, 9282f89f1aSSrujana Challa "t106_mode", DEVLINK_PARAM_TYPE_U8, 9382f89f1aSSrujana Challa BIT(DEVLINK_PARAM_CMODE_RUNTIME), 9482f89f1aSSrujana Challa otx2_cpt_dl_t106_mode_get, otx2_cpt_dl_t106_mode_set, 9582f89f1aSSrujana Challa NULL), 96fed8f4d5SSrujana Challa }; 97fed8f4d5SSrujana Challa 984ad28689SShijith Thotton static int otx2_cpt_dl_info_firmware_version_put(struct devlink_info_req *req, 994ad28689SShijith Thotton struct otx2_cpt_eng_grp_info grp[], 1004ad28689SShijith Thotton const char *ver_name, int eng_type) 1014ad28689SShijith Thotton { 1024ad28689SShijith Thotton struct otx2_cpt_engs_rsvd *eng; 1034ad28689SShijith Thotton int i; 1044ad28689SShijith Thotton 1054ad28689SShijith Thotton for (i = 0; i < OTX2_CPT_MAX_ENGINE_GROUPS; i++) { 1064ad28689SShijith Thotton eng = find_engines_by_type(&grp[i], eng_type); 1074ad28689SShijith Thotton if (eng) 1084ad28689SShijith Thotton return devlink_info_version_running_put(req, ver_name, 1094ad28689SShijith Thotton eng->ucode->ver_str); 1104ad28689SShijith Thotton } 1114ad28689SShijith Thotton 1124ad28689SShijith Thotton return 0; 1134ad28689SShijith Thotton } 1144ad28689SShijith Thotton 1154ad28689SShijith Thotton static int otx2_cpt_devlink_info_get(struct devlink *dl, 116fed8f4d5SSrujana Challa struct devlink_info_req *req, 117fed8f4d5SSrujana Challa struct netlink_ext_ack *extack) 118fed8f4d5SSrujana Challa { 1194ad28689SShijith Thotton struct otx2_cpt_devlink *cpt_dl = devlink_priv(dl); 1204ad28689SShijith Thotton struct otx2_cptpf_dev *cptpf = cpt_dl->cptpf; 1214ad28689SShijith Thotton int err; 1224ad28689SShijith Thotton 1234ad28689SShijith Thotton err = otx2_cpt_dl_info_firmware_version_put(req, cptpf->eng_grps.grp, 1244ad28689SShijith Thotton "fw.ae", OTX2_CPT_AE_TYPES); 1254ad28689SShijith Thotton if (err) 1264ad28689SShijith Thotton return err; 1274ad28689SShijith Thotton 1284ad28689SShijith Thotton err = otx2_cpt_dl_info_firmware_version_put(req, cptpf->eng_grps.grp, 1294ad28689SShijith Thotton "fw.se", OTX2_CPT_SE_TYPES); 1304ad28689SShijith Thotton if (err) 1314ad28689SShijith Thotton return err; 1324ad28689SShijith Thotton 1334ad28689SShijith Thotton return otx2_cpt_dl_info_firmware_version_put(req, cptpf->eng_grps.grp, 1344ad28689SShijith Thotton "fw.ie", OTX2_CPT_IE_TYPES); 135fed8f4d5SSrujana Challa } 136fed8f4d5SSrujana Challa 137fed8f4d5SSrujana Challa static const struct devlink_ops otx2_cpt_devlink_ops = { 138fed8f4d5SSrujana Challa .info_get = otx2_cpt_devlink_info_get, 139fed8f4d5SSrujana Challa }; 140fed8f4d5SSrujana Challa 141fed8f4d5SSrujana Challa int otx2_cpt_register_dl(struct otx2_cptpf_dev *cptpf) 142fed8f4d5SSrujana Challa { 143fed8f4d5SSrujana Challa struct device *dev = &cptpf->pdev->dev; 144fed8f4d5SSrujana Challa struct otx2_cpt_devlink *cpt_dl; 145fed8f4d5SSrujana Challa struct devlink *dl; 146fed8f4d5SSrujana Challa int ret; 147fed8f4d5SSrujana Challa 148fed8f4d5SSrujana Challa dl = devlink_alloc(&otx2_cpt_devlink_ops, 149fed8f4d5SSrujana Challa sizeof(struct otx2_cpt_devlink), dev); 150fed8f4d5SSrujana Challa if (!dl) { 151fed8f4d5SSrujana Challa dev_warn(dev, "devlink_alloc failed\n"); 152fed8f4d5SSrujana Challa return -ENOMEM; 153fed8f4d5SSrujana Challa } 154fed8f4d5SSrujana Challa 155fed8f4d5SSrujana Challa cpt_dl = devlink_priv(dl); 156fed8f4d5SSrujana Challa cpt_dl->dl = dl; 157fed8f4d5SSrujana Challa cpt_dl->cptpf = cptpf; 158fed8f4d5SSrujana Challa cptpf->dl = dl; 159fed8f4d5SSrujana Challa ret = devlink_params_register(dl, otx2_cpt_dl_params, 160fed8f4d5SSrujana Challa ARRAY_SIZE(otx2_cpt_dl_params)); 161fed8f4d5SSrujana Challa if (ret) { 162fed8f4d5SSrujana Challa dev_err(dev, "devlink params register failed with error %d", 163fed8f4d5SSrujana Challa ret); 164fed8f4d5SSrujana Challa devlink_free(dl); 165fed8f4d5SSrujana Challa return ret; 166fed8f4d5SSrujana Challa } 167fed8f4d5SSrujana Challa devlink_register(dl); 168fed8f4d5SSrujana Challa 169fed8f4d5SSrujana Challa return 0; 170fed8f4d5SSrujana Challa } 171fed8f4d5SSrujana Challa 172fed8f4d5SSrujana Challa void otx2_cpt_unregister_dl(struct otx2_cptpf_dev *cptpf) 173fed8f4d5SSrujana Challa { 174fed8f4d5SSrujana Challa struct devlink *dl = cptpf->dl; 175fed8f4d5SSrujana Challa 176fed8f4d5SSrujana Challa if (!dl) 177fed8f4d5SSrujana Challa return; 178fed8f4d5SSrujana Challa 179fed8f4d5SSrujana Challa devlink_unregister(dl); 180fed8f4d5SSrujana Challa devlink_params_unregister(dl, otx2_cpt_dl_params, 181fed8f4d5SSrujana Challa ARRAY_SIZE(otx2_cpt_dl_params)); 182fed8f4d5SSrujana Challa devlink_free(dl); 183fed8f4d5SSrujana Challa } 184