xref: /linux/drivers/crypto/marvell/octeontx2/cn10k_cpt.h (revision ea518afc992032f7570c0a89ac9240b387dc0faf)
1 /* SPDX-License-Identifier: GPL-2.0-only
2  * Copyright (C) 2021 Marvell.
3  */
4 #ifndef __CN10K_CPT_H
5 #define __CN10K_CPT_H
6 
7 #include "otx2_cpt_common.h"
8 #include "otx2_cptpf.h"
9 #include "otx2_cptvf.h"
10 
11 #define CN10K_CPT_HW_CTX_SIZE  256
12 
13 union cn10k_cpt_hw_ctx {
14 	u64 u;
15 	struct {
16 		u64 reserved_0_47:48;
17 		u64 ctx_push_sz:7;
18 		u64 reserved_55:1;
19 		u64 ctx_hdr_sz:2;
20 		u64 aop_valid:1;
21 		u64 reserved_59:1;
22 		u64 ctx_sz:4;
23 	} w0;
24 };
25 
26 struct cn10k_cpt_errata_ctx {
27 	union cn10k_cpt_hw_ctx *hw_ctx;
28 	u64 cptr_dma;
29 };
30 
31 static inline u8 cn10k_cpt_get_compcode(union otx2_cpt_res_s *result)
32 {
33 	return ((struct cn10k_cpt_res_s *)result)->compcode;
34 }
35 
36 static inline u8 cn10k_cpt_get_uc_compcode(union otx2_cpt_res_s *result)
37 {
38 	return ((struct cn10k_cpt_res_s *)result)->uc_compcode;
39 }
40 
41 static inline u8 otx2_cpt_get_compcode(union otx2_cpt_res_s *result)
42 {
43 	return ((struct cn9k_cpt_res_s *)result)->compcode;
44 }
45 
46 static inline u8 otx2_cpt_get_uc_compcode(union otx2_cpt_res_s *result)
47 {
48 	return ((struct cn9k_cpt_res_s *)result)->uc_compcode;
49 }
50 
51 int cn10k_cptpf_lmtst_init(struct otx2_cptpf_dev *cptpf);
52 int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptvf);
53 void cn10k_cpt_ctx_flush(struct pci_dev *pdev, u64 cptr, bool inval);
54 int cn10k_cpt_hw_ctx_init(struct pci_dev *pdev,
55 			  struct cn10k_cpt_errata_ctx *er_ctx);
56 void cn10k_cpt_hw_ctx_clear(struct pci_dev *pdev,
57 			    struct cn10k_cpt_errata_ctx *er_ctx);
58 void cn10k_cpt_hw_ctx_set(union cn10k_cpt_hw_ctx *hctx, u16 ctx_sz);
59 void cptvf_hw_ops_get(struct otx2_cptvf_dev *cptvf);
60 
61 #endif /* __CN10K_CPTLF_H */
62