1 /* SPDX-License-Identifier: GPL-2.0 2 * Marvell OcteonTX CPT driver 3 * 4 * Copyright (C) 2019 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef __OTX_CPTVF_H 12 #define __OTX_CPTVF_H 13 14 #include <linux/list.h> 15 #include <linux/interrupt.h> 16 #include <linux/device.h> 17 #include "otx_cpt_common.h" 18 #include "otx_cptvf_reqmgr.h" 19 20 /* Flags to indicate the features supported */ 21 #define OTX_CPT_FLAG_DEVICE_READY BIT(1) 22 #define otx_cpt_device_ready(cpt) ((cpt)->flags & OTX_CPT_FLAG_DEVICE_READY) 23 /* Default command queue length */ 24 #define OTX_CPT_CMD_QLEN (4*2046) 25 #define OTX_CPT_CMD_QCHUNK_SIZE 1023 26 #define OTX_CPT_NUM_QS_PER_VF 1 27 28 struct otx_cpt_cmd_chunk { 29 u8 *head; 30 dma_addr_t dma_addr; 31 u32 size; /* Chunk size, max OTX_CPT_INST_CHUNK_MAX_SIZE */ 32 struct list_head nextchunk; 33 }; 34 35 struct otx_cpt_cmd_queue { 36 u32 idx; /* Command queue host write idx */ 37 u32 num_chunks; /* Number of command chunks */ 38 struct otx_cpt_cmd_chunk *qhead;/* 39 * Command queue head, instructions 40 * are inserted here 41 */ 42 struct otx_cpt_cmd_chunk *base; 43 struct list_head chead; 44 }; 45 46 struct otx_cpt_cmd_qinfo { 47 u32 qchunksize; /* Command queue chunk size */ 48 struct otx_cpt_cmd_queue queue[OTX_CPT_NUM_QS_PER_VF]; 49 }; 50 51 struct otx_cpt_pending_qinfo { 52 u32 num_queues; /* Number of queues supported */ 53 struct otx_cpt_pending_queue queue[OTX_CPT_NUM_QS_PER_VF]; 54 }; 55 56 #define for_each_pending_queue(qinfo, q, i) \ 57 for (i = 0, q = &qinfo->queue[i]; i < qinfo->num_queues; i++, \ 58 q = &qinfo->queue[i]) 59 60 struct otx_cptvf_wqe { 61 struct tasklet_struct twork; 62 struct otx_cptvf *cptvf; 63 }; 64 65 struct otx_cptvf_wqe_info { 66 struct otx_cptvf_wqe vq_wqe[OTX_CPT_NUM_QS_PER_VF]; 67 }; 68 69 struct otx_cptvf { 70 u16 flags; /* Flags to hold device status bits */ 71 u8 vfid; /* Device Index 0...OTX_CPT_MAX_VF_NUM */ 72 u8 num_vfs; /* Number of enabled VFs */ 73 u8 vftype; /* VF type of SE_TYPE(2) or AE_TYPE(1) */ 74 u8 vfgrp; /* VF group (0 - 8) */ 75 u8 node; /* Operating node: Bits (46:44) in BAR0 address */ 76 u8 priority; /* 77 * VF priority ring: 1-High proirity round 78 * robin ring;0-Low priority round robin ring; 79 */ 80 struct pci_dev *pdev; /* Pci device handle */ 81 void __iomem *reg_base; /* Register start address */ 82 void *wqe_info; /* BH worker info */ 83 /* MSI-X */ 84 cpumask_var_t affinity_mask[OTX_CPT_VF_MSIX_VECTORS]; 85 /* Command and Pending queues */ 86 u32 qsize; 87 u32 num_queues; 88 struct otx_cpt_cmd_qinfo cqinfo; /* Command queue information */ 89 struct otx_cpt_pending_qinfo pqinfo; /* Pending queue information */ 90 /* VF-PF mailbox communication */ 91 bool pf_acked; 92 bool pf_nacked; 93 }; 94 95 int otx_cptvf_send_vf_up(struct otx_cptvf *cptvf); 96 int otx_cptvf_send_vf_down(struct otx_cptvf *cptvf); 97 int otx_cptvf_send_vf_to_grp_msg(struct otx_cptvf *cptvf, int group); 98 int otx_cptvf_send_vf_priority_msg(struct otx_cptvf *cptvf); 99 int otx_cptvf_send_vq_size_msg(struct otx_cptvf *cptvf); 100 int otx_cptvf_check_pf_ready(struct otx_cptvf *cptvf); 101 void otx_cptvf_handle_mbox_intr(struct otx_cptvf *cptvf); 102 void otx_cptvf_write_vq_doorbell(struct otx_cptvf *cptvf, u32 val); 103 104 #endif /* __OTX_CPTVF_H */ 105