1*10b4f094SSrujanaChalla /* SPDX-License-Identifier: GPL-2.0 2*10b4f094SSrujanaChalla * Marvell OcteonTX CPT driver 3*10b4f094SSrujanaChalla * 4*10b4f094SSrujanaChalla * Copyright (C) 2019 Marvell International Ltd. 5*10b4f094SSrujanaChalla * 6*10b4f094SSrujanaChalla * This program is free software; you can redistribute it and/or modify 7*10b4f094SSrujanaChalla * it under the terms of the GNU General Public License version 2 as 8*10b4f094SSrujanaChalla * published by the Free Software Foundation. 9*10b4f094SSrujanaChalla */ 10*10b4f094SSrujanaChalla 11*10b4f094SSrujanaChalla #ifndef __OTX_CPTVF_H 12*10b4f094SSrujanaChalla #define __OTX_CPTVF_H 13*10b4f094SSrujanaChalla 14*10b4f094SSrujanaChalla #include <linux/list.h> 15*10b4f094SSrujanaChalla #include <linux/interrupt.h> 16*10b4f094SSrujanaChalla #include <linux/device.h> 17*10b4f094SSrujanaChalla #include "otx_cpt_common.h" 18*10b4f094SSrujanaChalla #include "otx_cptvf_reqmgr.h" 19*10b4f094SSrujanaChalla 20*10b4f094SSrujanaChalla /* Flags to indicate the features supported */ 21*10b4f094SSrujanaChalla #define OTX_CPT_FLAG_DEVICE_READY BIT(1) 22*10b4f094SSrujanaChalla #define otx_cpt_device_ready(cpt) ((cpt)->flags & OTX_CPT_FLAG_DEVICE_READY) 23*10b4f094SSrujanaChalla /* Default command queue length */ 24*10b4f094SSrujanaChalla #define OTX_CPT_CMD_QLEN (4*2046) 25*10b4f094SSrujanaChalla #define OTX_CPT_CMD_QCHUNK_SIZE 1023 26*10b4f094SSrujanaChalla #define OTX_CPT_NUM_QS_PER_VF 1 27*10b4f094SSrujanaChalla 28*10b4f094SSrujanaChalla struct otx_cpt_cmd_chunk { 29*10b4f094SSrujanaChalla u8 *head; 30*10b4f094SSrujanaChalla dma_addr_t dma_addr; 31*10b4f094SSrujanaChalla u32 size; /* Chunk size, max OTX_CPT_INST_CHUNK_MAX_SIZE */ 32*10b4f094SSrujanaChalla struct list_head nextchunk; 33*10b4f094SSrujanaChalla }; 34*10b4f094SSrujanaChalla 35*10b4f094SSrujanaChalla struct otx_cpt_cmd_queue { 36*10b4f094SSrujanaChalla u32 idx; /* Command queue host write idx */ 37*10b4f094SSrujanaChalla u32 num_chunks; /* Number of command chunks */ 38*10b4f094SSrujanaChalla struct otx_cpt_cmd_chunk *qhead;/* 39*10b4f094SSrujanaChalla * Command queue head, instructions 40*10b4f094SSrujanaChalla * are inserted here 41*10b4f094SSrujanaChalla */ 42*10b4f094SSrujanaChalla struct otx_cpt_cmd_chunk *base; 43*10b4f094SSrujanaChalla struct list_head chead; 44*10b4f094SSrujanaChalla }; 45*10b4f094SSrujanaChalla 46*10b4f094SSrujanaChalla struct otx_cpt_cmd_qinfo { 47*10b4f094SSrujanaChalla u32 qchunksize; /* Command queue chunk size */ 48*10b4f094SSrujanaChalla struct otx_cpt_cmd_queue queue[OTX_CPT_NUM_QS_PER_VF]; 49*10b4f094SSrujanaChalla }; 50*10b4f094SSrujanaChalla 51*10b4f094SSrujanaChalla struct otx_cpt_pending_qinfo { 52*10b4f094SSrujanaChalla u32 num_queues; /* Number of queues supported */ 53*10b4f094SSrujanaChalla struct otx_cpt_pending_queue queue[OTX_CPT_NUM_QS_PER_VF]; 54*10b4f094SSrujanaChalla }; 55*10b4f094SSrujanaChalla 56*10b4f094SSrujanaChalla #define for_each_pending_queue(qinfo, q, i) \ 57*10b4f094SSrujanaChalla for (i = 0, q = &qinfo->queue[i]; i < qinfo->num_queues; i++, \ 58*10b4f094SSrujanaChalla q = &qinfo->queue[i]) 59*10b4f094SSrujanaChalla 60*10b4f094SSrujanaChalla struct otx_cptvf_wqe { 61*10b4f094SSrujanaChalla struct tasklet_struct twork; 62*10b4f094SSrujanaChalla struct otx_cptvf *cptvf; 63*10b4f094SSrujanaChalla }; 64*10b4f094SSrujanaChalla 65*10b4f094SSrujanaChalla struct otx_cptvf_wqe_info { 66*10b4f094SSrujanaChalla struct otx_cptvf_wqe vq_wqe[OTX_CPT_NUM_QS_PER_VF]; 67*10b4f094SSrujanaChalla }; 68*10b4f094SSrujanaChalla 69*10b4f094SSrujanaChalla struct otx_cptvf { 70*10b4f094SSrujanaChalla u16 flags; /* Flags to hold device status bits */ 71*10b4f094SSrujanaChalla u8 vfid; /* Device Index 0...OTX_CPT_MAX_VF_NUM */ 72*10b4f094SSrujanaChalla u8 num_vfs; /* Number of enabled VFs */ 73*10b4f094SSrujanaChalla u8 vftype; /* VF type of SE_TYPE(2) or AE_TYPE(1) */ 74*10b4f094SSrujanaChalla u8 vfgrp; /* VF group (0 - 8) */ 75*10b4f094SSrujanaChalla u8 node; /* Operating node: Bits (46:44) in BAR0 address */ 76*10b4f094SSrujanaChalla u8 priority; /* 77*10b4f094SSrujanaChalla * VF priority ring: 1-High proirity round 78*10b4f094SSrujanaChalla * robin ring;0-Low priority round robin ring; 79*10b4f094SSrujanaChalla */ 80*10b4f094SSrujanaChalla struct pci_dev *pdev; /* Pci device handle */ 81*10b4f094SSrujanaChalla void __iomem *reg_base; /* Register start address */ 82*10b4f094SSrujanaChalla void *wqe_info; /* BH worker info */ 83*10b4f094SSrujanaChalla /* MSI-X */ 84*10b4f094SSrujanaChalla cpumask_var_t affinity_mask[OTX_CPT_VF_MSIX_VECTORS]; 85*10b4f094SSrujanaChalla /* Command and Pending queues */ 86*10b4f094SSrujanaChalla u32 qsize; 87*10b4f094SSrujanaChalla u32 num_queues; 88*10b4f094SSrujanaChalla struct otx_cpt_cmd_qinfo cqinfo; /* Command queue information */ 89*10b4f094SSrujanaChalla struct otx_cpt_pending_qinfo pqinfo; /* Pending queue information */ 90*10b4f094SSrujanaChalla /* VF-PF mailbox communication */ 91*10b4f094SSrujanaChalla bool pf_acked; 92*10b4f094SSrujanaChalla bool pf_nacked; 93*10b4f094SSrujanaChalla }; 94*10b4f094SSrujanaChalla 95*10b4f094SSrujanaChalla int otx_cptvf_send_vf_up(struct otx_cptvf *cptvf); 96*10b4f094SSrujanaChalla int otx_cptvf_send_vf_down(struct otx_cptvf *cptvf); 97*10b4f094SSrujanaChalla int otx_cptvf_send_vf_to_grp_msg(struct otx_cptvf *cptvf, int group); 98*10b4f094SSrujanaChalla int otx_cptvf_send_vf_priority_msg(struct otx_cptvf *cptvf); 99*10b4f094SSrujanaChalla int otx_cptvf_send_vq_size_msg(struct otx_cptvf *cptvf); 100*10b4f094SSrujanaChalla int otx_cptvf_check_pf_ready(struct otx_cptvf *cptvf); 101*10b4f094SSrujanaChalla void otx_cptvf_handle_mbox_intr(struct otx_cptvf *cptvf); 102*10b4f094SSrujanaChalla void otx_cptvf_write_vq_doorbell(struct otx_cptvf *cptvf, u32 val); 103*10b4f094SSrujanaChalla 104*10b4f094SSrujanaChalla #endif /* __OTX_CPTVF_H */ 105