1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */ 2 /* Copyright(c) 2014 - 2020 Intel Corporation */ 3 #ifndef _ICP_QAT_HW_H_ 4 #define _ICP_QAT_HW_H_ 5 6 enum icp_qat_hw_ae_id { 7 ICP_QAT_HW_AE_0 = 0, 8 ICP_QAT_HW_AE_1 = 1, 9 ICP_QAT_HW_AE_2 = 2, 10 ICP_QAT_HW_AE_3 = 3, 11 ICP_QAT_HW_AE_4 = 4, 12 ICP_QAT_HW_AE_5 = 5, 13 ICP_QAT_HW_AE_6 = 6, 14 ICP_QAT_HW_AE_7 = 7, 15 ICP_QAT_HW_AE_8 = 8, 16 ICP_QAT_HW_AE_9 = 9, 17 ICP_QAT_HW_AE_10 = 10, 18 ICP_QAT_HW_AE_11 = 11, 19 ICP_QAT_HW_AE_DELIMITER = 12 20 }; 21 22 enum icp_qat_hw_qat_id { 23 ICP_QAT_HW_QAT_0 = 0, 24 ICP_QAT_HW_QAT_1 = 1, 25 ICP_QAT_HW_QAT_2 = 2, 26 ICP_QAT_HW_QAT_3 = 3, 27 ICP_QAT_HW_QAT_4 = 4, 28 ICP_QAT_HW_QAT_5 = 5, 29 ICP_QAT_HW_QAT_DELIMITER = 6 30 }; 31 32 enum icp_qat_hw_auth_algo { 33 ICP_QAT_HW_AUTH_ALGO_NULL = 0, 34 ICP_QAT_HW_AUTH_ALGO_SHA1 = 1, 35 ICP_QAT_HW_AUTH_ALGO_MD5 = 2, 36 ICP_QAT_HW_AUTH_ALGO_SHA224 = 3, 37 ICP_QAT_HW_AUTH_ALGO_SHA256 = 4, 38 ICP_QAT_HW_AUTH_ALGO_SHA384 = 5, 39 ICP_QAT_HW_AUTH_ALGO_SHA512 = 6, 40 ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC = 7, 41 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC = 8, 42 ICP_QAT_HW_AUTH_ALGO_AES_F9 = 9, 43 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 = 10, 44 ICP_QAT_HW_AUTH_ALGO_GALOIS_64 = 11, 45 ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 = 12, 46 ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 = 13, 47 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 = 14, 48 ICP_QAT_HW_AUTH_RESERVED_1 = 15, 49 ICP_QAT_HW_AUTH_RESERVED_2 = 16, 50 ICP_QAT_HW_AUTH_ALGO_SHA3_256 = 17, 51 ICP_QAT_HW_AUTH_RESERVED_3 = 18, 52 ICP_QAT_HW_AUTH_ALGO_SHA3_512 = 19, 53 ICP_QAT_HW_AUTH_ALGO_DELIMITER = 20 54 }; 55 56 enum icp_qat_hw_auth_mode { 57 ICP_QAT_HW_AUTH_MODE0 = 0, 58 ICP_QAT_HW_AUTH_MODE1 = 1, 59 ICP_QAT_HW_AUTH_MODE2 = 2, 60 ICP_QAT_HW_AUTH_MODE_DELIMITER = 3 61 }; 62 63 struct icp_qat_hw_auth_config { 64 __u32 config; 65 __u32 reserved; 66 }; 67 68 struct icp_qat_hw_ucs_cipher_config { 69 __u32 val; 70 __u32 reserved[3]; 71 }; 72 73 enum icp_qat_slice_mask { 74 ICP_ACCEL_MASK_CIPHER_SLICE = BIT(0), 75 ICP_ACCEL_MASK_AUTH_SLICE = BIT(1), 76 ICP_ACCEL_MASK_PKE_SLICE = BIT(2), 77 ICP_ACCEL_MASK_COMPRESS_SLICE = BIT(3), 78 ICP_ACCEL_MASK_LZS_SLICE = BIT(4), 79 ICP_ACCEL_MASK_EIA3_SLICE = BIT(5), 80 ICP_ACCEL_MASK_SHA3_SLICE = BIT(6), 81 }; 82 83 enum icp_qat_capabilities_mask { 84 ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = BIT(0), 85 ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = BIT(1), 86 ICP_ACCEL_CAPABILITIES_CIPHER = BIT(2), 87 ICP_ACCEL_CAPABILITIES_AUTHENTICATION = BIT(3), 88 ICP_ACCEL_CAPABILITIES_RESERVED_1 = BIT(4), 89 ICP_ACCEL_CAPABILITIES_COMPRESSION = BIT(5), 90 /* Bits 6-7 are currently reserved */ 91 ICP_ACCEL_CAPABILITIES_ZUC = BIT(8), 92 ICP_ACCEL_CAPABILITIES_SHA3 = BIT(9), 93 /* Bits 10-11 are currently reserved */ 94 ICP_ACCEL_CAPABILITIES_HKDF = BIT(12), 95 ICP_ACCEL_CAPABILITIES_ECEDMONT = BIT(13), 96 /* Bit 14 is currently reserved */ 97 ICP_ACCEL_CAPABILITIES_SHA3_EXT = BIT(15), 98 ICP_ACCEL_CAPABILITIES_AESGCM_SPC = BIT(16), 99 ICP_ACCEL_CAPABILITIES_CHACHA_POLY = BIT(17), 100 ICP_ACCEL_CAPABILITIES_SM2 = BIT(18), 101 ICP_ACCEL_CAPABILITIES_SM3 = BIT(19), 102 ICP_ACCEL_CAPABILITIES_SM4 = BIT(20), 103 /* Bit 21 is currently reserved */ 104 ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY = BIT(22), 105 ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64 = BIT(23), 106 ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION = BIT(24), 107 ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION = BIT(25), 108 ICP_ACCEL_CAPABILITIES_AES_V2 = BIT(26) 109 }; 110 111 #define QAT_AUTH_MODE_BITPOS 4 112 #define QAT_AUTH_MODE_MASK 0xF 113 #define QAT_AUTH_ALGO_BITPOS 0 114 #define QAT_AUTH_ALGO_MASK 0xF 115 #define QAT_AUTH_CMP_BITPOS 8 116 #define QAT_AUTH_CMP_MASK 0x7F 117 #define QAT_AUTH_SHA3_PADDING_BITPOS 16 118 #define QAT_AUTH_SHA3_PADDING_MASK 0x1 119 #define QAT_AUTH_ALGO_SHA3_BITPOS 22 120 #define QAT_AUTH_ALGO_SHA3_MASK 0x3 121 #define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \ 122 (((mode & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \ 123 ((algo & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \ 124 (((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) << \ 125 QAT_AUTH_ALGO_SHA3_BITPOS) | \ 126 (((((algo == ICP_QAT_HW_AUTH_ALGO_SHA3_256) || \ 127 (algo == ICP_QAT_HW_AUTH_ALGO_SHA3_512)) ? 1 : 0) \ 128 & QAT_AUTH_SHA3_PADDING_MASK) << QAT_AUTH_SHA3_PADDING_BITPOS) | \ 129 ((cmp_len & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS)) 130 131 struct icp_qat_hw_auth_counter { 132 __be32 counter; 133 __u32 reserved; 134 }; 135 136 #define QAT_AUTH_COUNT_MASK 0xFFFFFFFF 137 #define QAT_AUTH_COUNT_BITPOS 0 138 #define ICP_QAT_HW_AUTH_COUNT_BUILD(val) \ 139 (((val) & QAT_AUTH_COUNT_MASK) << QAT_AUTH_COUNT_BITPOS) 140 141 struct icp_qat_hw_auth_setup { 142 struct icp_qat_hw_auth_config auth_config; 143 struct icp_qat_hw_auth_counter auth_counter; 144 }; 145 146 #define QAT_HW_DEFAULT_ALIGNMENT 8 147 #define QAT_HW_ROUND_UP(val, n) (((val) + ((n) - 1)) & (~(n - 1))) 148 #define ICP_QAT_HW_NULL_STATE1_SZ 32 149 #define ICP_QAT_HW_MD5_STATE1_SZ 16 150 #define ICP_QAT_HW_SHA1_STATE1_SZ 20 151 #define ICP_QAT_HW_SHA224_STATE1_SZ 32 152 #define ICP_QAT_HW_SHA256_STATE1_SZ 32 153 #define ICP_QAT_HW_SHA3_256_STATE1_SZ 32 154 #define ICP_QAT_HW_SHA384_STATE1_SZ 64 155 #define ICP_QAT_HW_SHA512_STATE1_SZ 64 156 #define ICP_QAT_HW_SHA3_512_STATE1_SZ 64 157 #define ICP_QAT_HW_SHA3_224_STATE1_SZ 28 158 #define ICP_QAT_HW_SHA3_384_STATE1_SZ 48 159 #define ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ 16 160 #define ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ 16 161 #define ICP_QAT_HW_AES_F9_STATE1_SZ 32 162 #define ICP_QAT_HW_KASUMI_F9_STATE1_SZ 16 163 #define ICP_QAT_HW_GALOIS_128_STATE1_SZ 16 164 #define ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ 8 165 #define ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ 8 166 #define ICP_QAT_HW_NULL_STATE2_SZ 32 167 #define ICP_QAT_HW_MD5_STATE2_SZ 16 168 #define ICP_QAT_HW_SHA1_STATE2_SZ 20 169 #define ICP_QAT_HW_SHA224_STATE2_SZ 32 170 #define ICP_QAT_HW_SHA256_STATE2_SZ 32 171 #define ICP_QAT_HW_SHA3_256_STATE2_SZ 0 172 #define ICP_QAT_HW_SHA384_STATE2_SZ 64 173 #define ICP_QAT_HW_SHA512_STATE2_SZ 64 174 #define ICP_QAT_HW_SHA3_512_STATE2_SZ 0 175 #define ICP_QAT_HW_SHA3_224_STATE2_SZ 0 176 #define ICP_QAT_HW_SHA3_384_STATE2_SZ 0 177 #define ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ 16 178 #define ICP_QAT_HW_AES_CBC_MAC_KEY_SZ 16 179 #define ICP_QAT_HW_AES_CCM_CBC_E_CTR0_SZ 16 180 #define ICP_QAT_HW_F9_IK_SZ 16 181 #define ICP_QAT_HW_F9_FK_SZ 16 182 #define ICP_QAT_HW_KASUMI_F9_STATE2_SZ (ICP_QAT_HW_F9_IK_SZ + \ 183 ICP_QAT_HW_F9_FK_SZ) 184 #define ICP_QAT_HW_AES_F9_STATE2_SZ ICP_QAT_HW_KASUMI_F9_STATE2_SZ 185 #define ICP_QAT_HW_SNOW_3G_UIA2_STATE2_SZ 24 186 #define ICP_QAT_HW_ZUC_3G_EIA3_STATE2_SZ 32 187 #define ICP_QAT_HW_GALOIS_H_SZ 16 188 #define ICP_QAT_HW_GALOIS_LEN_A_SZ 8 189 #define ICP_QAT_HW_GALOIS_E_CTR0_SZ 16 190 191 struct icp_qat_hw_auth_sha512 { 192 struct icp_qat_hw_auth_setup inner_setup; 193 __u8 state1[ICP_QAT_HW_SHA512_STATE1_SZ]; 194 struct icp_qat_hw_auth_setup outer_setup; 195 __u8 state2[ICP_QAT_HW_SHA512_STATE2_SZ]; 196 }; 197 198 struct icp_qat_hw_auth_algo_blk { 199 struct icp_qat_hw_auth_sha512 sha; 200 }; 201 202 #define ICP_QAT_HW_GALOIS_LEN_A_BITPOS 0 203 #define ICP_QAT_HW_GALOIS_LEN_A_MASK 0xFFFFFFFF 204 205 enum icp_qat_hw_cipher_algo { 206 ICP_QAT_HW_CIPHER_ALGO_NULL = 0, 207 ICP_QAT_HW_CIPHER_ALGO_DES = 1, 208 ICP_QAT_HW_CIPHER_ALGO_3DES = 2, 209 ICP_QAT_HW_CIPHER_ALGO_AES128 = 3, 210 ICP_QAT_HW_CIPHER_ALGO_AES192 = 4, 211 ICP_QAT_HW_CIPHER_ALGO_AES256 = 5, 212 ICP_QAT_HW_CIPHER_ALGO_ARC4 = 6, 213 ICP_QAT_HW_CIPHER_ALGO_KASUMI = 7, 214 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 = 8, 215 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3 = 9, 216 ICP_QAT_HW_CIPHER_DELIMITER = 10 217 }; 218 219 enum icp_qat_hw_cipher_mode { 220 ICP_QAT_HW_CIPHER_ECB_MODE = 0, 221 ICP_QAT_HW_CIPHER_CBC_MODE = 1, 222 ICP_QAT_HW_CIPHER_CTR_MODE = 2, 223 ICP_QAT_HW_CIPHER_F8_MODE = 3, 224 ICP_QAT_HW_CIPHER_XTS_MODE = 6, 225 ICP_QAT_HW_CIPHER_MODE_DELIMITER = 7 226 }; 227 228 struct icp_qat_hw_cipher_config { 229 __u32 val; 230 __u32 reserved; 231 }; 232 233 enum icp_qat_hw_cipher_dir { 234 ICP_QAT_HW_CIPHER_ENCRYPT = 0, 235 ICP_QAT_HW_CIPHER_DECRYPT = 1, 236 }; 237 238 enum icp_qat_hw_cipher_convert { 239 ICP_QAT_HW_CIPHER_NO_CONVERT = 0, 240 ICP_QAT_HW_CIPHER_KEY_CONVERT = 1, 241 }; 242 243 #define QAT_CIPHER_MODE_BITPOS 4 244 #define QAT_CIPHER_MODE_MASK 0xF 245 #define QAT_CIPHER_ALGO_BITPOS 0 246 #define QAT_CIPHER_ALGO_MASK 0xF 247 #define QAT_CIPHER_CONVERT_BITPOS 9 248 #define QAT_CIPHER_CONVERT_MASK 0x1 249 #define QAT_CIPHER_DIR_BITPOS 8 250 #define QAT_CIPHER_DIR_MASK 0x1 251 #define QAT_CIPHER_MODE_F8_KEY_SZ_MULT 2 252 #define QAT_CIPHER_MODE_XTS_KEY_SZ_MULT 2 253 #define ICP_QAT_HW_CIPHER_CONFIG_BUILD(mode, algo, convert, dir) \ 254 (((mode & QAT_CIPHER_MODE_MASK) << QAT_CIPHER_MODE_BITPOS) | \ 255 ((algo & QAT_CIPHER_ALGO_MASK) << QAT_CIPHER_ALGO_BITPOS) | \ 256 ((convert & QAT_CIPHER_CONVERT_MASK) << QAT_CIPHER_CONVERT_BITPOS) | \ 257 ((dir & QAT_CIPHER_DIR_MASK) << QAT_CIPHER_DIR_BITPOS)) 258 #define ICP_QAT_HW_DES_BLK_SZ 8 259 #define ICP_QAT_HW_3DES_BLK_SZ 8 260 #define ICP_QAT_HW_NULL_BLK_SZ 8 261 #define ICP_QAT_HW_AES_BLK_SZ 16 262 #define ICP_QAT_HW_KASUMI_BLK_SZ 8 263 #define ICP_QAT_HW_SNOW_3G_BLK_SZ 8 264 #define ICP_QAT_HW_ZUC_3G_BLK_SZ 8 265 #define ICP_QAT_HW_NULL_KEY_SZ 256 266 #define ICP_QAT_HW_DES_KEY_SZ 8 267 #define ICP_QAT_HW_3DES_KEY_SZ 24 268 #define ICP_QAT_HW_AES_128_KEY_SZ 16 269 #define ICP_QAT_HW_AES_192_KEY_SZ 24 270 #define ICP_QAT_HW_AES_256_KEY_SZ 32 271 #define ICP_QAT_HW_AES_128_F8_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \ 272 QAT_CIPHER_MODE_F8_KEY_SZ_MULT) 273 #define ICP_QAT_HW_AES_192_F8_KEY_SZ (ICP_QAT_HW_AES_192_KEY_SZ * \ 274 QAT_CIPHER_MODE_F8_KEY_SZ_MULT) 275 #define ICP_QAT_HW_AES_256_F8_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \ 276 QAT_CIPHER_MODE_F8_KEY_SZ_MULT) 277 #define ICP_QAT_HW_AES_128_XTS_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \ 278 QAT_CIPHER_MODE_XTS_KEY_SZ_MULT) 279 #define ICP_QAT_HW_AES_256_XTS_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \ 280 QAT_CIPHER_MODE_XTS_KEY_SZ_MULT) 281 #define ICP_QAT_HW_KASUMI_KEY_SZ 16 282 #define ICP_QAT_HW_KASUMI_F8_KEY_SZ (ICP_QAT_HW_KASUMI_KEY_SZ * \ 283 QAT_CIPHER_MODE_F8_KEY_SZ_MULT) 284 #define ICP_QAT_HW_AES_128_XTS_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \ 285 QAT_CIPHER_MODE_XTS_KEY_SZ_MULT) 286 #define ICP_QAT_HW_AES_256_XTS_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \ 287 QAT_CIPHER_MODE_XTS_KEY_SZ_MULT) 288 #define ICP_QAT_HW_ARC4_KEY_SZ 256 289 #define ICP_QAT_HW_SNOW_3G_UEA2_KEY_SZ 16 290 #define ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ 16 291 #define ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ 16 292 #define ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ 16 293 #define ICP_QAT_HW_MODE_F8_NUM_REG_TO_CLEAR 2 294 #define INIT_SHRAM_CONSTANTS_TABLE_SZ 1024 295 296 struct icp_qat_hw_cipher_aes256_f8 { 297 struct icp_qat_hw_cipher_config cipher_config; 298 __u8 key[ICP_QAT_HW_AES_256_F8_KEY_SZ]; 299 }; 300 301 struct icp_qat_hw_ucs_cipher_aes256_f8 { 302 struct icp_qat_hw_ucs_cipher_config cipher_config; 303 __u8 key[ICP_QAT_HW_AES_256_F8_KEY_SZ]; 304 }; 305 306 struct icp_qat_hw_cipher_algo_blk { 307 union { 308 struct icp_qat_hw_cipher_aes256_f8 aes; 309 struct icp_qat_hw_ucs_cipher_aes256_f8 ucs_aes; 310 }; 311 } __aligned(64); 312 313 enum icp_qat_hw_compression_direction { 314 ICP_QAT_HW_COMPRESSION_DIR_COMPRESS = 0, 315 ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS = 1, 316 ICP_QAT_HW_COMPRESSION_DIR_DELIMITER = 2 317 }; 318 319 enum icp_qat_hw_compression_delayed_match { 320 ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DISABLED = 0, 321 ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_ENABLED = 1, 322 ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DELIMITER = 2 323 }; 324 325 enum icp_qat_hw_compression_algo { 326 ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE = 0, 327 ICP_QAT_HW_COMPRESSION_ALGO_LZS = 1, 328 ICP_QAT_HW_COMPRESSION_ALGO_DELIMITER = 2 329 }; 330 331 enum icp_qat_hw_compression_depth { 332 ICP_QAT_HW_COMPRESSION_DEPTH_1 = 0, 333 ICP_QAT_HW_COMPRESSION_DEPTH_4 = 1, 334 ICP_QAT_HW_COMPRESSION_DEPTH_8 = 2, 335 ICP_QAT_HW_COMPRESSION_DEPTH_16 = 3, 336 ICP_QAT_HW_COMPRESSION_DEPTH_128 = 4, 337 ICP_QAT_HW_COMPRESSION_DEPTH_DELIMITER = 5 338 }; 339 340 enum icp_qat_hw_compression_file_type { 341 ICP_QAT_HW_COMPRESSION_FILE_TYPE_0 = 0, 342 ICP_QAT_HW_COMPRESSION_FILE_TYPE_1 = 1, 343 ICP_QAT_HW_COMPRESSION_FILE_TYPE_2 = 2, 344 ICP_QAT_HW_COMPRESSION_FILE_TYPE_3 = 3, 345 ICP_QAT_HW_COMPRESSION_FILE_TYPE_4 = 4, 346 ICP_QAT_HW_COMPRESSION_FILE_TYPE_DELIMITER = 5 347 }; 348 349 struct icp_qat_hw_compression_config { 350 __u32 lower_val; 351 __u32 upper_val; 352 }; 353 354 #define QAT_COMPRESSION_DIR_BITPOS 4 355 #define QAT_COMPRESSION_DIR_MASK 0x7 356 #define QAT_COMPRESSION_DELAYED_MATCH_BITPOS 16 357 #define QAT_COMPRESSION_DELAYED_MATCH_MASK 0x1 358 #define QAT_COMPRESSION_ALGO_BITPOS 31 359 #define QAT_COMPRESSION_ALGO_MASK 0x1 360 #define QAT_COMPRESSION_DEPTH_BITPOS 28 361 #define QAT_COMPRESSION_DEPTH_MASK 0x7 362 #define QAT_COMPRESSION_FILE_TYPE_BITPOS 24 363 #define QAT_COMPRESSION_FILE_TYPE_MASK 0xF 364 365 #define ICP_QAT_HW_COMPRESSION_CONFIG_BUILD(dir, delayed, \ 366 algo, depth, filetype) \ 367 ((((dir) & QAT_COMPRESSION_DIR_MASK) << \ 368 QAT_COMPRESSION_DIR_BITPOS) | \ 369 (((delayed) & QAT_COMPRESSION_DELAYED_MATCH_MASK) << \ 370 QAT_COMPRESSION_DELAYED_MATCH_BITPOS) | \ 371 (((algo) & QAT_COMPRESSION_ALGO_MASK) << \ 372 QAT_COMPRESSION_ALGO_BITPOS) | \ 373 (((depth) & QAT_COMPRESSION_DEPTH_MASK) << \ 374 QAT_COMPRESSION_DEPTH_BITPOS) | \ 375 (((filetype) & QAT_COMPRESSION_FILE_TYPE_MASK) << \ 376 QAT_COMPRESSION_FILE_TYPE_BITPOS)) 377 378 #endif 379