1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */ 2 /* Copyright(c) 2014 - 2020 Intel Corporation */ 3 #ifndef __ICP_QAT_HAL_H 4 #define __ICP_QAT_HAL_H 5 #include "icp_qat_fw_loader_handle.h" 6 7 enum hal_global_csr { 8 MISC_CONTROL = 0xA04, 9 ICP_RESET = 0xA0c, 10 ICP_GLOBAL_CLK_ENABLE = 0xA50 11 }; 12 13 enum { 14 MISC_CONTROL_C4XXX = 0xAA0, 15 ICP_RESET_CPP0 = 0x938, 16 ICP_RESET_CPP1 = 0x93c, 17 ICP_GLOBAL_CLK_ENABLE_CPP0 = 0x964, 18 ICP_GLOBAL_CLK_ENABLE_CPP1 = 0x968 19 }; 20 21 enum hal_ae_csr { 22 USTORE_ADDRESS = 0x000, 23 USTORE_DATA_LOWER = 0x004, 24 USTORE_DATA_UPPER = 0x008, 25 ALU_OUT = 0x010, 26 CTX_ARB_CNTL = 0x014, 27 CTX_ENABLES = 0x018, 28 CC_ENABLE = 0x01c, 29 CSR_CTX_POINTER = 0x020, 30 CTX_STS_INDIRECT = 0x040, 31 ACTIVE_CTX_STATUS = 0x044, 32 CTX_SIG_EVENTS_INDIRECT = 0x048, 33 CTX_SIG_EVENTS_ACTIVE = 0x04c, 34 CTX_WAKEUP_EVENTS_INDIRECT = 0x050, 35 LM_ADDR_0_INDIRECT = 0x060, 36 LM_ADDR_1_INDIRECT = 0x068, 37 LM_ADDR_2_INDIRECT = 0x0cc, 38 LM_ADDR_3_INDIRECT = 0x0d4, 39 INDIRECT_LM_ADDR_0_BYTE_INDEX = 0x0e0, 40 INDIRECT_LM_ADDR_1_BYTE_INDEX = 0x0e8, 41 INDIRECT_LM_ADDR_2_BYTE_INDEX = 0x10c, 42 INDIRECT_LM_ADDR_3_BYTE_INDEX = 0x114, 43 INDIRECT_T_INDEX = 0x0f8, 44 INDIRECT_T_INDEX_BYTE_INDEX = 0x0fc, 45 FUTURE_COUNT_SIGNAL_INDIRECT = 0x078, 46 TIMESTAMP_LOW = 0x0c0, 47 TIMESTAMP_HIGH = 0x0c4, 48 PROFILE_COUNT = 0x144, 49 SIGNATURE_ENABLE = 0x150, 50 AE_MISC_CONTROL = 0x160, 51 LOCAL_CSR_STATUS = 0x180, 52 }; 53 54 enum fcu_csr { 55 FCU_CONTROL = 0x8c0, 56 FCU_STATUS = 0x8c4, 57 FCU_STATUS1 = 0x8c8, 58 FCU_DRAM_ADDR_LO = 0x8cc, 59 FCU_DRAM_ADDR_HI = 0x8d0, 60 FCU_RAMBASE_ADDR_HI = 0x8d4, 61 FCU_RAMBASE_ADDR_LO = 0x8d8 62 }; 63 64 enum fcu_csr_4xxx { 65 FCU_CONTROL_4XXX = 0x1000, 66 FCU_STATUS_4XXX = 0x1004, 67 FCU_ME_BROADCAST_MASK_TYPE = 0x1008, 68 FCU_AE_LOADED_4XXX = 0x1010, 69 FCU_DRAM_ADDR_LO_4XXX = 0x1014, 70 FCU_DRAM_ADDR_HI_4XXX = 0x1018, 71 }; 72 73 enum fcu_cmd { 74 FCU_CTRL_CMD_NOOP = 0, 75 FCU_CTRL_CMD_AUTH = 1, 76 FCU_CTRL_CMD_LOAD = 2, 77 FCU_CTRL_CMD_START = 3 78 }; 79 80 enum fcu_sts { 81 FCU_STS_NO_STS = 0, 82 FCU_STS_VERI_DONE = 1, 83 FCU_STS_LOAD_DONE = 2, 84 FCU_STS_VERI_FAIL = 3, 85 FCU_STS_LOAD_FAIL = 4, 86 FCU_STS_BUSY = 5 87 }; 88 89 #define ALL_AE_MASK 0xFFFFFFFF 90 #define UA_ECS (0x1 << 31) 91 #define ACS_ABO_BITPOS 31 92 #define ACS_ACNO 0x7 93 #define CE_ENABLE_BITPOS 0x8 94 #define CE_LMADDR_0_GLOBAL_BITPOS 16 95 #define CE_LMADDR_1_GLOBAL_BITPOS 17 96 #define CE_LMADDR_2_GLOBAL_BITPOS 22 97 #define CE_LMADDR_3_GLOBAL_BITPOS 23 98 #define CE_T_INDEX_GLOBAL_BITPOS 21 99 #define CE_NN_MODE_BITPOS 20 100 #define CE_REG_PAR_ERR_BITPOS 25 101 #define CE_BREAKPOINT_BITPOS 27 102 #define CE_CNTL_STORE_PARITY_ERROR_BITPOS 29 103 #define CE_INUSE_CONTEXTS_BITPOS 31 104 #define CE_NN_MODE (0x1 << CE_NN_MODE_BITPOS) 105 #define CE_INUSE_CONTEXTS (0x1 << CE_INUSE_CONTEXTS_BITPOS) 106 #define XCWE_VOLUNTARY (0x1) 107 #define LCS_STATUS (0x1) 108 #define MMC_SHARE_CS_BITPOS 2 109 #define WAKEUP_EVENT 0x10000 110 #define FCU_CTRL_BROADCAST_POS 0x4 111 #define FCU_CTRL_AE_POS 0x8 112 #define FCU_AUTH_STS_MASK 0x7 113 #define FCU_STS_DONE_POS 0x9 114 #define FCU_STS_AUTHFWLD_POS 0X8 115 #define FCU_LOADED_AE_POS 0x16 116 #define FW_AUTH_WAIT_PERIOD 10 117 #define FW_AUTH_MAX_RETRY 300 118 #define ICP_QAT_AE_OFFSET 0x20000 119 #define ICP_QAT_CAP_OFFSET (ICP_QAT_AE_OFFSET + 0x10000) 120 #define LOCAL_TO_XFER_REG_OFFSET 0x800 121 #define ICP_QAT_EP_OFFSET 0x3a000 122 #define ICP_QAT_EP_OFFSET_4XXX 0x200000 /* HI MMIO CSRs */ 123 #define ICP_QAT_AE_OFFSET_4XXX 0x600000 124 #define ICP_QAT_CAP_OFFSET_4XXX 0x640000 125 #define SET_CAP_CSR(handle, csr, val) \ 126 ADF_CSR_WR((handle)->hal_cap_g_ctl_csr_addr_v, csr, val) 127 #define GET_CAP_CSR(handle, csr) \ 128 ADF_CSR_RD((handle)->hal_cap_g_ctl_csr_addr_v, csr) 129 #define AE_CSR(handle, ae) \ 130 ((char __iomem *)(handle)->hal_cap_ae_local_csr_addr_v + ((ae) << 12)) 131 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & (csr))) 132 #define SET_AE_CSR(handle, ae, csr, val) \ 133 ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val) 134 #define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0) 135 #define AE_XFER(handle, ae) \ 136 ((char __iomem *)(handle)->hal_cap_ae_xfer_csr_addr_v + ((ae) << 12)) 137 #define AE_XFER_ADDR(handle, ae, reg) (AE_XFER(handle, ae) + \ 138 (((reg) & 0xff) << 2)) 139 #define SET_AE_XFER(handle, ae, reg, val) \ 140 ADF_CSR_WR(AE_XFER_ADDR(handle, ae, reg), 0, val) 141 #define SRAM_WRITE(handle, addr, val) \ 142 ADF_CSR_WR((handle)->hal_sram_addr_v, addr, val) 143 #endif 144