1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) 2 /* Copyright(c) 2015 - 2021 Intel Corporation */ 3 #include <linux/workqueue.h> 4 #include <linux/pci.h> 5 #include <linux/device.h> 6 #include "adf_common_drv.h" 7 #include "adf_cfg.h" 8 #include "adf_pfvf_pf_msg.h" 9 10 #define ADF_VF2PF_RATELIMIT_INTERVAL 8 11 #define ADF_VF2PF_RATELIMIT_BURST 130 12 13 static struct workqueue_struct *pf2vf_resp_wq; 14 15 struct adf_pf2vf_resp { 16 struct work_struct pf2vf_resp_work; 17 struct adf_accel_vf_info *vf_info; 18 }; 19 20 static void adf_iov_send_resp(struct work_struct *work) 21 { 22 struct adf_pf2vf_resp *pf2vf_resp = 23 container_of(work, struct adf_pf2vf_resp, pf2vf_resp_work); 24 struct adf_accel_vf_info *vf_info = pf2vf_resp->vf_info; 25 struct adf_accel_dev *accel_dev = vf_info->accel_dev; 26 u32 vf_nr = vf_info->vf_nr; 27 bool ret; 28 29 ret = adf_recv_and_handle_vf2pf_msg(accel_dev, vf_nr); 30 if (ret) 31 /* re-enable interrupt on PF from this VF */ 32 adf_enable_vf2pf_interrupts(accel_dev, 1 << vf_nr); 33 34 kfree(pf2vf_resp); 35 } 36 37 void adf_schedule_vf2pf_handler(struct adf_accel_vf_info *vf_info) 38 { 39 struct adf_pf2vf_resp *pf2vf_resp; 40 41 pf2vf_resp = kzalloc(sizeof(*pf2vf_resp), GFP_ATOMIC); 42 if (!pf2vf_resp) 43 return; 44 45 pf2vf_resp->vf_info = vf_info; 46 INIT_WORK(&pf2vf_resp->pf2vf_resp_work, adf_iov_send_resp); 47 queue_work(pf2vf_resp_wq, &pf2vf_resp->pf2vf_resp_work); 48 } 49 50 static int adf_enable_sriov(struct adf_accel_dev *accel_dev) 51 { 52 struct pci_dev *pdev = accel_to_pci_dev(accel_dev); 53 int totalvfs = pci_sriov_get_totalvfs(pdev); 54 struct adf_hw_device_data *hw_data = accel_dev->hw_device; 55 struct adf_accel_vf_info *vf_info; 56 int i; 57 58 for (i = 0, vf_info = accel_dev->pf.vf_info; i < totalvfs; 59 i++, vf_info++) { 60 /* This ptr will be populated when VFs will be created */ 61 vf_info->accel_dev = accel_dev; 62 vf_info->vf_nr = i; 63 64 mutex_init(&vf_info->pf2vf_lock); 65 ratelimit_state_init(&vf_info->vf2pf_ratelimit, 66 ADF_VF2PF_RATELIMIT_INTERVAL, 67 ADF_VF2PF_RATELIMIT_BURST); 68 } 69 70 /* Set Valid bits in AE Thread to PCIe Function Mapping */ 71 if (hw_data->configure_iov_threads) 72 hw_data->configure_iov_threads(accel_dev, true); 73 74 /* Enable VF to PF interrupts for all VFs */ 75 adf_enable_vf2pf_interrupts(accel_dev, BIT_ULL(totalvfs) - 1); 76 77 /* 78 * Due to the hardware design, when SR-IOV and the ring arbiter 79 * are enabled all the VFs supported in hardware must be enabled in 80 * order for all the hardware resources (i.e. bundles) to be usable. 81 * When SR-IOV is enabled, each of the VFs will own one bundle. 82 */ 83 return pci_enable_sriov(pdev, totalvfs); 84 } 85 86 void adf_reenable_sriov(struct adf_accel_dev *accel_dev) 87 { 88 struct pci_dev *pdev = accel_to_pci_dev(accel_dev); 89 char cfg[ADF_CFG_MAX_VAL_LEN_IN_BYTES] = {0}; 90 unsigned long val = 0; 91 92 if (adf_cfg_get_param_value(accel_dev, ADF_GENERAL_SEC, 93 ADF_SRIOV_ENABLED, cfg)) 94 return; 95 96 if (!accel_dev->pf.vf_info) 97 return; 98 99 if (adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_CY, 100 &val, ADF_DEC)) 101 return; 102 103 if (adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_DC, 104 &val, ADF_DEC)) 105 return; 106 107 set_bit(ADF_STATUS_CONFIGURED, &accel_dev->status); 108 dev_dbg(&pdev->dev, "Re-enabling SRIOV\n"); 109 adf_enable_sriov(accel_dev); 110 } 111 112 /** 113 * adf_disable_sriov() - Disable SRIOV for the device 114 * @accel_dev: Pointer to accel device. 115 * 116 * Function disables SRIOV for the accel device. 117 * 118 * Return: 0 on success, error code otherwise. 119 */ 120 void adf_disable_sriov(struct adf_accel_dev *accel_dev) 121 { 122 struct adf_hw_device_data *hw_data = accel_dev->hw_device; 123 int totalvfs = pci_sriov_get_totalvfs(accel_to_pci_dev(accel_dev)); 124 struct adf_accel_vf_info *vf; 125 int i; 126 127 if (!accel_dev->pf.vf_info) 128 return; 129 130 adf_pf2vf_notify_restarting(accel_dev); 131 adf_pf2vf_wait_for_restarting_complete(accel_dev); 132 pci_disable_sriov(accel_to_pci_dev(accel_dev)); 133 134 /* Disable VF to PF interrupts */ 135 adf_disable_all_vf2pf_interrupts(accel_dev); 136 137 /* Clear Valid bits in AE Thread to PCIe Function Mapping */ 138 if (hw_data->configure_iov_threads) 139 hw_data->configure_iov_threads(accel_dev, false); 140 141 for (i = 0, vf = accel_dev->pf.vf_info; i < totalvfs; i++, vf++) 142 mutex_destroy(&vf->pf2vf_lock); 143 144 if (!test_bit(ADF_STATUS_RESTARTING, &accel_dev->status)) { 145 kfree(accel_dev->pf.vf_info); 146 accel_dev->pf.vf_info = NULL; 147 } 148 } 149 EXPORT_SYMBOL_GPL(adf_disable_sriov); 150 151 /** 152 * adf_sriov_configure() - Enable SRIOV for the device 153 * @pdev: Pointer to PCI device. 154 * @numvfs: Number of virtual functions (VFs) to enable. 155 * 156 * Note that the @numvfs parameter is ignored and all VFs supported by the 157 * device are enabled due to the design of the hardware. 158 * 159 * Function enables SRIOV for the PCI device. 160 * 161 * Return: number of VFs enabled on success, error code otherwise. 162 */ 163 int adf_sriov_configure(struct pci_dev *pdev, int numvfs) 164 { 165 struct adf_accel_dev *accel_dev = adf_devmgr_pci_to_accel_dev(pdev); 166 int totalvfs = pci_sriov_get_totalvfs(pdev); 167 unsigned long val; 168 int ret; 169 170 if (!accel_dev) { 171 dev_err(&pdev->dev, "Failed to find accel_dev\n"); 172 return -EFAULT; 173 } 174 175 if (!device_iommu_mapped(&pdev->dev)) 176 dev_warn(&pdev->dev, "IOMMU should be enabled for SR-IOV to work correctly\n"); 177 178 if (accel_dev->pf.vf_info) { 179 dev_info(&pdev->dev, "Already enabled for this device\n"); 180 return -EINVAL; 181 } 182 183 if (adf_dev_started(accel_dev)) { 184 if (adf_devmgr_in_reset(accel_dev) || 185 adf_dev_in_use(accel_dev)) { 186 dev_err(&GET_DEV(accel_dev), "Device busy\n"); 187 return -EBUSY; 188 } 189 190 ret = adf_dev_down(accel_dev, true); 191 if (ret) 192 return ret; 193 } 194 195 if (adf_cfg_section_add(accel_dev, ADF_KERNEL_SEC)) 196 return -EFAULT; 197 val = 0; 198 if (adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, 199 ADF_NUM_CY, (void *)&val, ADF_DEC)) 200 return -EFAULT; 201 ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_DC, 202 &val, ADF_DEC); 203 if (ret) 204 return ret; 205 206 set_bit(ADF_STATUS_CONFIGURED, &accel_dev->status); 207 208 /* Allocate memory for VF info structs */ 209 accel_dev->pf.vf_info = kcalloc(totalvfs, 210 sizeof(struct adf_accel_vf_info), 211 GFP_KERNEL); 212 if (!accel_dev->pf.vf_info) 213 return -ENOMEM; 214 215 if (adf_dev_up(accel_dev, false)) { 216 dev_err(&GET_DEV(accel_dev), "Failed to start qat_dev%d\n", 217 accel_dev->accel_id); 218 return -EFAULT; 219 } 220 221 ret = adf_enable_sriov(accel_dev); 222 if (ret) 223 return ret; 224 225 val = 1; 226 adf_cfg_add_key_value_param(accel_dev, ADF_GENERAL_SEC, ADF_SRIOV_ENABLED, 227 &val, ADF_DEC); 228 229 return numvfs; 230 } 231 EXPORT_SYMBOL_GPL(adf_sriov_configure); 232 233 int __init adf_init_pf_wq(void) 234 { 235 /* Workqueue for PF2VF responses */ 236 pf2vf_resp_wq = alloc_workqueue("qat_pf2vf_resp_wq", WQ_MEM_RECLAIM, 0); 237 238 return !pf2vf_resp_wq ? -ENOMEM : 0; 239 } 240 241 void adf_exit_pf_wq(void) 242 { 243 if (pf2vf_resp_wq) { 244 destroy_workqueue(pf2vf_resp_wq); 245 pf2vf_resp_wq = NULL; 246 } 247 } 248