1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) 2 /* Copyright(c) 2015 - 2021 Intel Corporation */ 3 #include <linux/workqueue.h> 4 #include <linux/pci.h> 5 #include <linux/device.h> 6 #include "adf_common_drv.h" 7 #include "adf_cfg.h" 8 #include "adf_pfvf_pf_msg.h" 9 10 #define ADF_VF2PF_RATELIMIT_INTERVAL 8 11 #define ADF_VF2PF_RATELIMIT_BURST 130 12 13 static struct workqueue_struct *pf2vf_resp_wq; 14 15 struct adf_pf2vf_resp { 16 struct work_struct pf2vf_resp_work; 17 struct adf_accel_vf_info *vf_info; 18 }; 19 20 static void adf_iov_send_resp(struct work_struct *work) 21 { 22 struct adf_pf2vf_resp *pf2vf_resp = 23 container_of(work, struct adf_pf2vf_resp, pf2vf_resp_work); 24 struct adf_accel_vf_info *vf_info = pf2vf_resp->vf_info; 25 struct adf_accel_dev *accel_dev = vf_info->accel_dev; 26 u32 vf_nr = vf_info->vf_nr; 27 bool ret; 28 29 mutex_lock(&vf_info->pfvf_mig_lock); 30 ret = adf_recv_and_handle_vf2pf_msg(accel_dev, vf_nr); 31 if (ret) 32 /* re-enable interrupt on PF from this VF */ 33 adf_enable_vf2pf_interrupts(accel_dev, 1 << vf_nr); 34 mutex_unlock(&vf_info->pfvf_mig_lock); 35 36 kfree(pf2vf_resp); 37 } 38 39 void adf_schedule_vf2pf_handler(struct adf_accel_vf_info *vf_info) 40 { 41 struct adf_pf2vf_resp *pf2vf_resp; 42 43 pf2vf_resp = kzalloc(sizeof(*pf2vf_resp), GFP_ATOMIC); 44 if (!pf2vf_resp) 45 return; 46 47 pf2vf_resp->vf_info = vf_info; 48 INIT_WORK(&pf2vf_resp->pf2vf_resp_work, adf_iov_send_resp); 49 queue_work(pf2vf_resp_wq, &pf2vf_resp->pf2vf_resp_work); 50 } 51 52 static int adf_enable_sriov(struct adf_accel_dev *accel_dev) 53 { 54 struct pci_dev *pdev = accel_to_pci_dev(accel_dev); 55 int totalvfs = pci_sriov_get_totalvfs(pdev); 56 struct adf_hw_device_data *hw_data = accel_dev->hw_device; 57 struct adf_accel_vf_info *vf_info; 58 int i; 59 60 for (i = 0, vf_info = accel_dev->pf.vf_info; i < totalvfs; 61 i++, vf_info++) { 62 /* This ptr will be populated when VFs will be created */ 63 vf_info->accel_dev = accel_dev; 64 vf_info->vf_nr = i; 65 66 mutex_init(&vf_info->pf2vf_lock); 67 mutex_init(&vf_info->pfvf_mig_lock); 68 ratelimit_state_init(&vf_info->vf2pf_ratelimit, 69 ADF_VF2PF_RATELIMIT_INTERVAL, 70 ADF_VF2PF_RATELIMIT_BURST); 71 } 72 73 /* Set Valid bits in AE Thread to PCIe Function Mapping */ 74 if (hw_data->configure_iov_threads) 75 hw_data->configure_iov_threads(accel_dev, true); 76 77 /* Enable VF to PF interrupts for all VFs */ 78 adf_enable_vf2pf_interrupts(accel_dev, BIT_ULL(totalvfs) - 1); 79 80 /* 81 * Due to the hardware design, when SR-IOV and the ring arbiter 82 * are enabled all the VFs supported in hardware must be enabled in 83 * order for all the hardware resources (i.e. bundles) to be usable. 84 * When SR-IOV is enabled, each of the VFs will own one bundle. 85 */ 86 return pci_enable_sriov(pdev, totalvfs); 87 } 88 89 void adf_reenable_sriov(struct adf_accel_dev *accel_dev) 90 { 91 struct pci_dev *pdev = accel_to_pci_dev(accel_dev); 92 char cfg[ADF_CFG_MAX_VAL_LEN_IN_BYTES] = {0}; 93 unsigned long val = 0; 94 95 if (adf_cfg_get_param_value(accel_dev, ADF_GENERAL_SEC, 96 ADF_SRIOV_ENABLED, cfg)) 97 return; 98 99 if (!accel_dev->pf.vf_info) 100 return; 101 102 if (adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_CY, 103 &val, ADF_DEC)) 104 return; 105 106 if (adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_DC, 107 &val, ADF_DEC)) 108 return; 109 110 set_bit(ADF_STATUS_CONFIGURED, &accel_dev->status); 111 dev_dbg(&pdev->dev, "Re-enabling SRIOV\n"); 112 adf_enable_sriov(accel_dev); 113 } 114 115 /** 116 * adf_disable_sriov() - Disable SRIOV for the device 117 * @accel_dev: Pointer to accel device. 118 * 119 * Function disables SRIOV for the accel device. 120 * 121 * Return: 0 on success, error code otherwise. 122 */ 123 void adf_disable_sriov(struct adf_accel_dev *accel_dev) 124 { 125 struct adf_hw_device_data *hw_data = accel_dev->hw_device; 126 int totalvfs = pci_sriov_get_totalvfs(accel_to_pci_dev(accel_dev)); 127 struct adf_accel_vf_info *vf; 128 int i; 129 130 if (!accel_dev->pf.vf_info) 131 return; 132 133 adf_pf2vf_notify_restarting(accel_dev); 134 adf_pf2vf_wait_for_restarting_complete(accel_dev); 135 pci_disable_sriov(accel_to_pci_dev(accel_dev)); 136 137 /* Disable VF to PF interrupts */ 138 adf_disable_all_vf2pf_interrupts(accel_dev); 139 140 /* Clear Valid bits in AE Thread to PCIe Function Mapping */ 141 if (hw_data->configure_iov_threads) 142 hw_data->configure_iov_threads(accel_dev, false); 143 144 for (i = 0, vf = accel_dev->pf.vf_info; i < totalvfs; i++, vf++) { 145 mutex_destroy(&vf->pf2vf_lock); 146 mutex_destroy(&vf->pfvf_mig_lock); 147 } 148 149 if (!test_bit(ADF_STATUS_RESTARTING, &accel_dev->status)) { 150 kfree(accel_dev->pf.vf_info); 151 accel_dev->pf.vf_info = NULL; 152 } 153 } 154 EXPORT_SYMBOL_GPL(adf_disable_sriov); 155 156 /** 157 * adf_sriov_configure() - Enable SRIOV for the device 158 * @pdev: Pointer to PCI device. 159 * @numvfs: Number of virtual functions (VFs) to enable. 160 * 161 * Note that the @numvfs parameter is ignored and all VFs supported by the 162 * device are enabled due to the design of the hardware. 163 * 164 * Function enables SRIOV for the PCI device. 165 * 166 * Return: number of VFs enabled on success, error code otherwise. 167 */ 168 int adf_sriov_configure(struct pci_dev *pdev, int numvfs) 169 { 170 struct adf_accel_dev *accel_dev = adf_devmgr_pci_to_accel_dev(pdev); 171 int totalvfs = pci_sriov_get_totalvfs(pdev); 172 unsigned long val; 173 int ret; 174 175 if (!accel_dev) { 176 dev_err(&pdev->dev, "Failed to find accel_dev\n"); 177 return -EFAULT; 178 } 179 180 if (!device_iommu_mapped(&pdev->dev)) 181 dev_warn(&pdev->dev, "IOMMU should be enabled for SR-IOV to work correctly\n"); 182 183 if (accel_dev->pf.vf_info) { 184 dev_info(&pdev->dev, "Already enabled for this device\n"); 185 return -EINVAL; 186 } 187 188 if (adf_dev_started(accel_dev)) { 189 if (adf_devmgr_in_reset(accel_dev) || 190 adf_dev_in_use(accel_dev)) { 191 dev_err(&GET_DEV(accel_dev), "Device busy\n"); 192 return -EBUSY; 193 } 194 195 ret = adf_dev_down(accel_dev, true); 196 if (ret) 197 return ret; 198 } 199 200 if (adf_cfg_section_add(accel_dev, ADF_KERNEL_SEC)) 201 return -EFAULT; 202 val = 0; 203 if (adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, 204 ADF_NUM_CY, (void *)&val, ADF_DEC)) 205 return -EFAULT; 206 ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_DC, 207 &val, ADF_DEC); 208 if (ret) 209 return ret; 210 211 set_bit(ADF_STATUS_CONFIGURED, &accel_dev->status); 212 213 /* Allocate memory for VF info structs */ 214 accel_dev->pf.vf_info = kcalloc(totalvfs, 215 sizeof(struct adf_accel_vf_info), 216 GFP_KERNEL); 217 if (!accel_dev->pf.vf_info) 218 return -ENOMEM; 219 220 if (adf_dev_up(accel_dev, false)) { 221 dev_err(&GET_DEV(accel_dev), "Failed to start qat_dev%d\n", 222 accel_dev->accel_id); 223 return -EFAULT; 224 } 225 226 ret = adf_enable_sriov(accel_dev); 227 if (ret) 228 return ret; 229 230 val = 1; 231 adf_cfg_add_key_value_param(accel_dev, ADF_GENERAL_SEC, ADF_SRIOV_ENABLED, 232 &val, ADF_DEC); 233 234 return numvfs; 235 } 236 EXPORT_SYMBOL_GPL(adf_sriov_configure); 237 238 int __init adf_init_pf_wq(void) 239 { 240 /* Workqueue for PF2VF responses */ 241 pf2vf_resp_wq = alloc_workqueue("qat_pf2vf_resp_wq", WQ_MEM_RECLAIM, 0); 242 243 return !pf2vf_resp_wq ? -ENOMEM : 0; 244 } 245 246 void adf_exit_pf_wq(void) 247 { 248 if (pf2vf_resp_wq) { 249 destroy_workqueue(pf2vf_resp_wq); 250 pf2vf_resp_wq = NULL; 251 } 252 } 253